REG_GET_3         962 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hubp.c 	REG_GET_3(DCN_SURF0_TTU_CNTL0,
REG_GET_3         971 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hubp.c 	REG_GET_3(DCN_SURF1_TTU_CNTL0,
REG_GET_3        1004 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hubp.c 	REG_GET_3(DCHUBP_CNTL,
REG_GET_3        1160 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hubp.c 	REG_GET_3(DCN_SURF0_TTU_CNTL0,
REG_GET_3        1169 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hubp.c 	REG_GET_3(DCN_SURF1_TTU_CNTL0,
REG_GET_3        1202 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hubp.c 	REG_GET_3(DCHUBP_CNTL,
REG_GET_3         453 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_mpc.c 	REG_GET_3(MPCC_STATUS[mpcc_id],
REG_GET_3         289 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_optc.c 	REG_GET_3(OPTC_DATA_SOURCE_SELECT,
REG_GET_3          87 drivers/gpu/drm/amd/display/dc/gpio/hw_ddc.c 	regval = REG_GET_3(gpio.MASK_reg,