REG_GET 61 drivers/gpu/drm/amd/display/dc/bios/bios_parser_helper.c REG_GET(BIOS_SCRATCH_6, S6_ACC_MODE, &acc_mode); REG_GET 138 drivers/gpu/drm/amd/display/dc/clk_mgr/dce100/dce_clk_mgr.c REG_GET(DPREFCLK_CNTL, DPREFCLK_SRC_SEL, &dprefclk_src_sel); REG_GET 143 drivers/gpu/drm/amd/display/dc/clk_mgr/dce100/dce_clk_mgr.c REG_GET(DENTIST_DISPCLK_CNTL, DENTIST_DPREFCLK_WDIVIDER, &dprefclk_wdivider); REG_GET 148 drivers/gpu/drm/amd/display/dc/clk_mgr/dcn21/rn_clk_mgr.c REG_GET(CLK1_CLK_PLL_REQ, FbMult_frac, &fbmult_frac_val); /* 16 bit fractional part*/ REG_GET 149 drivers/gpu/drm/amd/display/dc/clk_mgr/dcn21/rn_clk_mgr.c REG_GET(CLK1_CLK_PLL_REQ, FbMult_int, &fbmult_int_val); /* 8 bit integer part */ REG_GET 95 drivers/gpu/drm/amd/display/dc/dce/dce_abm.c REG_GET(BL_PWM_PERIOD_CNTL, BL_PWM_PERIOD, &bl_period); REG_GET 96 drivers/gpu/drm/amd/display/dc/dce/dce_abm.c REG_GET(BL_PWM_PERIOD_CNTL, BL_PWM_PERIOD_BITCNT, &bl_int_count); REG_GET 99 drivers/gpu/drm/amd/display/dc/dce/dce_abm.c REG_GET(BL_PWM_CNTL, BL_ACTIVE_INT_FRAC_CNT, (uint32_t *)(&bl_pwm)); REG_GET 100 drivers/gpu/drm/amd/display/dc/dce/dce_abm.c REG_GET(BL_PWM_CNTL, BL_PWM_FRACTIONAL_EN, &fractional_duty_cycle_en); REG_GET 350 drivers/gpu/drm/amd/display/dc/dce/dce_abm.c REG_GET(LVTMA_PWRSEQ_REF_DIV, BL_PWM_REF_DIV, REG_GET 364 drivers/gpu/drm/amd/display/dc/dce/dce_abm.c REG_GET(BL_PWM_CNTL, BL_ACTIVE_INT_FRAC_CNT, &value); REG_GET 392 drivers/gpu/drm/amd/display/dc/dce/dce_abm.c REG_GET(LVTMA_PWRSEQ_REF_DIV, BL_PWM_REF_DIV, REG_GET 268 drivers/gpu/drm/amd/display/dc/dce/dce_aux.c *sw_status = REG_GET(AUX_SW_STATUS, AUX_SW_REPLY_BYTE_COUNT, REG_GET 284 drivers/gpu/drm/amd/display/dc/dce/dce_aux.c REG_GET(AUX_SW_DATA, AUX_SW_DATA, &reply_result_32); REG_GET 302 drivers/gpu/drm/amd/display/dc/dce/dce_aux.c REG_GET(AUX_SW_DATA, AUX_SW_DATA, &aux_sw_data_val); REG_GET 157 drivers/gpu/drm/amd/display/dc/dce/dce_clk_mgr.c REG_GET(DPREFCLK_CNTL, DPREFCLK_SRC_SEL, &dprefclk_src_sel); REG_GET 162 drivers/gpu/drm/amd/display/dc/dce/dce_clk_mgr.c REG_GET(DENTIST_DISPCLK_CNTL, DENTIST_DPREFCLK_WDIVIDER, &dprefclk_wdivider); REG_GET 486 drivers/gpu/drm/amd/display/dc/dce/dce_clock_source.c REG_GET(PLL_CNTL, PLL_REF_DIV_SRC, &field); REG_GET 276 drivers/gpu/drm/amd/display/dc/dce/dce_dmcu.c REG_GET(DMCU_STATUS, UC_IN_RESET, &dmcu_uc_reset); REG_GET 77 drivers/gpu/drm/amd/display/dc/dce/dce_i2c_hw.c REG_GET(DC_I2C_SW_STATUS, DC_I2C_SW_STATUS, &i2c_sw_status); REG_GET 108 drivers/gpu/drm/amd/display/dc/dce/dce_i2c_hw.c REG_GET(SPEED, DC_I2C_DDC1_PRESCALE, &pre_scale); REG_GET 138 drivers/gpu/drm/amd/display/dc/dce/dce_i2c_hw.c REG_GET(DC_I2C_DATA, DC_I2C_DATA, &i2c_data); REG_GET 150 drivers/gpu/drm/amd/display/dc/dce/dce_i2c_hw.c REG_GET(HW_STATUS, DC_I2C_DDC1_HW_STATUS, &i2c_hw_status); REG_GET 154 drivers/gpu/drm/amd/display/dc/dce/dce_i2c_hw.c REG_GET(DC_I2C_ARBITRATION, DC_I2C_REG_RW_CNTL_STATUS, &arbitrate); REG_GET 165 drivers/gpu/drm/amd/display/dc/dce/dce_i2c_hw.c REG_GET(DC_I2C_SW_STATUS, DC_I2C_SW_STATUS, &i2c_sw_status); REG_GET 359 drivers/gpu/drm/amd/display/dc/dce/dce_i2c_hw.c REG_GET(DC_I2C_SW_STATUS, DC_I2C_SW_STATUS, &i2c_sw_status); REG_GET 658 drivers/gpu/drm/amd/display/dc/dce/dce_i2c_hw.c REG_GET(MICROSECOND_TIME_BASE_DIV, XTAL_REF_DIV, &xtal_ref_div); REG_GET 553 drivers/gpu/drm/amd/display/dc/dce/dce_link_encoder.c REG_GET(DIG_BE_EN_CNTL, DIG_ENABLE, &value); REG_GET 1335 drivers/gpu/drm/amd/display/dc/dce/dce_link_encoder.c REG_GET(DP_MSE_SAT_UPDATE, REG_GET 1338 drivers/gpu/drm/amd/display/dc/dce/dce_link_encoder.c REG_GET(DP_MSE_SAT_UPDATE, REG_GET 1358 drivers/gpu/drm/amd/display/dc/dce/dce_link_encoder.c REG_GET(DIG_BE_CNTL, DIG_FE_SOURCE_SELECT, &field); REG_GET 588 drivers/gpu/drm/amd/display/dc/dce/dce_mem_input.c dmif_buffer_control = REG_GET(DMIF_BUFFER_CONTROL, REG_GET 625 drivers/gpu/drm/amd/display/dc/dce/dce_mem_input.c dmif_buffer_control = REG_GET(DMIF_BUFFER_CONTROL, REG_GET 682 drivers/gpu/drm/amd/display/dc/dce/dce_mem_input.c REG_GET(GRPH_UPDATE, GRPH_SURFACE_UPDATE_PENDING, &update_pending); REG_GET 440 drivers/gpu/drm/amd/display/dc/dce/dce_opp.c REG_GET(CONTROL, REG_GET 933 drivers/gpu/drm/amd/display/dc/dce/dce_stream_encoder.c REG_GET(DP_VID_STREAM_CNTL, DP_VID_STREAM_ENABLE, ®1); REG_GET 1611 drivers/gpu/drm/amd/display/dc/dce/dce_stream_encoder.c REG_GET(DIG_FE_CNTL, DIG_SOURCE_SELECT, &tg_inst); REG_GET 1156 drivers/gpu/drm/amd/display/dc/dce/dce_transform.c REG_GET(DCFE_MEM_PWR_STATUS, REG_GET 1164 drivers/gpu/drm/amd/display/dc/dce/dce_transform.c REG_GET(DCFE_MEM_LIGHT_SLEEP_CNTL, REG_GET 410 drivers/gpu/drm/amd/display/dc/dce100/dce100_resource.c REG_GET(DC_PINSTRAPS, DC_PINSTRAPS_AUDIO, &straps->dc_pinstraps_audio); REG_GET 702 drivers/gpu/drm/amd/display/dc/dce110/dce110_hw_sequencer.c REG_GET(LVTMA_PWRSEQ_CNTL, LVTMA_BLON, &value); REG_GET 712 drivers/gpu/drm/amd/display/dc/dce110/dce110_hw_sequencer.c REG_GET(LVTMA_PWRSEQ_STATE, LVTMA_PWRSEQ_TARGET_STATE_R, &pwr_seq_state); REG_GET 451 drivers/gpu/drm/amd/display/dc/dce110/dce110_resource.c REG_GET(DC_PINSTRAPS, DC_PINSTRAPS_AUDIO, &straps->dc_pinstraps_audio); REG_GET 428 drivers/gpu/drm/amd/display/dc/dce112/dce112_resource.c REG_GET(DC_PINSTRAPS, DC_PINSTRAPS_AUDIO, &straps->dc_pinstraps_audio); REG_GET 257 drivers/gpu/drm/amd/display/dc/dce120/dce120_hw_sequencer.c REG_GET(MC_VM_XGMI_LFB_CNTL, PF_MAX_REGION, &pf_max_region); REG_GET 442 drivers/gpu/drm/amd/display/dc/dce80/dce80_resource.c REG_GET(DC_PINSTRAPS, DC_PINSTRAPS_AUDIO, &straps->dc_pinstraps_audio); REG_GET 99 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dpp.c REG_GET(DPP_CONTROL, REG_GET 101 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dpp.c REG_GET(CM_IGAM_CONTROL, REG_GET 103 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dpp.c REG_GET(CM_IGAM_CONTROL, REG_GET 105 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dpp.c REG_GET(CM_DGAM_CONTROL, REG_GET 107 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dpp.c REG_GET(CM_RGAM_CONTROL, REG_GET 109 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dpp.c REG_GET(CM_GAMUT_REMAP_CONTROL, REG_GET 224 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dpp_cm.c REG_GET(CM_TEST_DEBUG_DATA, REG_GET 479 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dpp_cm.c REG_GET(CM_TEST_DEBUG_DATA, REG_GET 656 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dpp_cm.c REG_GET(CM_IGAM_LUT_RW_CONTROL, CM_IGAM_DGAM_CONFIG_STATUS, REG_GET 750 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dpp_cm.c REG_GET(CM_IGAM_LUT_RW_CONTROL, CM_IGAM_DGAM_CONFIG_STATUS, REG_GET 820 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dpp_cm.c REG_GET(CM_IGAM_CONTROL, CM_IGAM_LUT_MODE, &ram_num); REG_GET 112 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hubbub.c REG_GET(DCHUBBUB_ARB_DRAM_STATE_CNTL, REG_GET 701 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hubbub.c REG_GET(DCHUBBUB_ARB_WATERMARK_CHANGE_CNTL, REG_GET 95 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hubp.c REG_GET(DCHUBP_CNTL, REG_GET 727 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hubp.c REG_GET(DCSURF_FLIP_CONTROL, REG_GET 730 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hubp.c REG_GET(DCSURF_SURFACE_EARLIEST_INUSE, REG_GET 733 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hubp.c REG_GET(DCSURF_SURFACE_EARLIEST_INUSE_HIGH, REG_GET 855 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hubp.c REG_GET(HUBPRET_CONTROL, REG_GET 868 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hubp.c REG_GET(BLANK_OFFSET_1, REG_GET 871 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hubp.c REG_GET(DST_DIMENSIONS, REG_GET 891 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hubp.c REG_GET(REF_FREQ_TO_PIX_FREQ, REG_GET 895 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hubp.c REG_GET(VBLANK_PARAMETERS_1, REG_GET 898 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hubp.c REG_GET(VBLANK_PARAMETERS_3, REG_GET 902 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hubp.c REG_GET(NOM_PARAMETERS_0, REG_GET 906 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hubp.c REG_GET(NOM_PARAMETERS_1, REG_GET 909 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hubp.c REG_GET(NOM_PARAMETERS_4, REG_GET 912 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hubp.c REG_GET(NOM_PARAMETERS_5, REG_GET 924 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hubp.c REG_GET(PREFETCH_SETTINS_C, REG_GET 927 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hubp.c REG_GET(PREFETCH_SETTINGS_C, REG_GET 930 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hubp.c REG_GET(VBLANK_PARAMETERS_2, REG_GET 933 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hubp.c REG_GET(VBLANK_PARAMETERS_4, REG_GET 937 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hubp.c REG_GET(NOM_PARAMETERS_2, REG_GET 941 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hubp.c REG_GET(NOM_PARAMETERS_3, REG_GET 944 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hubp.c REG_GET(NOM_PARAMETERS_6, REG_GET 947 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hubp.c REG_GET(NOM_PARAMETERS_7, REG_GET 967 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hubp.c REG_GET(DCN_SURF0_TTU_CNTL1, REG_GET 976 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hubp.c REG_GET(DCN_SURF1_TTU_CNTL1, REG_GET 981 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hubp.c REG_GET(DCSURF_SURFACE_CONFIG, REG_GET 984 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hubp.c REG_GET(DCSURF_SURFACE_EARLIEST_INUSE_HIGH, REG_GET 987 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hubp.c REG_GET(DCSURF_SURFACE_EARLIEST_INUSE, REG_GET 998 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hubp.c REG_GET(DCSURF_TILING_CONFIG, REG_GET 1001 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hubp.c REG_GET(DCSURF_SURFACE_CONTROL, REG_GET 1009 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hubp.c REG_GET(DCN_GLOBAL_TTU_CNTL, REG_GET 471 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c REG_GET(D1VGA_CONTROL, D1VGA_MODE_ENABLE, &in_vga1_mode); REG_GET 472 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c REG_GET(D2VGA_CONTROL, D2VGA_MODE_ENABLE, &in_vga2_mode); REG_GET 473 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c REG_GET(D3VGA_CONTROL, D3VGA_MODE_ENABLE, &in_vga3_mode); REG_GET 474 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c REG_GET(D4VGA_CONTROL, D4VGA_MODE_ENABLE, &in_vga4_mode); REG_GET 1750 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c REG_GET(MC_VM_SYSTEM_APERTURE_DEFAULT_ADDR_MSB, REG_GET 1752 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c REG_GET(MC_VM_SYSTEM_APERTURE_DEFAULT_ADDR_LSB, REG_GET 1755 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c REG_GET(MC_VM_SYSTEM_APERTURE_LOW_ADDR, REG_GET 1758 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c REG_GET(MC_VM_SYSTEM_APERTURE_HIGH_ADDR, REG_GET 1776 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c REG_GET(DCHUBBUB_SDPIF_FB_BASE, SDPIF_FB_BASE, &fb_base_value); REG_GET 1777 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c REG_GET(DCHUBBUB_SDPIF_FB_OFFSET, SDPIF_FB_OFFSET, &fb_offset_value); REG_GET 1779 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c REG_GET(VM_CONTEXT0_PAGE_TABLE_BASE_ADDR_HI32, REG_GET 1781 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c REG_GET(VM_CONTEXT0_PAGE_TABLE_BASE_ADDR_LO32, REG_GET 1784 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c REG_GET(VM_CONTEXT0_PAGE_TABLE_START_ADDR_HI32, REG_GET 1786 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c REG_GET(VM_CONTEXT0_PAGE_TABLE_START_ADDR_LO32, REG_GET 1789 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c REG_GET(VM_CONTEXT0_PAGE_TABLE_END_ADDR_HI32, REG_GET 1791 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c REG_GET(VM_CONTEXT0_PAGE_TABLE_END_ADDR_LO32, REG_GET 1794 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c REG_GET(VM_L2_PROTECTION_FAULT_DEFAULT_ADDR_HI32, REG_GET 1796 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c REG_GET(VM_L2_PROTECTION_FAULT_DEFAULT_ADDR_LO32, REG_GET 456 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_link_encoder.c REG_GET(DIG_BE_CNTL, DIG_FE_SOURCE_SELECT, &value); REG_GET 541 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_link_encoder.c REG_GET(DIG_BE_EN_CNTL, DIG_ENABLE, &value); REG_GET 1302 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_link_encoder.c REG_GET(DP_MSE_SAT_UPDATE, REG_GET 1305 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_link_encoder.c REG_GET(DP_MSE_SAT_UPDATE, REG_GET 1325 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_link_encoder.c REG_GET(DIG_BE_CNTL, DIG_FE_SOURCE_SELECT, &field); REG_GET 1407 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_link_encoder.c REG_GET(DIG_BE_CNTL, DIG_MODE, &value); REG_GET 133 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_mpc.c REG_GET(MPCC_TOP_SEL[mpcc_id], MPCC_TOP_SEL, &top_sel); REG_GET 134 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_mpc.c REG_GET(MPCC_OPP_ID[mpcc_id], MPCC_OPP_ID, &opp_id); REG_GET 135 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_mpc.c REG_GET(MPCC_STATUS[mpcc_id], MPCC_IDLE, &idle); REG_GET 147 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_mpc.c REG_GET(MPCC_TOP_SEL[mpcc_id], REG_GET 372 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_mpc.c REG_GET(MPCC_OPP_ID[mpcc_id], MPCC_OPP_ID, &opp_id); REG_GET 398 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_mpc.c REG_GET(MUX[tree->opp_id], MPC_OUT_MUX, &out_mux); REG_GET 402 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_mpc.c REG_GET(MPCC_OPP_ID[mpcc_id], MPCC_OPP_ID, &opp_id); REG_GET 403 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_mpc.c REG_GET(MPCC_TOP_SEL[mpcc_id], MPCC_TOP_SEL, &top_sel); REG_GET 404 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_mpc.c REG_GET(MPCC_BOT_SEL[mpcc_id], MPCC_BOT_SEL, &bot_sel); REG_GET 418 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_mpc.c REG_GET(MPCC_OPP_ID[bot_mpcc_id], MPCC_OPP_ID, &opp_id); REG_GET 419 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_mpc.c REG_GET(MPCC_TOP_SEL[bot_mpcc_id], MPCC_TOP_SEL, &top_sel); REG_GET 438 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_mpc.c REG_GET(MPCC_OPP_ID[mpcc_inst], MPCC_OPP_ID, &s->opp_id); REG_GET 439 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_mpc.c REG_GET(MPCC_TOP_SEL[mpcc_inst], MPCC_TOP_SEL, &s->dpp_id); REG_GET 440 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_mpc.c REG_GET(MPCC_BOT_SEL[mpcc_inst], MPCC_BOT_SEL, &s->bot_mpcc_id); REG_GET 579 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_optc.c REG_GET(OTG_STATUS_FRAME_COUNT, REG_GET 627 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_optc.c REG_GET(OTG_NOM_VERT_POSITION, REG_GET 651 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_optc.c REG_GET(OTG_FORCE_COUNT_NOW_CNTL, REG_GET 654 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_optc.c REG_GET(OTG_VERT_SYNC_CONTROL, REG_GET 678 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_optc.c REG_GET(OTG_V_SYNC_A_CNTL, REG_GET 1223 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_optc.c REG_GET(OTG_STEREO_STATUS, REG_GET 1294 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_optc.c REG_GET(OTG_CONTROL, REG_GET 1301 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_optc.c REG_GET(OTG_V_SYNC_A_CNTL, REG_GET 1304 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_optc.c REG_GET(OTG_V_TOTAL, REG_GET 1307 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_optc.c REG_GET(OTG_V_TOTAL_MAX, REG_GET 1310 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_optc.c REG_GET(OTG_V_TOTAL_MIN, REG_GET 1313 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_optc.c REG_GET(OTG_V_TOTAL_CONTROL, REG_GET 1316 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_optc.c REG_GET(OTG_V_TOTAL_CONTROL, REG_GET 1331 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_optc.c REG_GET(OTG_H_SYNC_A_CNTL, REG_GET 1334 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_optc.c REG_GET(OTG_H_TOTAL, REG_GET 1337 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_optc.c REG_GET(OPTC_INPUT_GLOBAL_CONTROL, REG_GET 1353 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_optc.c REG_GET(OTG_CONTROL, REG_GET 1390 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_optc.c REG_GET(OTG_CONTROL, OTG_MASTER_EN, &otg_enabled); REG_GET 1401 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_optc.c REG_GET(OPTC_INPUT_GLOBAL_CONTROL, REG_GET 1458 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_optc.c REG_GET(OTG_CRC_CNTL, OTG_CRC_EN, &field); REG_GET 1468 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_optc.c REG_GET(OTG_CRC0_DATA_B, REG_GET 892 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_stream_encoder.c REG_GET(DP_VID_STREAM_CNTL, DP_VID_STREAM_ENABLE, ®1); REG_GET 1551 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_stream_encoder.c REG_GET(DIG_FE_CNTL, DIG_SOURCE_SELECT, &tg_inst); REG_GET 56 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dpp.c REG_GET(DPP_CONTROL, REG_GET 58 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dpp.c REG_GET(CM_DGAM_CONTROL, REG_GET 63 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dpp.c REG_GET(CM_GAMUT_REMAP_CONTROL, REG_GET 72 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dpp_cm.c REG_GET(CM_DGAM_LUT_WRITE_EN_MASK, CM_DGAM_CONFIG_STATUS, REG_GET 295 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dpp_cm.c REG_GET(CM_BLNDGAM_LUT_WRITE_EN_MASK, REG_GET 388 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dpp_cm.c REG_GET(CM_SHAPER_LUT_WRITE_EN_MASK, REG_GET 792 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dpp_cm.c REG_GET(CM_3DLUT_MODE, CM_3DLUT_SIZE, &lut_size); REG_GET 158 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dsc.c REG_GET(DSC_TOP_CONTROL, DSC_CLOCK_EN, &s->dsc_clock_en); REG_GET 159 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dsc.c REG_GET(DSCC_PPS_CONFIG3, SLICE_WIDTH, &s->dsc_slice_width); REG_GET 160 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dsc.c REG_GET(DSCC_PPS_CONFIG1, BITS_PER_PIXEL, &s->dsc_bytes_per_pixel); REG_GET 177 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dwb.c REG_GET(CNV_UPDATE, CNV_UPDATE_LOCK, &pre_locked); REG_GET 204 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dwb.c REG_GET(WB_ENABLE, WB_ENABLE, &wb_enabled); REG_GET 205 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dwb.c REG_GET(CNV_MODE, CNV_FRAME_CAPTURE_EN, &cnv_frame_capture_en); REG_GET 673 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hubp.c REG_GET(DMDATA_STATUS, DMDATA_DONE, &status); REG_GET 859 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hubp.c REG_GET(DCSURF_FLIP_CONTROL2, SURFACE_TRIPLE_BUFFER_ENABLE, &triple_buffer_en); REG_GET 873 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hubp.c REG_GET(DCSURF_FLIP_CONTROL2, SURFACE_TRIPLE_BUFFER_ENABLE, &triple_buffer_en); REG_GET 891 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hubp.c REG_GET(DCSURF_FLIP_CONTROL, REG_GET 894 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hubp.c REG_GET(DCSURF_SURFACE_EARLIEST_INUSE, REG_GET 897 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hubp.c REG_GET(DCSURF_SURFACE_EARLIEST_INUSE_HIGH, REG_GET 1053 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hubp.c REG_GET(HUBPRET_CONTROL, REG_GET 1066 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hubp.c REG_GET(BLANK_OFFSET_1, REG_GET 1069 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hubp.c REG_GET(DST_DIMENSIONS, REG_GET 1089 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hubp.c REG_GET(REF_FREQ_TO_PIX_FREQ, REG_GET 1093 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hubp.c REG_GET(VBLANK_PARAMETERS_1, REG_GET 1096 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hubp.c REG_GET(VBLANK_PARAMETERS_3, REG_GET 1100 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hubp.c REG_GET(NOM_PARAMETERS_0, REG_GET 1104 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hubp.c REG_GET(NOM_PARAMETERS_1, REG_GET 1107 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hubp.c REG_GET(NOM_PARAMETERS_4, REG_GET 1110 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hubp.c REG_GET(NOM_PARAMETERS_5, REG_GET 1122 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hubp.c REG_GET(PREFETCH_SETTINS_C, REG_GET 1125 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hubp.c REG_GET(PREFETCH_SETTINGS_C, REG_GET 1128 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hubp.c REG_GET(VBLANK_PARAMETERS_2, REG_GET 1131 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hubp.c REG_GET(VBLANK_PARAMETERS_4, REG_GET 1135 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hubp.c REG_GET(NOM_PARAMETERS_2, REG_GET 1139 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hubp.c REG_GET(NOM_PARAMETERS_3, REG_GET 1142 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hubp.c REG_GET(NOM_PARAMETERS_6, REG_GET 1145 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hubp.c REG_GET(NOM_PARAMETERS_7, REG_GET 1165 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hubp.c REG_GET(DCN_SURF0_TTU_CNTL1, REG_GET 1174 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hubp.c REG_GET(DCN_SURF1_TTU_CNTL1, REG_GET 1179 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hubp.c REG_GET(DCSURF_SURFACE_CONFIG, REG_GET 1182 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hubp.c REG_GET(DCSURF_SURFACE_EARLIEST_INUSE_HIGH, REG_GET 1185 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hubp.c REG_GET(DCSURF_SURFACE_EARLIEST_INUSE, REG_GET 1196 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hubp.c REG_GET(DCSURF_TILING_CONFIG, REG_GET 1199 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hubp.c REG_GET(DCSURF_SURFACE_CONTROL, REG_GET 1207 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hubp.c REG_GET(DCN_GLOBAL_TTU_CNTL, REG_GET 262 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hwseq.c REG_GET(DC_IP_REQUEST_CNTL, IP_REQUEST_EN, &org_ip_request_cntl); REG_GET 190 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_link_encoder.c REG_GET(DP_DPHY_CNTL, DPHY_FEC_ACTIVE_STATUS, &active); REG_GET 203 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_link_encoder.c REG_GET(DP_DPHY_CNTL, DPHY_FEC_EN, &s->dphy_fec_en); REG_GET 204 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_link_encoder.c REG_GET(DP_DPHY_CNTL, DPHY_FEC_READY_SHADOW, &s->dphy_fec_ready_shadow); REG_GET 205 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_link_encoder.c REG_GET(DP_DPHY_CNTL, DPHY_FEC_ACTIVE_STATUS, &s->dphy_fec_active_status); REG_GET 266 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_mpc.c REG_GET(MPCC_OGAM_LUT_RAM_CONTROL[mpcc_id], REG_GET 436 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_mpc.c REG_GET(MPCC_STATUS[id], MPCC_DISABLED, &mpc_disabled); REG_GET 450 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_mpc.c REG_GET(MPCC_TOP_SEL[mpcc_id], REG_GET 302 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_opp.c REG_GET(DPG_STATUS, REG_GET 359 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_optc.c REG_GET(OTG_V_BLANK_START_END, OTG_V_BLANK_START, &v_blank_start); REG_GET 361 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_optc.c REG_GET(OTG_H_BLANK_START_END, OTG_H_BLANK_START, &h_blank_start); REG_GET 351 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_stream_encoder.c REG_GET(DP_DSC_CNTL, DP_DSC_MODE, &s->dsc_mode); REG_GET 353 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_stream_encoder.c REG_GET(DP_DSC_CNTL, DP_DSC_SLICE_WIDTH, &s->dsc_slice_width); REG_GET 354 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_stream_encoder.c REG_GET(DP_SEC_CNTL6, DP_SEC_GSP7_LINE_NUM, &s->sec_gsp_pps_line_num); REG_GET 356 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_stream_encoder.c REG_GET(DP_MSA_VBID_MISC, DP_VBID6_LINE_REFERENCE, &s->vbid6_line_reference); REG_GET 357 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_stream_encoder.c REG_GET(DP_MSA_VBID_MISC, DP_VBID6_LINE_NUM, &s->vbid6_line_num); REG_GET 359 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_stream_encoder.c REG_GET(DP_SEC_CNTL, DP_SEC_GSP7_ENABLE, &s->sec_gsp_pps_enable); REG_GET 360 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_stream_encoder.c REG_GET(DP_SEC_CNTL, DP_SEC_STREAM_ENABLE, &s->sec_stream_enable); REG_GET 432 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_stream_encoder.c REG_GET(DP_SEC_METADATA_TRANSMISSION, REG_GET 58 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_vmid.c REG_GET(PAGE_TABLE_BASE_ADDR_LO32, REG_GET 83 drivers/gpu/drm/amd/display/dc/dcn21/dcn21_hubbub.c REG_GET(DCHVM_RIOMMU_STAT0, RIOMMU_ACTIVE, &riommu_active); REG_GET 522 drivers/gpu/drm/amd/display/dc/dcn21/dcn21_hubbub.c REG_GET(DCHUBBUB_ARB_DATA_URGENCY_WATERMARK_A, REG_GET 525 drivers/gpu/drm/amd/display/dc/dcn21/dcn21_hubbub.c REG_GET(DCHUBBUB_ARB_ALLOW_SR_ENTER_WATERMARK_A, REG_GET 528 drivers/gpu/drm/amd/display/dc/dcn21/dcn21_hubbub.c REG_GET(DCHUBBUB_ARB_ALLOW_SR_EXIT_WATERMARK_A, REG_GET 531 drivers/gpu/drm/amd/display/dc/dcn21/dcn21_hubbub.c REG_GET(DCHUBBUB_ARB_ALLOW_DRAM_CLK_CHANGE_WATERMARK_A, REG_GET 536 drivers/gpu/drm/amd/display/dc/dcn21/dcn21_hubbub.c REG_GET(DCHUBBUB_ARB_DATA_URGENCY_WATERMARK_B, REG_GET 539 drivers/gpu/drm/amd/display/dc/dcn21/dcn21_hubbub.c REG_GET(DCHUBBUB_ARB_ALLOW_SR_ENTER_WATERMARK_B, REG_GET 542 drivers/gpu/drm/amd/display/dc/dcn21/dcn21_hubbub.c REG_GET(DCHUBBUB_ARB_ALLOW_SR_EXIT_WATERMARK_B, REG_GET 545 drivers/gpu/drm/amd/display/dc/dcn21/dcn21_hubbub.c REG_GET(DCHUBBUB_ARB_ALLOW_DRAM_CLK_CHANGE_WATERMARK_B, REG_GET 550 drivers/gpu/drm/amd/display/dc/dcn21/dcn21_hubbub.c REG_GET(DCHUBBUB_ARB_DATA_URGENCY_WATERMARK_C, REG_GET 553 drivers/gpu/drm/amd/display/dc/dcn21/dcn21_hubbub.c REG_GET(DCHUBBUB_ARB_ALLOW_SR_ENTER_WATERMARK_C, REG_GET 556 drivers/gpu/drm/amd/display/dc/dcn21/dcn21_hubbub.c REG_GET(DCHUBBUB_ARB_ALLOW_SR_EXIT_WATERMARK_C, REG_GET 559 drivers/gpu/drm/amd/display/dc/dcn21/dcn21_hubbub.c REG_GET(DCHUBBUB_ARB_ALLOW_DRAM_CLK_CHANGE_WATERMARK_C, REG_GET 564 drivers/gpu/drm/amd/display/dc/dcn21/dcn21_hubbub.c REG_GET(DCHUBBUB_ARB_DATA_URGENCY_WATERMARK_D, REG_GET 567 drivers/gpu/drm/amd/display/dc/dcn21/dcn21_hubbub.c REG_GET(DCHUBBUB_ARB_ALLOW_SR_ENTER_WATERMARK_D, REG_GET 570 drivers/gpu/drm/amd/display/dc/dcn21/dcn21_hubbub.c REG_GET(DCHUBBUB_ARB_ALLOW_SR_EXIT_WATERMARK_D, REG_GET 573 drivers/gpu/drm/amd/display/dc/dcn21/dcn21_hubbub.c REG_GET(DCHUBBUB_ARB_ALLOW_DRAM_CLK_CHANGE_WATERMARK_D, REG_GET 78 drivers/gpu/drm/amd/display/dc/dcn21/dcn21_hubp.c REG_GET(VBLANK_PARAMETERS_5, REFCYC_PER_VM_GROUP_VBLANK, &cur_value); REG_GET 83 drivers/gpu/drm/amd/display/dc/dcn21/dcn21_hubp.c REG_GET(VBLANK_PARAMETERS_6, REG_GET 90 drivers/gpu/drm/amd/display/dc/dcn21/dcn21_hubp.c REG_GET(FLIP_PARAMETERS_3, REFCYC_PER_VM_GROUP_FLIP, &cur_value); REG_GET 95 drivers/gpu/drm/amd/display/dc/dcn21/dcn21_hubp.c REG_GET(FLIP_PARAMETERS_4, REFCYC_PER_VM_REQ_FLIP, &cur_value); REG_GET 45 drivers/gpu/drm/amd/display/dc/gpio/hw_gpio.c REG_GET(MASK_reg, MASK, &gpio->store.mask); REG_GET 46 drivers/gpu/drm/amd/display/dc/gpio/hw_gpio.c REG_GET(A_reg, A, &gpio->store.a); REG_GET 47 drivers/gpu/drm/amd/display/dc/gpio/hw_gpio.c REG_GET(EN_reg, EN, &gpio->store.en); REG_GET 86 drivers/gpu/drm/amd/display/dc/gpio/hw_gpio.c REG_GET(Y_reg, Y, value); REG_GET 94 drivers/gpu/drm/amd/display/dc/gpio/hw_hpd.c REG_GET(int_status, REG_GET 49 drivers/gpu/drm/amd/display/dc/inc/reg_helper.h #ifdef REG_GET REG_GET 373 drivers/gpu/drm/omapdrm/dss/dispc.c return REG_GET(dispc, rfld.reg, rfld.high, rfld.low); REG_GET 739 drivers/gpu/drm/omapdrm/dss/dispc.c return REG_GET(dispc, DISPC_CONTROL2, 6, 6) == 1; REG_GET 747 drivers/gpu/drm/omapdrm/dss/dispc.c enable = REG_GET(dispc, DISPC_OVL_ATTRIBUTES(plane), 0, 0) == 1; REG_GET 752 drivers/gpu/drm/omapdrm/dss/dispc.c go = REG_GET(dispc, DISPC_CONTROL2, 6, 6) == 1; REG_GET 1383 drivers/gpu/drm/omapdrm/dss/dispc.c size = REG_GET(dispc, DISPC_OVL_FIFO_SIZE_STATUS(fifo), REG_GET 1481 drivers/gpu/drm/omapdrm/dss/dispc.c REG_GET(dispc, DISPC_OVL_FIFO_THRESHOLD(plane), REG_GET 1483 drivers/gpu/drm/omapdrm/dss/dispc.c REG_GET(dispc, DISPC_OVL_FIFO_THRESHOLD(plane), REG_GET 3331 drivers/gpu/drm/omapdrm/dss/dispc.c lcd = REG_GET(dispc, DISPC_DIVISORo(channel), 23, 16); REG_GET 3745 drivers/gpu/drm/omapdrm/dss/dispc.c cinfo->lck_div = REG_GET(dispc, DISPC_DIVISORo(channel), 23, 16); REG_GET 3746 drivers/gpu/drm/omapdrm/dss/dispc.c cinfo->pck_div = REG_GET(dispc, DISPC_DIVISORo(channel), 7, 0); REG_GET 4644 drivers/gpu/drm/omapdrm/dss/dispc.c gatestate = REG_GET(dispc, DISPC_CONFIG, 8, 4); REG_GET 4908 drivers/gpu/drm/omapdrm/dss/dispc.c if (REG_GET(dispc, DISPC_CONFIG, 2, 1) != OMAP_DSS_LOAD_FRAME_ONLY) { REG_GET 499 drivers/gpu/drm/omapdrm/dss/dsi.c if (REG_GET(dsi, idx, bitnum, bitnum) == value) REG_GET 506 drivers/gpu/drm/omapdrm/dss/dsi.c if (REG_GET(dsi, idx, bitnum, bitnum) == value) REG_GET 1658 drivers/gpu/drm/omapdrm/dss/dsi.c val = REG_GET(dsi, DSI_GNQ, 14, 12); /* VP1_LINE_BUFFER_SIZE */ REG_GET 2221 drivers/gpu/drm/omapdrm/dss/dsi.c return REG_GET(dsi, DSI_VC_CTRL(channel), 0, 0); REG_GET 2232 drivers/gpu/drm/omapdrm/dss/dsi.c if (REG_GET(dsi, DSI_VC_TE(channel), bit, bit) == 0) REG_GET 2254 drivers/gpu/drm/omapdrm/dss/dsi.c if (REG_GET(dsi, DSI_VC_TE(channel), bit, bit)) { REG_GET 2281 drivers/gpu/drm/omapdrm/dss/dsi.c if (REG_GET(dsi, DSI_VC_CTRL(channel), 5, 5) == 0) REG_GET 2300 drivers/gpu/drm/omapdrm/dss/dsi.c if (REG_GET(dsi, DSI_VC_CTRL(channel), 5, 5)) { REG_GET 2447 drivers/gpu/drm/omapdrm/dss/dsi.c while (REG_GET(dsi, DSI_VC_CTRL(channel), 20, 20)) { REG_GET 2498 drivers/gpu/drm/omapdrm/dss/dsi.c while (REG_GET(dsi, DSI_VC_CTRL(channel), 20, 20)) { REG_GET 2532 drivers/gpu/drm/omapdrm/dss/dsi.c if (REG_GET(dsi, DSI_VC_CTRL(channel), 20, 20)) { REG_GET 2780 drivers/gpu/drm/omapdrm/dss/dsi.c if (REG_GET(dsi, DSI_VC_CTRL(channel), 20, 20)) { REG_GET 2870 drivers/gpu/drm/omapdrm/dss/dsi.c if (REG_GET(dsi, DSI_VC_CTRL(channel), 20, 20) == 0) { REG_GET 3052 drivers/gpu/drm/omapdrm/dss/dsi.c if (REG_GET(dsi, DSI_CLK_CTRL, 13, 13)) { REG_GET 3070 drivers/gpu/drm/omapdrm/dss/dsi.c if (REG_GET(dsi, DSI_COMPLEXIO_CFG2, 16, 16)) { /* HS_BUSY */ REG_GET 3075 drivers/gpu/drm/omapdrm/dss/dsi.c if (REG_GET(dsi, DSI_COMPLEXIO_CFG2, 17, 17)) { /* LP_BUSY */ REG_GET 5387 drivers/gpu/drm/omapdrm/dss/dsi.c dsi->num_lanes_supported = 1 + REG_GET(dsi, DSI_GNQ, 11, 9); REG_GET 286 drivers/gpu/drm/omapdrm/dss/hdmi.h while (val != (v = REG_GET(base_addr, idx, b2, b1))) { REG_GET 43 drivers/gpu/drm/omapdrm/dss/hdmi4_core.c if (REG_GET(base, HDMI_CORE_DDC_STATUS, 4, 4) == 1) { REG_GET 115 drivers/gpu/drm/omapdrm/dss/hdmi4_core.c if (REG_GET(base, HDMI_CORE_DDC_STATUS, 6, 6) == 1) { REG_GET 120 drivers/gpu/drm/omapdrm/dss/hdmi4_core.c if (REG_GET(base, HDMI_CORE_DDC_STATUS, 5, 5) == 1) { REG_GET 129 drivers/gpu/drm/omapdrm/dss/hdmi4_core.c if (REG_GET(base, HDMI_CORE_DDC_STATUS, 4, 4) == 0) { REG_GET 136 drivers/gpu/drm/omapdrm/dss/hdmi4_core.c while (REG_GET(base, HDMI_CORE_DDC_STATUS, 2, 2) == 1) { REG_GET 144 drivers/gpu/drm/omapdrm/dss/hdmi4_core.c pedid[i] = REG_GET(base, HDMI_CORE_DDC_DATA, 7, 0); REG_GET 284 drivers/gpu/drm/omapdrm/dss/hdmi5.c idlemode = REG_GET(hdmi->wp.base, HDMI_WP_SYSCONFIG, 3, 2); REG_GET 589 drivers/gpu/drm/omapdrm/dss/hdmi5.c REG_GET(hdmi->wp.base, HDMI_WP_SYSCONFIG, 3, 2); REG_GET 159 drivers/gpu/drm/omapdrm/dss/hdmi5_core.c stat = REG_GET(base, HDMI_CORE_IH_I2CM_STAT0, 1, 0); REG_GET 179 drivers/gpu/drm/omapdrm/dss/hdmi5_core.c pedid[cur_addr] = REG_GET(base, HDMI_CORE_I2CM_DATAI, 7, 0); REG_GET 70 drivers/gpu/drm/omapdrm/dss/hdmi_wp.c if (REG_GET(wp->base, HDMI_WP_PWR_CTRL, 5, 4) == val) REG_GET 264 drivers/video/fbdev/omap2/omapfb/dss/dispc.c return REG_GET(rfld.reg, rfld.high, rfld.low); REG_GET 584 drivers/video/fbdev/omap2/omapfb/dss/dispc.c return REG_GET(DISPC_CONTROL2, 6, 6) == 1; REG_GET 592 drivers/video/fbdev/omap2/omapfb/dss/dispc.c enable = REG_GET(DISPC_OVL_ATTRIBUTES(plane), 0, 0) == 1; REG_GET 597 drivers/video/fbdev/omap2/omapfb/dss/dispc.c go = REG_GET(DISPC_CONTROL2, 6, 6) == 1; REG_GET 1157 drivers/video/fbdev/omap2/omapfb/dss/dispc.c size = REG_GET(DISPC_OVL_FIFO_SIZE_STATUS(fifo), start, end); REG_GET 1248 drivers/video/fbdev/omap2/omapfb/dss/dispc.c REG_GET(DISPC_OVL_FIFO_THRESHOLD(plane), REG_GET 1250 drivers/video/fbdev/omap2/omapfb/dss/dispc.c REG_GET(DISPC_OVL_FIFO_THRESHOLD(plane), REG_GET 2888 drivers/video/fbdev/omap2/omapfb/dss/dispc.c return REG_GET(DISPC_OVL_ATTRIBUTES(plane), 0, 0); REG_GET 3779 drivers/video/fbdev/omap2/omapfb/dss/dispc.c cinfo->lck_div = REG_GET(DISPC_DIVISORo(channel), 23, 16); REG_GET 3780 drivers/video/fbdev/omap2/omapfb/dss/dispc.c cinfo->pck_div = REG_GET(DISPC_DIVISORo(channel), 7, 0); REG_GET 4160 drivers/video/fbdev/omap2/omapfb/dss/dispc.c if (REG_GET(DISPC_CONFIG, 2, 1) != OMAP_DSS_LOAD_FRAME_ONLY) { REG_GET 501 drivers/video/fbdev/omap2/omapfb/dss/dsi.c if (REG_GET(dsidev, idx, bitnum, bitnum) == value) REG_GET 508 drivers/video/fbdev/omap2/omapfb/dss/dsi.c if (REG_GET(dsidev, idx, bitnum, bitnum) == value) REG_GET 1775 drivers/video/fbdev/omap2/omapfb/dss/dsi.c val = REG_GET(dsidev, DSI_GNQ, 14, 12); /* VP1_LINE_BUFFER_SIZE */ REG_GET 2271 drivers/video/fbdev/omap2/omapfb/dss/dsi.c return REG_GET(dsidev, DSI_VC_CTRL(channel), 0, 0); REG_GET 2282 drivers/video/fbdev/omap2/omapfb/dss/dsi.c if (REG_GET(vp_data->dsidev, DSI_VC_TE(channel), bit, bit) == 0) REG_GET 2305 drivers/video/fbdev/omap2/omapfb/dss/dsi.c if (REG_GET(dsidev, DSI_VC_TE(channel), bit, bit)) { REG_GET 2332 drivers/video/fbdev/omap2/omapfb/dss/dsi.c if (REG_GET(l4_data->dsidev, DSI_VC_CTRL(channel), 5, 5) == 0) REG_GET 2351 drivers/video/fbdev/omap2/omapfb/dss/dsi.c if (REG_GET(dsidev, DSI_VC_CTRL(channel), 5, 5)) { REG_GET 2506 drivers/video/fbdev/omap2/omapfb/dss/dsi.c while (REG_GET(dsidev, DSI_VC_CTRL(channel), 20, 20)) { REG_GET 2558 drivers/video/fbdev/omap2/omapfb/dss/dsi.c while (REG_GET(dsidev, DSI_VC_CTRL(channel), 20, 20)) { REG_GET 2594 drivers/video/fbdev/omap2/omapfb/dss/dsi.c if (REG_GET(dsidev, DSI_VC_CTRL(channel), 20, 20)) { REG_GET 2846 drivers/video/fbdev/omap2/omapfb/dss/dsi.c if (REG_GET(dsidev, DSI_VC_CTRL(channel), 20, 20)) { REG_GET 2939 drivers/video/fbdev/omap2/omapfb/dss/dsi.c if (REG_GET(dsidev, DSI_VC_CTRL(channel), 20, 20) == 0) { REG_GET 3122 drivers/video/fbdev/omap2/omapfb/dss/dsi.c if (REG_GET(dsidev, DSI_CLK_CTRL, 13, 13)) { REG_GET 3140 drivers/video/fbdev/omap2/omapfb/dss/dsi.c if (REG_GET(dsidev, DSI_COMPLEXIO_CFG2, 16, 16)) { /* HS_BUSY */ REG_GET 3145 drivers/video/fbdev/omap2/omapfb/dss/dsi.c if (REG_GET(dsidev, DSI_COMPLEXIO_CFG2, 17, 17)) { /* LP_BUSY */ REG_GET 5420 drivers/video/fbdev/omap2/omapfb/dss/dsi.c dsi->num_lanes_supported = 1 + REG_GET(dsidev, DSI_GNQ, 11, 9); REG_GET 649 drivers/video/fbdev/omap2/omapfb/dss/dss.c return REG_GET(DSS_CONTROL, 15, 15); REG_GET 268 drivers/video/fbdev/omap2/omapfb/dss/hdmi.h while (val != (v = REG_GET(base_addr, idx, b2, b1))) { REG_GET 44 drivers/video/fbdev/omap2/omapfb/dss/hdmi4_core.c if (REG_GET(base, HDMI_CORE_DDC_STATUS, 4, 4) == 1) { REG_GET 116 drivers/video/fbdev/omap2/omapfb/dss/hdmi4_core.c if (REG_GET(base, HDMI_CORE_DDC_STATUS, 6, 6) == 1) { REG_GET 121 drivers/video/fbdev/omap2/omapfb/dss/hdmi4_core.c if (REG_GET(base, HDMI_CORE_DDC_STATUS, 5, 5) == 1) { REG_GET 130 drivers/video/fbdev/omap2/omapfb/dss/hdmi4_core.c if (REG_GET(base, HDMI_CORE_DDC_STATUS, 4, 4) == 0) { REG_GET 137 drivers/video/fbdev/omap2/omapfb/dss/hdmi4_core.c while (REG_GET(base, HDMI_CORE_DDC_STATUS, 2, 2) == 1) { REG_GET 145 drivers/video/fbdev/omap2/omapfb/dss/hdmi4_core.c pedid[i] = REG_GET(base, HDMI_CORE_DDC_DATA, 7, 0); REG_GET 317 drivers/video/fbdev/omap2/omapfb/dss/hdmi5.c idlemode = REG_GET(hdmi.wp.base, HDMI_WP_SYSCONFIG, 3, 2); REG_GET 701 drivers/video/fbdev/omap2/omapfb/dss/hdmi5.c REG_GET(hdmi.wp.base, HDMI_WP_SYSCONFIG, 3, 2); REG_GET 160 drivers/video/fbdev/omap2/omapfb/dss/hdmi5_core.c stat = REG_GET(base, HDMI_CORE_IH_I2CM_STAT0, 1, 0); REG_GET 180 drivers/video/fbdev/omap2/omapfb/dss/hdmi5_core.c pedid[cur_addr] = REG_GET(base, HDMI_CORE_I2CM_DATAI, 7, 0); REG_GET 71 drivers/video/fbdev/omap2/omapfb/dss/hdmi_wp.c if (REG_GET(wp->base, HDMI_WP_PWR_CTRL, 5, 4) == val)