REG_FLD_MOD 115 drivers/gpu/drm/gma500/mdfld_dsi_dpi.c REG_FLD_MOD(MIPI_DEVICE_READY_REG(pipe), !!state, 0, 0); REG_FLD_MOD 148 drivers/gpu/drm/gma500/mdfld_dsi_dpi.c REG_FLD_MOD(MIPI_DEVICE_READY_REG(pipe), 2, 2, 1); REG_FLD_MOD 152 drivers/gpu/drm/gma500/mdfld_dsi_dpi.c REG_FLD_MOD(MIPI_PORT_CONTROL(pipe), 0, 16, 16); REG_FLD_MOD 156 drivers/gpu/drm/gma500/mdfld_dsi_dpi.c REG_FLD_MOD(dspcntr_reg, 0, 31, 31); REG_FLD_MOD 163 drivers/gpu/drm/gma500/mdfld_dsi_dpi.c REG_FLD_MOD(pipeconf_reg, 0, 31, 31); REG_FLD_MOD 478 drivers/gpu/drm/gma500/mdfld_dsi_dpi.c REG_FLD_MOD(MIPI_DEVICE_READY_REG(pipe), 0, 0, 0); REG_FLD_MOD 567 drivers/gpu/drm/gma500/mdfld_dsi_dpi.c REG_FLD_MOD(MIPI_DEVICE_READY_REG(pipe), 1, 0, 0); REG_FLD_MOD 385 drivers/gpu/drm/omapdrm/dss/dispc.c REG_FLD_MOD(dispc, rfld.reg, val, rfld.high, rfld.low); REG_FLD_MOD 388 drivers/gpu/drm/omapdrm/dss/dispc.c REG_FLD_MOD(dispc, rfld.reg, val, rfld.high, rfld.low); REG_FLD_MOD 758 drivers/gpu/drm/omapdrm/dss/dispc.c REG_FLD_MOD(dispc, DISPC_CONTROL2, 1, 6, 6); REG_FLD_MOD 883 drivers/gpu/drm/omapdrm/dss/dispc.c REG_FLD_MOD(dispc, DISPC_OVL_ATTRIBUTES(plane), ct->full_range, 11, 11); REG_FLD_MOD 901 drivers/gpu/drm/omapdrm/dss/dispc.c REG_FLD_MOD(dispc, DISPC_OVL_ATTRIBUTES(plane), ct->full_range, 11, 11); REG_FLD_MOD 1007 drivers/gpu/drm/omapdrm/dss/dispc.c REG_FLD_MOD(dispc, DISPC_OVL_ATTRIBUTES(plane), zorder, 27, 26); REG_FLD_MOD 1018 drivers/gpu/drm/omapdrm/dss/dispc.c REG_FLD_MOD(dispc, DISPC_OVL_ATTRIBUTES(i), 1, 25, 25); REG_FLD_MOD 1029 drivers/gpu/drm/omapdrm/dss/dispc.c REG_FLD_MOD(dispc, DISPC_OVL_ATTRIBUTES(plane), enable ? 1 : 0, 28, 28); REG_FLD_MOD 1044 drivers/gpu/drm/omapdrm/dss/dispc.c REG_FLD_MOD(dispc, DISPC_GLOBAL_ALPHA, global_alpha, shift + 7, shift); REG_FLD_MOD 1129 drivers/gpu/drm/omapdrm/dss/dispc.c REG_FLD_MOD(dispc, DISPC_OVL_ATTRIBUTES(plane), m, 4, 1); REG_FLD_MOD 1140 drivers/gpu/drm/omapdrm/dss/dispc.c REG_FLD_MOD(dispc, DISPC_OVL_ATTRIBUTES(plane), 1, 29, 29); REG_FLD_MOD 1142 drivers/gpu/drm/omapdrm/dss/dispc.c REG_FLD_MOD(dispc, DISPC_OVL_ATTRIBUTES(plane), 0, 29, 29); REG_FLD_MOD 1257 drivers/gpu/drm/omapdrm/dss/dispc.c REG_FLD_MOD(dispc, DISPC_OVL_ATTRIBUTES(plane), burst_size, REG_FLD_MOD 1356 drivers/gpu/drm/omapdrm/dss/dispc.c REG_FLD_MOD(dispc, DISPC_OVL_ATTRIBUTES(plane), enable, shift, shift); REG_FLD_MOD 1510 drivers/gpu/drm/omapdrm/dss/dispc.c REG_FLD_MOD(dispc, DISPC_CONFIG, enable ? 1 : 0, 14, 14); REG_FLD_MOD 1570 drivers/gpu/drm/omapdrm/dss/dispc.c REG_FLD_MOD(dispc, DISPC_OVL_ATTRIBUTES(plane), enable, bit, bit); REG_FLD_MOD 1900 drivers/gpu/drm/omapdrm/dss/dispc.c REG_FLD_MOD(dispc, DISPC_OVL_ATTRIBUTES2(plane), REG_FLD_MOD 1953 drivers/gpu/drm/omapdrm/dss/dispc.c REG_FLD_MOD(dispc, DISPC_OVL_ATTRIBUTES2(plane), REG_FLD_MOD 1957 drivers/gpu/drm/omapdrm/dss/dispc.c REG_FLD_MOD(dispc, DISPC_OVL_ATTRIBUTES(plane), scale_x ? 1 : 0, 5, 5); REG_FLD_MOD 1959 drivers/gpu/drm/omapdrm/dss/dispc.c REG_FLD_MOD(dispc, DISPC_OVL_ATTRIBUTES(plane), scale_y ? 1 : 0, 6, 6); REG_FLD_MOD 2038 drivers/gpu/drm/omapdrm/dss/dispc.c REG_FLD_MOD(dispc, DISPC_OVL_ATTRIBUTES(plane), vidrot, 13, 12); REG_FLD_MOD 2040 drivers/gpu/drm/omapdrm/dss/dispc.c REG_FLD_MOD(dispc, DISPC_OVL_ATTRIBUTES(plane), REG_FLD_MOD 2050 drivers/gpu/drm/omapdrm/dss/dispc.c REG_FLD_MOD(dispc, DISPC_OVL_ATTRIBUTES(plane), REG_FLD_MOD 2850 drivers/gpu/drm/omapdrm/dss/dispc.c REG_FLD_MOD(dispc, DISPC_OVL_ATTRIBUTES2(plane), 0, 7, 0); REG_FLD_MOD 2866 drivers/gpu/drm/omapdrm/dss/dispc.c REG_FLD_MOD(dispc, DISPC_OVL_ATTRIBUTES2(plane), wbdelay, 7, 0); REG_FLD_MOD 2882 drivers/gpu/drm/omapdrm/dss/dispc.c REG_FLD_MOD(dispc, DISPC_OVL_ATTRIBUTES(plane), enable ? 1 : 0, 0, 0); REG_FLD_MOD 2893 drivers/gpu/drm/omapdrm/dss/dispc.c REG_FLD_MOD(dispc, DISPC_CONTROL, act_high ? 1 : 0, 29, 29); REG_FLD_MOD 2901 drivers/gpu/drm/omapdrm/dss/dispc.c REG_FLD_MOD(dispc, DISPC_CONTROL, enable ? 1 : 0, 28, 28); REG_FLD_MOD 2909 drivers/gpu/drm/omapdrm/dss/dispc.c REG_FLD_MOD(dispc, DISPC_CONTROL, enable ? 1 : 0, 27, 27); REG_FLD_MOD 2929 drivers/gpu/drm/omapdrm/dss/dispc.c REG_FLD_MOD(dispc, DISPC_CONFIG, mode, 2, 1); REG_FLD_MOD 2963 drivers/gpu/drm/omapdrm/dss/dispc.c REG_FLD_MOD(dispc, DISPC_CONFIG, enable, 18, 18); REG_FLD_MOD 2965 drivers/gpu/drm/omapdrm/dss/dispc.c REG_FLD_MOD(dispc, DISPC_CONFIG, enable, 19, 19); REG_FLD_MOD 3251 drivers/gpu/drm/omapdrm/dss/dispc.c REG_FLD_MOD(dispc, DISPC_CONTROL, REG_FLD_MOD 3780 drivers/gpu/drm/omapdrm/dss/dispc.c REG_FLD_MOD(dispc, DISPC_SYSCONFIG, 2, 4, 3); REG_FLD_MOD 3785 drivers/gpu/drm/omapdrm/dss/dispc.c REG_FLD_MOD(dispc, DISPC_SYSCONFIG, 1, 4, 3); /* SIDLEMODE: no idle */ REG_FLD_MOD 3939 drivers/gpu/drm/omapdrm/dss/dispc.c REG_FLD_MOD(dispc, DISPC_CONFIG, 1, 3, 3); REG_FLD_MOD 3947 drivers/gpu/drm/omapdrm/dss/dispc.c REG_FLD_MOD(dispc, DISPC_CONFIG, 1, 9, 9); REG_FLD_MOD 3960 drivers/gpu/drm/omapdrm/dss/dispc.c REG_FLD_MOD(dispc, DISPC_MSTANDBY_CTRL, 1, 0, 0); REG_FLD_MOD 4651 drivers/gpu/drm/omapdrm/dss/dispc.c REG_FLD_MOD(dispc, DISPC_CONFIG, 0x1f, 8, 4); REG_FLD_MOD 4689 drivers/gpu/drm/omapdrm/dss/dispc.c REG_FLD_MOD(dispc, DISPC_CONFIG, gatestate, 8, 4); REG_FLD_MOD 1170 drivers/gpu/drm/omapdrm/dss/dsi.c REG_FLD_MOD(dsi, DSI_CTRL, enable, 0, 0); /* IF_EN */ REG_FLD_MOD 1253 drivers/gpu/drm/omapdrm/dss/dsi.c REG_FLD_MOD(dsi, DSI_CLK_CTRL, lp_clk_div, 12, 0); REG_FLD_MOD 1256 drivers/gpu/drm/omapdrm/dss/dsi.c REG_FLD_MOD(dsi, DSI_CLK_CTRL, dsi_fclk > 30000000 ? 1 : 0, 21, 21); REG_FLD_MOD 1264 drivers/gpu/drm/omapdrm/dss/dsi.c REG_FLD_MOD(dsi, DSI_CLK_CTRL, 1, 14, 14); /* CIO_CLK_ICG */ REG_FLD_MOD 1271 drivers/gpu/drm/omapdrm/dss/dsi.c REG_FLD_MOD(dsi, DSI_CLK_CTRL, 0, 14, 14); /* CIO_CLK_ICG */ REG_FLD_MOD 1291 drivers/gpu/drm/omapdrm/dss/dsi.c REG_FLD_MOD(dsi, DSI_CLK_CTRL, state, 31, 30); REG_FLD_MOD 1631 drivers/gpu/drm/omapdrm/dss/dsi.c REG_FLD_MOD(dsi, DSI_COMPLEXIO_CFG1, state, 28, 27); REG_FLD_MOD 1853 drivers/gpu/drm/omapdrm/dss/dsi.c REG_FLD_MOD(dsi, DSI_DSIPHY_CFG10, l, lptxscp_start, 17); REG_FLD_MOD 1858 drivers/gpu/drm/omapdrm/dss/dsi.c REG_FLD_MOD(dsi, DSI_DSIPHY_CFG10, 1, 27, 27); REG_FLD_MOD 1864 drivers/gpu/drm/omapdrm/dss/dsi.c REG_FLD_MOD(dsi, DSI_DSIPHY_CFG10, 0, 27, 27); /* ENLPTXSCPDAT */ REG_FLD_MOD 1867 drivers/gpu/drm/omapdrm/dss/dsi.c REG_FLD_MOD(dsi, DSI_DSIPHY_CFG10, 0, 22, 17); REG_FLD_MOD 2082 drivers/gpu/drm/omapdrm/dss/dsi.c REG_FLD_MOD(dsi, DSI_CLK_CTRL, 1, 20, 20); /* LP_CLK_ENABLE */ REG_FLD_MOD 2100 drivers/gpu/drm/omapdrm/dss/dsi.c REG_FLD_MOD(dsi, DSI_TIMING1, 0, 15, 15); REG_FLD_MOD 2106 drivers/gpu/drm/omapdrm/dss/dsi.c REG_FLD_MOD(dsi, DSI_CLK_CTRL, REG_FLD_MOD 2117 drivers/gpu/drm/omapdrm/dss/dsi.c REG_FLD_MOD(dsi, DSI_CLK_CTRL, 0, 20, 20); /* LP_CLK_ENABLE */ REG_FLD_MOD 2132 drivers/gpu/drm/omapdrm/dss/dsi.c REG_FLD_MOD(dsi, DSI_CLK_CTRL, 0, 13, 13); REG_FLD_MOD 2347 drivers/gpu/drm/omapdrm/dss/dsi.c REG_FLD_MOD(dsi, DSI_VC_CTRL(channel), enable, 0, 0); REG_FLD_MOD 2406 drivers/gpu/drm/omapdrm/dss/dsi.c REG_FLD_MOD(dsi, DSI_VC_CTRL(channel), source, 1, 1); REG_FLD_MOD 2411 drivers/gpu/drm/omapdrm/dss/dsi.c REG_FLD_MOD(dsi, DSI_VC_CTRL(channel), enable, 30, 30); REG_FLD_MOD 2433 drivers/gpu/drm/omapdrm/dss/dsi.c REG_FLD_MOD(dsi, DSI_VC_CTRL(channel), enable, 9, 9); REG_FLD_MOD 2537 drivers/gpu/drm/omapdrm/dss/dsi.c REG_FLD_MOD(dsi, DSI_VC_CTRL(channel), 1, 6, 6); /* BTA_EN */ REG_FLD_MOD 3054 drivers/gpu/drm/omapdrm/dss/dsi.c REG_FLD_MOD(dsi, DSI_CLK_CTRL, 0, 13, 13); REG_FLD_MOD 3094 drivers/gpu/drm/omapdrm/dss/dsi.c REG_FLD_MOD(dsi, DSI_COMPLEXIO_CFG2, mask, 9, 5); REG_FLD_MOD 3110 drivers/gpu/drm/omapdrm/dss/dsi.c REG_FLD_MOD(dsi, DSI_COMPLEXIO_CFG2, 0, 9, 5); REG_FLD_MOD 3258 drivers/gpu/drm/omapdrm/dss/dsi.c REG_FLD_MOD(dsi, DSI_CTRL, num_line_buffers, 13, 12); REG_FLD_MOD 3762 drivers/gpu/drm/omapdrm/dss/dsi.c REG_FLD_MOD(dsi, DSI_VC_CTRL(channel), 1, 4, 4); REG_FLD_MOD 3798 drivers/gpu/drm/omapdrm/dss/dsi.c REG_FLD_MOD(dsi, DSI_VC_CTRL(channel), 0, 4, 4); REG_FLD_MOD 3877 drivers/gpu/drm/omapdrm/dss/dsi.c REG_FLD_MOD(dsi, DSI_TIMING2, 0, 15, 15); /* LP_RX_TO */ REG_FLD_MOD 3901 drivers/gpu/drm/omapdrm/dss/dsi.c REG_FLD_MOD(dsi, DSI_TIMING2, 1, 15, 15); /* LP_RX_TO */ REG_FLD_MOD 269 drivers/gpu/drm/omapdrm/dss/dss.c REG_FLD_MOD(dss, DSS_PLL_CONTROL, 1, 18, 18); /* SDI_PLL_SYSRESET */ REG_FLD_MOD 273 drivers/gpu/drm/omapdrm/dss/dss.c REG_FLD_MOD(dss, DSS_PLL_CONTROL, 1, 28, 28); /* SDI_PLL_GOBIT */ REG_FLD_MOD 285 drivers/gpu/drm/omapdrm/dss/dss.c REG_FLD_MOD(dss, DSS_PLL_CONTROL, 0, 28, 28); REG_FLD_MOD 313 drivers/gpu/drm/omapdrm/dss/dss.c REG_FLD_MOD(dss, DSS_PLL_CONTROL, 0, 18, 18); /* SDI_PLL_SYSRESET */ REG_FLD_MOD 327 drivers/gpu/drm/omapdrm/dss/dss.c REG_FLD_MOD(dss, DSS_PLL_CONTROL, 0, 18, 18); /* SDI_PLL_SYSRESET */ REG_FLD_MOD 431 drivers/gpu/drm/omapdrm/dss/dss.c REG_FLD_MOD(dss, DSS_CONTROL, b, /* DISPC_CLK_SWITCH */ REG_FLD_MOD 461 drivers/gpu/drm/omapdrm/dss/dss.c REG_FLD_MOD(dss, DSS_CONTROL, b, pos, pos); /* DSIx_CLK_SWITCH */ REG_FLD_MOD 481 drivers/gpu/drm/omapdrm/dss/dss.c REG_FLD_MOD(dss, DSS_CONTROL, 0, ctrl_bit, ctrl_bit); REG_FLD_MOD 489 drivers/gpu/drm/omapdrm/dss/dss.c REG_FLD_MOD(dss, DSS_CONTROL, 1, ctrl_bit, ctrl_bit); REG_FLD_MOD 513 drivers/gpu/drm/omapdrm/dss/dss.c REG_FLD_MOD(dss, DSS_CONTROL, 0, ctrl_bit, ctrl_bit); REG_FLD_MOD 520 drivers/gpu/drm/omapdrm/dss/dss.c REG_FLD_MOD(dss, DSS_CONTROL, 1, ctrl_bit, ctrl_bit); REG_FLD_MOD 542 drivers/gpu/drm/omapdrm/dss/dss.c REG_FLD_MOD(dss, DSS_CONTROL, 0, ctrl_bit, ctrl_bit); REG_FLD_MOD 549 drivers/gpu/drm/omapdrm/dss/dss.c REG_FLD_MOD(dss, DSS_CONTROL, 1, ctrl_bit, ctrl_bit); REG_FLD_MOD 709 drivers/gpu/drm/omapdrm/dss/dss.c REG_FLD_MOD(dss, DSS_CONTROL, l, 6, 6); REG_FLD_MOD 715 drivers/gpu/drm/omapdrm/dss/dss.c REG_FLD_MOD(dss, DSS_CONTROL, enable, 5, 5); REG_FLD_MOD 733 drivers/gpu/drm/omapdrm/dss/dss.c REG_FLD_MOD(dss, DSS_CONTROL, src, 15, 15); REG_FLD_MOD 761 drivers/gpu/drm/omapdrm/dss/dss.c REG_FLD_MOD(dss, DSS_CONTROL, val, 17, 17); REG_FLD_MOD 788 drivers/gpu/drm/omapdrm/dss/dss.c REG_FLD_MOD(dss, DSS_CONTROL, val, 17, 16); REG_FLD_MOD 1372 drivers/gpu/drm/omapdrm/dss/dss.c REG_FLD_MOD(dss, DSS_CONTROL, 0, 0, 0); REG_FLD_MOD 1377 drivers/gpu/drm/omapdrm/dss/dss.c REG_FLD_MOD(dss, DSS_CONTROL, 1, 4, 4); /* venc dac demen */ REG_FLD_MOD 1378 drivers/gpu/drm/omapdrm/dss/dss.c REG_FLD_MOD(dss, DSS_CONTROL, 1, 3, 3); /* venc clock 4x enable */ REG_FLD_MOD 1379 drivers/gpu/drm/omapdrm/dss/dss.c REG_FLD_MOD(dss, DSS_CONTROL, 0, 2, 2); /* venc clock mode = normal */ REG_FLD_MOD 120 drivers/gpu/drm/omapdrm/dss/hdmi4_cec.c REG_FLD_MOD(core->base, HDMI_CEC_DBG_3, 0x1, 7, 7); REG_FLD_MOD 128 drivers/gpu/drm/omapdrm/dss/hdmi4_cec.c REG_FLD_MOD(core->base, HDMI_CEC_DBG_3, 0x1, 7, 7); REG_FLD_MOD 140 drivers/gpu/drm/omapdrm/dss/hdmi4_cec.c REG_FLD_MOD(core->base, HDMI_CEC_DBG_3, 0x1, 7, 7); REG_FLD_MOD 175 drivers/gpu/drm/omapdrm/dss/hdmi4_cec.c REG_FLD_MOD(core->base, HDMI_CORE_SYS_INTR_UNMASK4, 0, 3, 3); REG_FLD_MOD 178 drivers/gpu/drm/omapdrm/dss/hdmi4_cec.c REG_FLD_MOD(core->wp->base, HDMI_WP_CLK, 0, 5, 0); REG_FLD_MOD 190 drivers/gpu/drm/omapdrm/dss/hdmi4_cec.c REG_FLD_MOD(core->wp->base, HDMI_WP_CLK, 0x18, 5, 0); REG_FLD_MOD 215 drivers/gpu/drm/omapdrm/dss/hdmi4_cec.c REG_FLD_MOD(core->base, HDMI_CORE_SYS_INTR_UNMASK4, 0x1, 3, 3); REG_FLD_MOD 250 drivers/gpu/drm/omapdrm/dss/hdmi4_cec.c REG_FLD_MOD(core->wp->base, HDMI_WP_CLK, 0, 5, 0); REG_FLD_MOD 300 drivers/gpu/drm/omapdrm/dss/hdmi4_cec.c REG_FLD_MOD(core->base, HDMI_CEC_DBG_3, attempts - 1, 6, 4); REG_FLD_MOD 352 drivers/gpu/drm/omapdrm/dss/hdmi4_cec.c REG_FLD_MOD(core->wp->base, HDMI_WP_CLK, 0, 5, 0); REG_FLD_MOD 40 drivers/gpu/drm/omapdrm/dss/hdmi4_core.c REG_FLD_MOD(base, HDMI_CORE_AV_DPD, 0x7, 2, 0); REG_FLD_MOD 45 drivers/gpu/drm/omapdrm/dss/hdmi4_core.c REG_FLD_MOD(base, HDMI_CORE_DDC_CMD, 0xf, 3, 0); REG_FLD_MOD 55 drivers/gpu/drm/omapdrm/dss/hdmi4_core.c REG_FLD_MOD(base, HDMI_CORE_DDC_CMD, 0xA, 3, 0); REG_FLD_MOD 65 drivers/gpu/drm/omapdrm/dss/hdmi4_core.c REG_FLD_MOD(base, HDMI_CORE_DDC_CMD, 0x9, 3, 0); REG_FLD_MOD 96 drivers/gpu/drm/omapdrm/dss/hdmi4_core.c REG_FLD_MOD(base, HDMI_CORE_DDC_SEGM, ext / 2, 7, 0); REG_FLD_MOD 99 drivers/gpu/drm/omapdrm/dss/hdmi4_core.c REG_FLD_MOD(base, HDMI_CORE_DDC_ADDR, 0xA0 >> 1, 7, 1); REG_FLD_MOD 102 drivers/gpu/drm/omapdrm/dss/hdmi4_core.c REG_FLD_MOD(base, HDMI_CORE_DDC_OFFSET, offset, 7, 0); REG_FLD_MOD 105 drivers/gpu/drm/omapdrm/dss/hdmi4_core.c REG_FLD_MOD(base, HDMI_CORE_DDC_COUNT1, 0x80, 7, 0); REG_FLD_MOD 106 drivers/gpu/drm/omapdrm/dss/hdmi4_core.c REG_FLD_MOD(base, HDMI_CORE_DDC_COUNT2, 0x0, 1, 0); REG_FLD_MOD 110 drivers/gpu/drm/omapdrm/dss/hdmi4_core.c REG_FLD_MOD(base, HDMI_CORE_DDC_CMD, 0x4, 3, 0); REG_FLD_MOD 112 drivers/gpu/drm/omapdrm/dss/hdmi4_core.c REG_FLD_MOD(base, HDMI_CORE_DDC_CMD, 0x2, 3, 0); REG_FLD_MOD 202 drivers/gpu/drm/omapdrm/dss/hdmi4_core.c REG_FLD_MOD(core->base, HDMI_CORE_SYS_SYS_CTRL1, 0x1, 0, 0); REG_FLD_MOD 208 drivers/gpu/drm/omapdrm/dss/hdmi4_core.c REG_FLD_MOD(core->base, HDMI_CORE_SYS_SRST, 0x0, 0, 0); REG_FLD_MOD 214 drivers/gpu/drm/omapdrm/dss/hdmi4_core.c REG_FLD_MOD(core->base, HDMI_CORE_SYS_SRST, 0x1, 0, 0); REG_FLD_MOD 233 drivers/gpu/drm/omapdrm/dss/hdmi4_core.c REG_FLD_MOD(core_sys_base, REG_FLD_MOD 257 drivers/gpu/drm/omapdrm/dss/hdmi4_core.c REG_FLD_MOD(core_sys_base, REG_FLD_MOD 525 drivers/gpu/drm/omapdrm/dss/hdmi4_core.c REG_FLD_MOD(av_base, HDMI_CORE_AV_N_SVAL1, cfg->n, 7, 0); REG_FLD_MOD 526 drivers/gpu/drm/omapdrm/dss/hdmi4_core.c REG_FLD_MOD(av_base, HDMI_CORE_AV_N_SVAL2, cfg->n >> 8, 7, 0); REG_FLD_MOD 527 drivers/gpu/drm/omapdrm/dss/hdmi4_core.c REG_FLD_MOD(av_base, HDMI_CORE_AV_N_SVAL3, cfg->n >> 16, 7, 0); REG_FLD_MOD 530 drivers/gpu/drm/omapdrm/dss/hdmi4_core.c REG_FLD_MOD(av_base, HDMI_CORE_AV_CTS_SVAL1, cfg->cts, 7, 0); REG_FLD_MOD 531 drivers/gpu/drm/omapdrm/dss/hdmi4_core.c REG_FLD_MOD(av_base, REG_FLD_MOD 533 drivers/gpu/drm/omapdrm/dss/hdmi4_core.c REG_FLD_MOD(av_base, REG_FLD_MOD 536 drivers/gpu/drm/omapdrm/dss/hdmi4_core.c REG_FLD_MOD(av_base, HDMI_CORE_AV_AUD_PAR_BUSCLK_1, REG_FLD_MOD 538 drivers/gpu/drm/omapdrm/dss/hdmi4_core.c REG_FLD_MOD(av_base, HDMI_CORE_AV_AUD_PAR_BUSCLK_2, REG_FLD_MOD 540 drivers/gpu/drm/omapdrm/dss/hdmi4_core.c REG_FLD_MOD(av_base, HDMI_CORE_AV_AUD_PAR_BUSCLK_3, REG_FLD_MOD 545 drivers/gpu/drm/omapdrm/dss/hdmi4_core.c REG_FLD_MOD(av_base, REG_FLD_MOD 561 drivers/gpu/drm/omapdrm/dss/hdmi4_core.c REG_FLD_MOD(av_base, HDMI_CORE_AV_ACR_CTRL, 1, 2, 2); REG_FLD_MOD 564 drivers/gpu/drm/omapdrm/dss/hdmi4_core.c REG_FLD_MOD(av_base, HDMI_CORE_AV_SPDIF_CTRL, REG_FLD_MOD 594 drivers/gpu/drm/omapdrm/dss/hdmi4_core.c REG_FLD_MOD(av_base, HDMI_CORE_AV_I2S_IN_LEN, REG_FLD_MOD 598 drivers/gpu/drm/omapdrm/dss/hdmi4_core.c REG_FLD_MOD(av_base, HDMI_CORE_AV_HDMI_CTRL, cfg->layout, 2, 1); REG_FLD_MOD 612 drivers/gpu/drm/omapdrm/dss/hdmi4_core.c REG_FLD_MOD(av_base, HDMI_CORE_AV_SWAP_I2S, 1, 5, 5); REG_FLD_MOD 856 drivers/gpu/drm/omapdrm/dss/hdmi4_core.c REG_FLD_MOD(hdmi_av_base(core), REG_FLD_MOD 866 drivers/gpu/drm/omapdrm/dss/hdmi4_core.c REG_FLD_MOD(hdmi_av_base(core), REG_FLD_MOD 98 drivers/gpu/drm/omapdrm/dss/hdmi5.c REG_FLD_MOD(hdmi->phy.base, HDMI_TXPHY_PAD_CFG_CTRL, 0, 15, 15); REG_FLD_MOD 286 drivers/gpu/drm/omapdrm/dss/hdmi5.c REG_FLD_MOD(hdmi->wp.base, HDMI_WP_SYSCONFIG, 1, 3, 2); REG_FLD_MOD 290 drivers/gpu/drm/omapdrm/dss/hdmi5.c REG_FLD_MOD(hdmi->wp.base, HDMI_WP_SYSCONFIG, idlemode, 3, 2); REG_FLD_MOD 300 drivers/gpu/drm/omapdrm/dss/hdmi5.c REG_FLD_MOD(hd->wp.base, HDMI_WP_SYSCONFIG, 1, 3, 2); REG_FLD_MOD 309 drivers/gpu/drm/omapdrm/dss/hdmi5.c REG_FLD_MOD(hd->wp.base, HDMI_WP_SYSCONFIG, hd->wp_idlemode, 3, 2); REG_FLD_MOD 55 drivers/gpu/drm/omapdrm/dss/hdmi5_core.c REG_FLD_MOD(base, HDMI_CORE_I2CM_SOFTRSTZ, 0, 0, 0); REG_FLD_MOD 61 drivers/gpu/drm/omapdrm/dss/hdmi5_core.c REG_FLD_MOD(base, HDMI_CORE_I2CM_DIV, 0, 3, 3); REG_FLD_MOD 65 drivers/gpu/drm/omapdrm/dss/hdmi5_core.c REG_FLD_MOD(base, HDMI_CORE_I2CM_SS_SCL_HCNT_1_ADDR, REG_FLD_MOD 67 drivers/gpu/drm/omapdrm/dss/hdmi5_core.c REG_FLD_MOD(base, HDMI_CORE_I2CM_SS_SCL_HCNT_0_ADDR, REG_FLD_MOD 72 drivers/gpu/drm/omapdrm/dss/hdmi5_core.c REG_FLD_MOD(base, HDMI_CORE_I2CM_SS_SCL_LCNT_1_ADDR, REG_FLD_MOD 74 drivers/gpu/drm/omapdrm/dss/hdmi5_core.c REG_FLD_MOD(base, HDMI_CORE_I2CM_SS_SCL_LCNT_0_ADDR, REG_FLD_MOD 79 drivers/gpu/drm/omapdrm/dss/hdmi5_core.c REG_FLD_MOD(base, HDMI_CORE_I2CM_FS_SCL_HCNT_1_ADDR, REG_FLD_MOD 81 drivers/gpu/drm/omapdrm/dss/hdmi5_core.c REG_FLD_MOD(base, HDMI_CORE_I2CM_FS_SCL_HCNT_0_ADDR, REG_FLD_MOD 86 drivers/gpu/drm/omapdrm/dss/hdmi5_core.c REG_FLD_MOD(base, HDMI_CORE_I2CM_FS_SCL_LCNT_1_ADDR, REG_FLD_MOD 88 drivers/gpu/drm/omapdrm/dss/hdmi5_core.c REG_FLD_MOD(base, HDMI_CORE_I2CM_FS_SCL_LCNT_0_ADDR, REG_FLD_MOD 93 drivers/gpu/drm/omapdrm/dss/hdmi5_core.c REG_FLD_MOD(base, HDMI_CORE_I2CM_SDA_HOLD_ADDR, v & 0xff, 7, 0); REG_FLD_MOD 95 drivers/gpu/drm/omapdrm/dss/hdmi5_core.c REG_FLD_MOD(base, HDMI_CORE_I2CM_SLAVE, 0x50, 6, 0); REG_FLD_MOD 96 drivers/gpu/drm/omapdrm/dss/hdmi5_core.c REG_FLD_MOD(base, HDMI_CORE_I2CM_SEGADDR, 0x30, 6, 0); REG_FLD_MOD 99 drivers/gpu/drm/omapdrm/dss/hdmi5_core.c REG_FLD_MOD(base, HDMI_CORE_I2CM_CTLINT, 0x1, 7, 7); REG_FLD_MOD 102 drivers/gpu/drm/omapdrm/dss/hdmi5_core.c REG_FLD_MOD(base, HDMI_CORE_I2CM_CTLINT, 0x0, 6, 6); REG_FLD_MOD 105 drivers/gpu/drm/omapdrm/dss/hdmi5_core.c REG_FLD_MOD(base, HDMI_CORE_I2CM_CTLINT, 0x1, 3, 3); REG_FLD_MOD 108 drivers/gpu/drm/omapdrm/dss/hdmi5_core.c REG_FLD_MOD(base, HDMI_CORE_I2CM_CTLINT, 0x0, 2, 2); REG_FLD_MOD 111 drivers/gpu/drm/omapdrm/dss/hdmi5_core.c REG_FLD_MOD(base, HDMI_CORE_I2CM_INT, 0x1, 3, 3); REG_FLD_MOD 114 drivers/gpu/drm/omapdrm/dss/hdmi5_core.c REG_FLD_MOD(base, HDMI_CORE_I2CM_INT, 0x0, 2, 2); REG_FLD_MOD 122 drivers/gpu/drm/omapdrm/dss/hdmi5_core.c REG_FLD_MOD(base, HDMI_CORE_I2CM_CTLINT, 0x1, 6, 6); REG_FLD_MOD 123 drivers/gpu/drm/omapdrm/dss/hdmi5_core.c REG_FLD_MOD(base, HDMI_CORE_I2CM_CTLINT, 0x1, 2, 2); REG_FLD_MOD 124 drivers/gpu/drm/omapdrm/dss/hdmi5_core.c REG_FLD_MOD(base, HDMI_CORE_I2CM_INT, 0x1, 2, 2); REG_FLD_MOD 136 drivers/gpu/drm/omapdrm/dss/hdmi5_core.c REG_FLD_MOD(base, HDMI_CORE_I2CM_SEGPTR, seg_ptr, 7, 0); REG_FLD_MOD 146 drivers/gpu/drm/omapdrm/dss/hdmi5_core.c REG_FLD_MOD(base, HDMI_CORE_IH_I2CM_STAT0, 0x3, 1, 0); REG_FLD_MOD 148 drivers/gpu/drm/omapdrm/dss/hdmi5_core.c REG_FLD_MOD(base, HDMI_CORE_I2CM_ADDRESS, REG_FLD_MOD 152 drivers/gpu/drm/omapdrm/dss/hdmi5_core.c REG_FLD_MOD(base, HDMI_CORE_I2CM_OPERATION, 1, 1, 1); REG_FLD_MOD 154 drivers/gpu/drm/omapdrm/dss/hdmi5_core.c REG_FLD_MOD(base, HDMI_CORE_I2CM_OPERATION, 1, 0, 0); REG_FLD_MOD 337 drivers/gpu/drm/omapdrm/dss/hdmi5_core.c REG_FLD_MOD(base, HDMI_CORE_FC_INHACTIV1, vm->hactive >> 8, 4, 0); REG_FLD_MOD 338 drivers/gpu/drm/omapdrm/dss/hdmi5_core.c REG_FLD_MOD(base, HDMI_CORE_FC_INHACTIV0, vm->hactive & 0xFF, 7, 0); REG_FLD_MOD 341 drivers/gpu/drm/omapdrm/dss/hdmi5_core.c REG_FLD_MOD(base, HDMI_CORE_FC_INVACTIV1, vm->vactive >> 8, 4, 0); REG_FLD_MOD 342 drivers/gpu/drm/omapdrm/dss/hdmi5_core.c REG_FLD_MOD(base, HDMI_CORE_FC_INVACTIV0, vm->vactive & 0xFF, 7, 0); REG_FLD_MOD 345 drivers/gpu/drm/omapdrm/dss/hdmi5_core.c REG_FLD_MOD(base, HDMI_CORE_FC_INHBLANK1, cfg->hblank >> 8, 4, 0); REG_FLD_MOD 346 drivers/gpu/drm/omapdrm/dss/hdmi5_core.c REG_FLD_MOD(base, HDMI_CORE_FC_INHBLANK0, cfg->hblank & 0xFF, 7, 0); REG_FLD_MOD 349 drivers/gpu/drm/omapdrm/dss/hdmi5_core.c REG_FLD_MOD(base, HDMI_CORE_FC_INVBLANK, cfg->vblank, 7, 0); REG_FLD_MOD 352 drivers/gpu/drm/omapdrm/dss/hdmi5_core.c REG_FLD_MOD(base, HDMI_CORE_FC_HSYNCINDELAY1, vm->hfront_porch >> 8, REG_FLD_MOD 354 drivers/gpu/drm/omapdrm/dss/hdmi5_core.c REG_FLD_MOD(base, HDMI_CORE_FC_HSYNCINDELAY0, vm->hfront_porch & 0xFF, REG_FLD_MOD 358 drivers/gpu/drm/omapdrm/dss/hdmi5_core.c REG_FLD_MOD(base, HDMI_CORE_FC_VSYNCINDELAY, vm->vfront_porch, 7, 0); REG_FLD_MOD 361 drivers/gpu/drm/omapdrm/dss/hdmi5_core.c REG_FLD_MOD(base, HDMI_CORE_FC_HSYNCINWIDTH1, (vm->hsync_len >> 8), REG_FLD_MOD 363 drivers/gpu/drm/omapdrm/dss/hdmi5_core.c REG_FLD_MOD(base, HDMI_CORE_FC_HSYNCINWIDTH0, vm->hsync_len & 0xFF, REG_FLD_MOD 367 drivers/gpu/drm/omapdrm/dss/hdmi5_core.c REG_FLD_MOD(base, HDMI_CORE_FC_VSYNCINWIDTH, vm->vsync_len, 5, 0); REG_FLD_MOD 370 drivers/gpu/drm/omapdrm/dss/hdmi5_core.c REG_FLD_MOD(base, HDMI_CORE_FC_INVIDCONF, REG_FLD_MOD 374 drivers/gpu/drm/omapdrm/dss/hdmi5_core.c REG_FLD_MOD(base, HDMI_CORE_FC_PRCONF, 2, 7, 4); REG_FLD_MOD 376 drivers/gpu/drm/omapdrm/dss/hdmi5_core.c REG_FLD_MOD(base, HDMI_CORE_FC_PRCONF, 1, 7, 4); REG_FLD_MOD 385 drivers/gpu/drm/omapdrm/dss/hdmi5_core.c REG_FLD_MOD(base, HDMI_CORE_VP_PR_CD, clr_depth, 7, 4); REG_FLD_MOD 387 drivers/gpu/drm/omapdrm/dss/hdmi5_core.c REG_FLD_MOD(base, HDMI_CORE_VP_CONF, clr_depth ? 0 : 1, 6, 6); REG_FLD_MOD 389 drivers/gpu/drm/omapdrm/dss/hdmi5_core.c REG_FLD_MOD(base, HDMI_CORE_VP_CONF, clr_depth ? 1 : 0, 5, 5); REG_FLD_MOD 391 drivers/gpu/drm/omapdrm/dss/hdmi5_core.c REG_FLD_MOD(base, HDMI_CORE_VP_CONF, 0, 3, 3); REG_FLD_MOD 393 drivers/gpu/drm/omapdrm/dss/hdmi5_core.c REG_FLD_MOD(base, HDMI_CORE_VP_STUFF, clr_depth ? 1 : 0, 1, 1); REG_FLD_MOD 395 drivers/gpu/drm/omapdrm/dss/hdmi5_core.c REG_FLD_MOD(base, HDMI_CORE_VP_STUFF, 1, 2, 2); REG_FLD_MOD 397 drivers/gpu/drm/omapdrm/dss/hdmi5_core.c REG_FLD_MOD(base, HDMI_CORE_VP_CONF, clr_depth ? 0 : 2, 1, 0); REG_FLD_MOD 405 drivers/gpu/drm/omapdrm/dss/hdmi5_core.c REG_FLD_MOD(core->base, HDMI_CORE_CSC_SCALE, clr_depth, 7, 4); REG_FLD_MOD 413 drivers/gpu/drm/omapdrm/dss/hdmi5_core.c REG_FLD_MOD(core->base, HDMI_CORE_TX_INVID0, video_mapping, 4, 0); REG_FLD_MOD 469 drivers/gpu/drm/omapdrm/dss/hdmi5_core.c REG_FLD_MOD(base, HDMI_CORE_FC_PRCONF, pr, 3, 0); REG_FLD_MOD 477 drivers/gpu/drm/omapdrm/dss/hdmi5_core.c REG_FLD_MOD(base, HDMI_CORE_CSC_COEF_A1_MSB, csc_coeff.a1 >> 8 , 6, 0); REG_FLD_MOD 478 drivers/gpu/drm/omapdrm/dss/hdmi5_core.c REG_FLD_MOD(base, HDMI_CORE_CSC_COEF_A1_LSB, csc_coeff.a1, 7, 0); REG_FLD_MOD 479 drivers/gpu/drm/omapdrm/dss/hdmi5_core.c REG_FLD_MOD(base, HDMI_CORE_CSC_COEF_A2_MSB, csc_coeff.a2 >> 8, 6, 0); REG_FLD_MOD 480 drivers/gpu/drm/omapdrm/dss/hdmi5_core.c REG_FLD_MOD(base, HDMI_CORE_CSC_COEF_A2_LSB, csc_coeff.a2, 7, 0); REG_FLD_MOD 481 drivers/gpu/drm/omapdrm/dss/hdmi5_core.c REG_FLD_MOD(base, HDMI_CORE_CSC_COEF_A3_MSB, csc_coeff.a3 >> 8, 6, 0); REG_FLD_MOD 482 drivers/gpu/drm/omapdrm/dss/hdmi5_core.c REG_FLD_MOD(base, HDMI_CORE_CSC_COEF_A3_LSB, csc_coeff.a3, 7, 0); REG_FLD_MOD 483 drivers/gpu/drm/omapdrm/dss/hdmi5_core.c REG_FLD_MOD(base, HDMI_CORE_CSC_COEF_A4_MSB, csc_coeff.a4 >> 8, 6, 0); REG_FLD_MOD 484 drivers/gpu/drm/omapdrm/dss/hdmi5_core.c REG_FLD_MOD(base, HDMI_CORE_CSC_COEF_A4_LSB, csc_coeff.a4, 7, 0); REG_FLD_MOD 485 drivers/gpu/drm/omapdrm/dss/hdmi5_core.c REG_FLD_MOD(base, HDMI_CORE_CSC_COEF_B1_MSB, csc_coeff.b1 >> 8, 6, 0); REG_FLD_MOD 486 drivers/gpu/drm/omapdrm/dss/hdmi5_core.c REG_FLD_MOD(base, HDMI_CORE_CSC_COEF_B1_LSB, csc_coeff.b1, 7, 0); REG_FLD_MOD 487 drivers/gpu/drm/omapdrm/dss/hdmi5_core.c REG_FLD_MOD(base, HDMI_CORE_CSC_COEF_B2_MSB, csc_coeff.b2 >> 8, 6, 0); REG_FLD_MOD 488 drivers/gpu/drm/omapdrm/dss/hdmi5_core.c REG_FLD_MOD(base, HDMI_CORE_CSC_COEF_B2_LSB, csc_coeff.b2, 7, 0); REG_FLD_MOD 489 drivers/gpu/drm/omapdrm/dss/hdmi5_core.c REG_FLD_MOD(base, HDMI_CORE_CSC_COEF_B3_MSB, csc_coeff.b3 >> 8, 6, 0); REG_FLD_MOD 490 drivers/gpu/drm/omapdrm/dss/hdmi5_core.c REG_FLD_MOD(base, HDMI_CORE_CSC_COEF_B3_LSB, csc_coeff.b3, 7, 0); REG_FLD_MOD 491 drivers/gpu/drm/omapdrm/dss/hdmi5_core.c REG_FLD_MOD(base, HDMI_CORE_CSC_COEF_B4_MSB, csc_coeff.b4 >> 8, 6, 0); REG_FLD_MOD 492 drivers/gpu/drm/omapdrm/dss/hdmi5_core.c REG_FLD_MOD(base, HDMI_CORE_CSC_COEF_B4_LSB, csc_coeff.b4, 7, 0); REG_FLD_MOD 493 drivers/gpu/drm/omapdrm/dss/hdmi5_core.c REG_FLD_MOD(base, HDMI_CORE_CSC_COEF_C1_MSB, csc_coeff.c1 >> 8, 6, 0); REG_FLD_MOD 494 drivers/gpu/drm/omapdrm/dss/hdmi5_core.c REG_FLD_MOD(base, HDMI_CORE_CSC_COEF_C1_LSB, csc_coeff.c1, 7, 0); REG_FLD_MOD 495 drivers/gpu/drm/omapdrm/dss/hdmi5_core.c REG_FLD_MOD(base, HDMI_CORE_CSC_COEF_C2_MSB, csc_coeff.c2 >> 8, 6, 0); REG_FLD_MOD 496 drivers/gpu/drm/omapdrm/dss/hdmi5_core.c REG_FLD_MOD(base, HDMI_CORE_CSC_COEF_C2_LSB, csc_coeff.c2, 7, 0); REG_FLD_MOD 497 drivers/gpu/drm/omapdrm/dss/hdmi5_core.c REG_FLD_MOD(base, HDMI_CORE_CSC_COEF_C3_MSB, csc_coeff.c3 >> 8, 6, 0); REG_FLD_MOD 498 drivers/gpu/drm/omapdrm/dss/hdmi5_core.c REG_FLD_MOD(base, HDMI_CORE_CSC_COEF_C3_LSB, csc_coeff.c3, 7, 0); REG_FLD_MOD 499 drivers/gpu/drm/omapdrm/dss/hdmi5_core.c REG_FLD_MOD(base, HDMI_CORE_CSC_COEF_C4_MSB, csc_coeff.c4 >> 8, 6, 0); REG_FLD_MOD 500 drivers/gpu/drm/omapdrm/dss/hdmi5_core.c REG_FLD_MOD(base, HDMI_CORE_CSC_COEF_C4_LSB, csc_coeff.c4, 7, 0); REG_FLD_MOD 502 drivers/gpu/drm/omapdrm/dss/hdmi5_core.c REG_FLD_MOD(base, HDMI_CORE_MC_FLOWCTRL, 0x1, 0, 0); REG_FLD_MOD 521 drivers/gpu/drm/omapdrm/dss/hdmi5_core.c REG_FLD_MOD(base, HDMI_CORE_FC_CTRLDUR, 0x0C, 7, 0); REG_FLD_MOD 522 drivers/gpu/drm/omapdrm/dss/hdmi5_core.c REG_FLD_MOD(base, HDMI_CORE_FC_EXCTRLDUR, 0x20, 7, 0); REG_FLD_MOD 523 drivers/gpu/drm/omapdrm/dss/hdmi5_core.c REG_FLD_MOD(base, HDMI_CORE_FC_EXCTRLSPAC, 0x01, 7, 0); REG_FLD_MOD 524 drivers/gpu/drm/omapdrm/dss/hdmi5_core.c REG_FLD_MOD(base, HDMI_CORE_FC_CH0PREAM, 0x0B, 7, 0); REG_FLD_MOD 525 drivers/gpu/drm/omapdrm/dss/hdmi5_core.c REG_FLD_MOD(base, HDMI_CORE_FC_CH1PREAM, 0x16, 5, 0); REG_FLD_MOD 526 drivers/gpu/drm/omapdrm/dss/hdmi5_core.c REG_FLD_MOD(base, HDMI_CORE_FC_CH2PREAM, 0x21, 5, 0); REG_FLD_MOD 527 drivers/gpu/drm/omapdrm/dss/hdmi5_core.c REG_FLD_MOD(base, HDMI_CORE_MC_CLKDIS, 0x00, 0, 0); REG_FLD_MOD 528 drivers/gpu/drm/omapdrm/dss/hdmi5_core.c REG_FLD_MOD(base, HDMI_CORE_MC_CLKDIS, 0x00, 1, 1); REG_FLD_MOD 536 drivers/gpu/drm/omapdrm/dss/hdmi5_core.c REG_FLD_MOD(base, HDMI_CORE_IH_MUTE, 0x3, 1, 0); REG_FLD_MOD 540 drivers/gpu/drm/omapdrm/dss/hdmi5_core.c REG_FLD_MOD(base, HDMI_CORE_VP_MASK, 0xff, 7, 0); REG_FLD_MOD 541 drivers/gpu/drm/omapdrm/dss/hdmi5_core.c REG_FLD_MOD(base, HDMI_CORE_FC_MASK0, 0xe7, 7, 0); REG_FLD_MOD 542 drivers/gpu/drm/omapdrm/dss/hdmi5_core.c REG_FLD_MOD(base, HDMI_CORE_FC_MASK1, 0xfb, 7, 0); REG_FLD_MOD 543 drivers/gpu/drm/omapdrm/dss/hdmi5_core.c REG_FLD_MOD(base, HDMI_CORE_FC_MASK2, 0x3, 1, 0); REG_FLD_MOD 545 drivers/gpu/drm/omapdrm/dss/hdmi5_core.c REG_FLD_MOD(base, HDMI_CORE_AUD_INT, 0x3, 3, 2); REG_FLD_MOD 546 drivers/gpu/drm/omapdrm/dss/hdmi5_core.c REG_FLD_MOD(base, HDMI_CORE_AUD_GP_MASK, 0x3, 1, 0); REG_FLD_MOD 548 drivers/gpu/drm/omapdrm/dss/hdmi5_core.c REG_FLD_MOD(base, HDMI_CORE_CEC_MASK, 0x7f, 6, 0); REG_FLD_MOD 550 drivers/gpu/drm/omapdrm/dss/hdmi5_core.c REG_FLD_MOD(base, HDMI_CORE_I2CM_CTLINT, 0x1, 6, 6); REG_FLD_MOD 551 drivers/gpu/drm/omapdrm/dss/hdmi5_core.c REG_FLD_MOD(base, HDMI_CORE_I2CM_CTLINT, 0x1, 2, 2); REG_FLD_MOD 552 drivers/gpu/drm/omapdrm/dss/hdmi5_core.c REG_FLD_MOD(base, HDMI_CORE_I2CM_INT, 0x1, 2, 2); REG_FLD_MOD 554 drivers/gpu/drm/omapdrm/dss/hdmi5_core.c REG_FLD_MOD(base, HDMI_CORE_PHY_MASK0, 0xf3, 7, 0); REG_FLD_MOD 556 drivers/gpu/drm/omapdrm/dss/hdmi5_core.c REG_FLD_MOD(base, HDMI_CORE_IH_PHY_STAT0, 0xff, 7, 0); REG_FLD_MOD 560 drivers/gpu/drm/omapdrm/dss/hdmi5_core.c REG_FLD_MOD(base, HDMI_CORE_IH_VP_STAT0, 0xff, 7, 0); REG_FLD_MOD 561 drivers/gpu/drm/omapdrm/dss/hdmi5_core.c REG_FLD_MOD(base, HDMI_CORE_IH_FC_STAT0, 0xe7, 7, 0); REG_FLD_MOD 562 drivers/gpu/drm/omapdrm/dss/hdmi5_core.c REG_FLD_MOD(base, HDMI_CORE_IH_FC_STAT1, 0xfb, 7, 0); REG_FLD_MOD 563 drivers/gpu/drm/omapdrm/dss/hdmi5_core.c REG_FLD_MOD(base, HDMI_CORE_IH_FC_STAT2, 0x3, 1, 0); REG_FLD_MOD 565 drivers/gpu/drm/omapdrm/dss/hdmi5_core.c REG_FLD_MOD(base, HDMI_CORE_IH_AS_STAT0, 0x7, 2, 0); REG_FLD_MOD 567 drivers/gpu/drm/omapdrm/dss/hdmi5_core.c REG_FLD_MOD(base, HDMI_CORE_IH_CEC_STAT0, 0x7f, 6, 0); REG_FLD_MOD 569 drivers/gpu/drm/omapdrm/dss/hdmi5_core.c REG_FLD_MOD(base, HDMI_CORE_IH_I2CM_STAT0, 0x3, 1, 0); REG_FLD_MOD 571 drivers/gpu/drm/omapdrm/dss/hdmi5_core.c REG_FLD_MOD(base, HDMI_CORE_IH_PHY_STAT0, 0xff, 7, 0); REG_FLD_MOD 577 drivers/gpu/drm/omapdrm/dss/hdmi5_core.c REG_FLD_MOD(core->base, HDMI_CORE_IH_MUTE, 0x0, 1, 0); REG_FLD_MOD 584 drivers/gpu/drm/omapdrm/dss/hdmi5_core.c REG_FLD_MOD(base, HDMI_CORE_IH_FC_STAT0, 0xff, 7, 0); REG_FLD_MOD 585 drivers/gpu/drm/omapdrm/dss/hdmi5_core.c REG_FLD_MOD(base, HDMI_CORE_IH_FC_STAT1, 0xff, 7, 0); REG_FLD_MOD 586 drivers/gpu/drm/omapdrm/dss/hdmi5_core.c REG_FLD_MOD(base, HDMI_CORE_IH_FC_STAT2, 0xff, 7, 0); REG_FLD_MOD 587 drivers/gpu/drm/omapdrm/dss/hdmi5_core.c REG_FLD_MOD(base, HDMI_CORE_IH_AS_STAT0, 0xff, 7, 0); REG_FLD_MOD 588 drivers/gpu/drm/omapdrm/dss/hdmi5_core.c REG_FLD_MOD(base, HDMI_CORE_IH_PHY_STAT0, 0xff, 7, 0); REG_FLD_MOD 589 drivers/gpu/drm/omapdrm/dss/hdmi5_core.c REG_FLD_MOD(base, HDMI_CORE_IH_I2CM_STAT0, 0xff, 7, 0); REG_FLD_MOD 590 drivers/gpu/drm/omapdrm/dss/hdmi5_core.c REG_FLD_MOD(base, HDMI_CORE_IH_CEC_STAT0, 0xff, 7, 0); REG_FLD_MOD 591 drivers/gpu/drm/omapdrm/dss/hdmi5_core.c REG_FLD_MOD(base, HDMI_CORE_IH_VP_STAT0, 0xff, 7, 0); REG_FLD_MOD 592 drivers/gpu/drm/omapdrm/dss/hdmi5_core.c REG_FLD_MOD(base, HDMI_CORE_IH_I2CMPHY_STAT0, 0xff, 7, 0); REG_FLD_MOD 649 drivers/gpu/drm/omapdrm/dss/hdmi5_core.c REG_FLD_MOD(base, HDMI_CORE_FC_AUDSCONF, 0xf, 7, 4); REG_FLD_MOD 652 drivers/gpu/drm/omapdrm/dss/hdmi5_core.c REG_FLD_MOD(base, HDMI_CORE_AUD_N1, cfg->n, 7, 0); REG_FLD_MOD 653 drivers/gpu/drm/omapdrm/dss/hdmi5_core.c REG_FLD_MOD(base, HDMI_CORE_AUD_N2, cfg->n >> 8, 7, 0); REG_FLD_MOD 654 drivers/gpu/drm/omapdrm/dss/hdmi5_core.c REG_FLD_MOD(base, HDMI_CORE_AUD_N3, cfg->n >> 16, 3, 0); REG_FLD_MOD 660 drivers/gpu/drm/omapdrm/dss/hdmi5_core.c REG_FLD_MOD(base, HDMI_CORE_AUD_CTS3, 1, 4, 4); REG_FLD_MOD 661 drivers/gpu/drm/omapdrm/dss/hdmi5_core.c REG_FLD_MOD(base, HDMI_CORE_AUD_CTS1, cfg->cts, 7, 0); REG_FLD_MOD 662 drivers/gpu/drm/omapdrm/dss/hdmi5_core.c REG_FLD_MOD(base, HDMI_CORE_AUD_CTS2, cfg->cts >> 8, 7, 0); REG_FLD_MOD 663 drivers/gpu/drm/omapdrm/dss/hdmi5_core.c REG_FLD_MOD(base, HDMI_CORE_AUD_CTS3, cfg->cts >> 16, 3, 0); REG_FLD_MOD 667 drivers/gpu/drm/omapdrm/dss/hdmi5_core.c REG_FLD_MOD(base, HDMI_CORE_FC_AUDSCONF, 0, 0, 0); REG_FLD_MOD 669 drivers/gpu/drm/omapdrm/dss/hdmi5_core.c REG_FLD_MOD(base, HDMI_CORE_FC_AUDSCONF, 1, 0, 0); REG_FLD_MOD 673 drivers/gpu/drm/omapdrm/dss/hdmi5_core.c REG_FLD_MOD(base, HDMI_CORE_FC_AUDSV, 0, 0, 0); REG_FLD_MOD 674 drivers/gpu/drm/omapdrm/dss/hdmi5_core.c REG_FLD_MOD(base, HDMI_CORE_FC_AUDSV, 0, 4, 4); REG_FLD_MOD 682 drivers/gpu/drm/omapdrm/dss/hdmi5_core.c REG_FLD_MOD(base, HDMI_CORE_FC_AUDSV, val, 1, 1); REG_FLD_MOD 683 drivers/gpu/drm/omapdrm/dss/hdmi5_core.c REG_FLD_MOD(base, HDMI_CORE_FC_AUDSV, val, 5, 5); REG_FLD_MOD 684 drivers/gpu/drm/omapdrm/dss/hdmi5_core.c REG_FLD_MOD(base, HDMI_CORE_FC_AUDSV, val, 2, 2); REG_FLD_MOD 685 drivers/gpu/drm/omapdrm/dss/hdmi5_core.c REG_FLD_MOD(base, HDMI_CORE_FC_AUDSV, val, 6, 6); REG_FLD_MOD 689 drivers/gpu/drm/omapdrm/dss/hdmi5_core.c REG_FLD_MOD(base, HDMI_CORE_FC_AUDSV, val, 3, 3); REG_FLD_MOD 690 drivers/gpu/drm/omapdrm/dss/hdmi5_core.c REG_FLD_MOD(base, HDMI_CORE_FC_AUDSV, val, 7, 7); REG_FLD_MOD 694 drivers/gpu/drm/omapdrm/dss/hdmi5_core.c REG_FLD_MOD(base, HDMI_CORE_FC_AUDSU, 0, 7, 0); REG_FLD_MOD 699 drivers/gpu/drm/omapdrm/dss/hdmi5_core.c REG_FLD_MOD(base, HDMI_CORE_FC_AUDSCHNLS(0), val, 5, 4); REG_FLD_MOD 704 drivers/gpu/drm/omapdrm/dss/hdmi5_core.c REG_FLD_MOD(base, HDMI_CORE_FC_AUDSCHNLS(0), val, 0, 0); REG_FLD_MOD 712 drivers/gpu/drm/omapdrm/dss/hdmi5_core.c REG_FLD_MOD(base, HDMI_CORE_FC_AUDSCHNLS(2), val, 6, 4); REG_FLD_MOD 716 drivers/gpu/drm/omapdrm/dss/hdmi5_core.c REG_FLD_MOD(base, HDMI_CORE_FC_AUDSCHNLS(2), val, 3, 0); REG_FLD_MOD 719 drivers/gpu/drm/omapdrm/dss/hdmi5_core.c REG_FLD_MOD(base, HDMI_CORE_FC_AUDSCHNLS(3), 2, 3, 0); REG_FLD_MOD 721 drivers/gpu/drm/omapdrm/dss/hdmi5_core.c REG_FLD_MOD(base, HDMI_CORE_FC_AUDSCHNLS(3), 4, 7, 4); REG_FLD_MOD 723 drivers/gpu/drm/omapdrm/dss/hdmi5_core.c REG_FLD_MOD(base, HDMI_CORE_FC_AUDSCHNLS(4), 6, 3, 0); REG_FLD_MOD 725 drivers/gpu/drm/omapdrm/dss/hdmi5_core.c REG_FLD_MOD(base, HDMI_CORE_FC_AUDSCHNLS(4), 8, 7, 4); REG_FLD_MOD 727 drivers/gpu/drm/omapdrm/dss/hdmi5_core.c REG_FLD_MOD(base, HDMI_CORE_FC_AUDSCHNLS(5), 1, 3, 0); REG_FLD_MOD 729 drivers/gpu/drm/omapdrm/dss/hdmi5_core.c REG_FLD_MOD(base, HDMI_CORE_FC_AUDSCHNLS(5), 3, 7, 4); REG_FLD_MOD 731 drivers/gpu/drm/omapdrm/dss/hdmi5_core.c REG_FLD_MOD(base, HDMI_CORE_FC_AUDSCHNLS(6), 5, 3, 0); REG_FLD_MOD 733 drivers/gpu/drm/omapdrm/dss/hdmi5_core.c REG_FLD_MOD(base, HDMI_CORE_FC_AUDSCHNLS(6), 7, 7, 4); REG_FLD_MOD 744 drivers/gpu/drm/omapdrm/dss/hdmi5_core.c REG_FLD_MOD(base, HDMI_CORE_AUD_INT, 3, 3, 2); REG_FLD_MOD 750 drivers/gpu/drm/omapdrm/dss/hdmi5_core.c REG_FLD_MOD(base, HDMI_CORE_AUD_CONF0, 0, 5, 5); REG_FLD_MOD 752 drivers/gpu/drm/omapdrm/dss/hdmi5_core.c REG_FLD_MOD(base, HDMI_CORE_AUD_GP_CONF1, 3, 7, 0); REG_FLD_MOD 755 drivers/gpu/drm/omapdrm/dss/hdmi5_core.c REG_FLD_MOD(base, HDMI_CORE_AUD_CONF0, 0, 5, 5); REG_FLD_MOD 757 drivers/gpu/drm/omapdrm/dss/hdmi5_core.c REG_FLD_MOD(base, HDMI_CORE_AUD_GP_CONF1, 0x3F, 7, 0); REG_FLD_MOD 760 drivers/gpu/drm/omapdrm/dss/hdmi5_core.c REG_FLD_MOD(base, HDMI_CORE_AUD_CONF0, 0, 5, 5); REG_FLD_MOD 762 drivers/gpu/drm/omapdrm/dss/hdmi5_core.c REG_FLD_MOD(base, HDMI_CORE_AUD_GP_CONF1, 0xFF, 7, 0); REG_FLD_MOD 766 drivers/gpu/drm/omapdrm/dss/hdmi5_core.c REG_FLD_MOD(base, HDMI_CORE_AUD_GP_CONF2, 0, 0, 0); REG_FLD_MOD 768 drivers/gpu/drm/omapdrm/dss/hdmi5_core.c REG_FLD_MOD(base, HDMI_CORE_AUD_GP_CONF2, 1, 1, 1); REG_FLD_MOD 770 drivers/gpu/drm/omapdrm/dss/hdmi5_core.c REG_FLD_MOD(base, HDMI_CORE_AUD_GP_MASK, 3, 1, 0); REG_FLD_MOD 772 drivers/gpu/drm/omapdrm/dss/hdmi5_core.c REG_FLD_MOD(base, HDMI_CORE_AUD_GP_POL, 1, 0, 0); REG_FLD_MOD 775 drivers/gpu/drm/omapdrm/dss/hdmi5_core.c REG_FLD_MOD(base, HDMI_CORE_FC_AUDSCONF, 0, 7, 4); REG_FLD_MOD 119 drivers/gpu/drm/omapdrm/dss/hdmi_phy.c REG_FLD_MOD(phy->base, HDMI_TXPHY_PAD_CFG_CTRL, lane_cfg_val, 26, 22); REG_FLD_MOD 120 drivers/gpu/drm/omapdrm/dss/hdmi_phy.c REG_FLD_MOD(phy->base, HDMI_TXPHY_PAD_CFG_CTRL, pol_val, 30, 27); REG_FLD_MOD 139 drivers/gpu/drm/omapdrm/dss/hdmi_phy.c REG_FLD_MOD(phy->base, HDMI_TXPHY_BIST_CONTROL, 1, 11, 11); REG_FLD_MOD 156 drivers/gpu/drm/omapdrm/dss/hdmi_phy.c REG_FLD_MOD(phy->base, HDMI_TXPHY_TX_CTRL, freqout, 31, 30); REG_FLD_MOD 163 drivers/gpu/drm/omapdrm/dss/hdmi_phy.c REG_FLD_MOD(phy->base, HDMI_TXPHY_POWER_CTRL, 0xB, 3, 0); REG_FLD_MOD 74 drivers/gpu/drm/omapdrm/dss/hdmi_wp.c REG_FLD_MOD(wp->base, HDMI_WP_PWR_CTRL, val, 7, 6); REG_FLD_MOD 90 drivers/gpu/drm/omapdrm/dss/hdmi_wp.c REG_FLD_MOD(wp->base, HDMI_WP_PWR_CTRL, val, 3, 2); REG_FLD_MOD 104 drivers/gpu/drm/omapdrm/dss/hdmi_wp.c REG_FLD_MOD(wp->base, HDMI_WP_VIDEO_CFG, true, 31, 31); REG_FLD_MOD 115 drivers/gpu/drm/omapdrm/dss/hdmi_wp.c REG_FLD_MOD(wp->base, HDMI_WP_VIDEO_CFG, false, 31, 31); REG_FLD_MOD 135 drivers/gpu/drm/omapdrm/dss/hdmi_wp.c REG_FLD_MOD(wp->base, HDMI_WP_VIDEO_CFG, video_fmt->packing_mode, REG_FLD_MOD 266 drivers/gpu/drm/omapdrm/dss/hdmi_wp.c REG_FLD_MOD(wp->base, HDMI_WP_AUDIO_CTRL, enable, 31, 31); REG_FLD_MOD 273 drivers/gpu/drm/omapdrm/dss/hdmi_wp.c REG_FLD_MOD(wp->base, HDMI_WP_AUDIO_CTRL, enable, 30, 30); REG_FLD_MOD 276 drivers/video/fbdev/omap2/omapfb/dss/dispc.c REG_FLD_MOD(rfld.reg, val, rfld.high, rfld.low); REG_FLD_MOD 603 drivers/video/fbdev/omap2/omapfb/dss/dispc.c REG_FLD_MOD(DISPC_CONTROL2, 1, 6, 6); REG_FLD_MOD 700 drivers/video/fbdev/omap2/omapfb/dss/dispc.c REG_FLD_MOD(DISPC_OVL_ATTRIBUTES(plane), ct->full_range, 11, 11); REG_FLD_MOD 790 drivers/video/fbdev/omap2/omapfb/dss/dispc.c REG_FLD_MOD(DISPC_OVL_ATTRIBUTES(plane), zorder, 27, 26); REG_FLD_MOD 801 drivers/video/fbdev/omap2/omapfb/dss/dispc.c REG_FLD_MOD(DISPC_OVL_ATTRIBUTES(i), 1, 25, 25); REG_FLD_MOD 810 drivers/video/fbdev/omap2/omapfb/dss/dispc.c REG_FLD_MOD(DISPC_OVL_ATTRIBUTES(plane), enable ? 1 : 0, 28, 28); REG_FLD_MOD 823 drivers/video/fbdev/omap2/omapfb/dss/dispc.c REG_FLD_MOD(DISPC_GLOBAL_ALPHA, global_alpha, shift + 7, shift); REG_FLD_MOD 914 drivers/video/fbdev/omap2/omapfb/dss/dispc.c REG_FLD_MOD(DISPC_OVL_ATTRIBUTES(plane), m, 4, 1); REG_FLD_MOD 924 drivers/video/fbdev/omap2/omapfb/dss/dispc.c REG_FLD_MOD(DISPC_OVL_ATTRIBUTES(plane), 1, 29, 29); REG_FLD_MOD 926 drivers/video/fbdev/omap2/omapfb/dss/dispc.c REG_FLD_MOD(DISPC_OVL_ATTRIBUTES(plane), 0, 29, 29); REG_FLD_MOD 1035 drivers/video/fbdev/omap2/omapfb/dss/dispc.c REG_FLD_MOD(DISPC_OVL_ATTRIBUTES(plane), channel, 18, 16); REG_FLD_MOD 1045 drivers/video/fbdev/omap2/omapfb/dss/dispc.c REG_FLD_MOD(DISPC_OVL_ATTRIBUTES(plane), burst_size, shift + 1, shift); REG_FLD_MOD 1078 drivers/video/fbdev/omap2/omapfb/dss/dispc.c REG_FLD_MOD(DISPC_CONFIG, enable, 9, 9); REG_FLD_MOD 1130 drivers/video/fbdev/omap2/omapfb/dss/dispc.c REG_FLD_MOD(DISPC_OVL_ATTRIBUTES(plane), enable, shift, shift); REG_FLD_MOD 1276 drivers/video/fbdev/omap2/omapfb/dss/dispc.c REG_FLD_MOD(DISPC_CONFIG, enable ? 1 : 0, 14, 14); REG_FLD_MOD 1335 drivers/video/fbdev/omap2/omapfb/dss/dispc.c REG_FLD_MOD(DISPC_OVL_ATTRIBUTES(plane), enable, bit, bit); REG_FLD_MOD 1647 drivers/video/fbdev/omap2/omapfb/dss/dispc.c REG_FLD_MOD(DISPC_OVL_ATTRIBUTES2(plane), 0, 8, 8); REG_FLD_MOD 1700 drivers/video/fbdev/omap2/omapfb/dss/dispc.c REG_FLD_MOD(DISPC_OVL_ATTRIBUTES2(plane), REG_FLD_MOD 1704 drivers/video/fbdev/omap2/omapfb/dss/dispc.c REG_FLD_MOD(DISPC_OVL_ATTRIBUTES(plane), scale_x ? 1 : 0, 5, 5); REG_FLD_MOD 1706 drivers/video/fbdev/omap2/omapfb/dss/dispc.c REG_FLD_MOD(DISPC_OVL_ATTRIBUTES(plane), scale_y ? 1 : 0, 6, 6); REG_FLD_MOD 1790 drivers/video/fbdev/omap2/omapfb/dss/dispc.c REG_FLD_MOD(DISPC_OVL_ATTRIBUTES(plane), vidrot, 13, 12); REG_FLD_MOD 1792 drivers/video/fbdev/omap2/omapfb/dss/dispc.c REG_FLD_MOD(DISPC_OVL_ATTRIBUTES(plane), REG_FLD_MOD 1800 drivers/video/fbdev/omap2/omapfb/dss/dispc.c REG_FLD_MOD(DISPC_OVL_ATTRIBUTES(plane), doublestride, 22, 22); REG_FLD_MOD 2862 drivers/video/fbdev/omap2/omapfb/dss/dispc.c REG_FLD_MOD(DISPC_OVL_ATTRIBUTES2(plane), 0, 7, 0); REG_FLD_MOD 2870 drivers/video/fbdev/omap2/omapfb/dss/dispc.c REG_FLD_MOD(DISPC_OVL_ATTRIBUTES2(plane), wbdelay, 7, 0); REG_FLD_MOD 2880 drivers/video/fbdev/omap2/omapfb/dss/dispc.c REG_FLD_MOD(DISPC_OVL_ATTRIBUTES(plane), enable ? 1 : 0, 0, 0); REG_FLD_MOD 2921 drivers/video/fbdev/omap2/omapfb/dss/dispc.c REG_FLD_MOD(DISPC_CONTROL, act_high ? 1 : 0, 29, 29); REG_FLD_MOD 2929 drivers/video/fbdev/omap2/omapfb/dss/dispc.c REG_FLD_MOD(DISPC_CONTROL, enable ? 1 : 0, 28, 28); REG_FLD_MOD 2937 drivers/video/fbdev/omap2/omapfb/dss/dispc.c REG_FLD_MOD(DISPC_CONTROL, enable ? 1 : 0, 27, 27); REG_FLD_MOD 2953 drivers/video/fbdev/omap2/omapfb/dss/dispc.c REG_FLD_MOD(DISPC_CONFIG, mode, 2, 1); REG_FLD_MOD 2983 drivers/video/fbdev/omap2/omapfb/dss/dispc.c REG_FLD_MOD(DISPC_CONFIG, enable, 18, 18); REG_FLD_MOD 2985 drivers/video/fbdev/omap2/omapfb/dss/dispc.c REG_FLD_MOD(DISPC_CONFIG, enable, 19, 19); REG_FLD_MOD 3819 drivers/video/fbdev/omap2/omapfb/dss/dispc.c REG_FLD_MOD(DISPC_SYSCONFIG, 2, 4, 3); /* SIDLEMODE: smart idle */ REG_FLD_MOD 3824 drivers/video/fbdev/omap2/omapfb/dss/dispc.c REG_FLD_MOD(DISPC_SYSCONFIG, 1, 4, 3); /* SIDLEMODE: no idle */ REG_FLD_MOD 3844 drivers/video/fbdev/omap2/omapfb/dss/dispc.c REG_FLD_MOD(DISPC_CONFIG, 1, 9, 9); REG_FLD_MOD 3857 drivers/video/fbdev/omap2/omapfb/dss/dispc.c REG_FLD_MOD(DISPC_MSTANDBY_CTRL, 1, 0, 0); REG_FLD_MOD 1217 drivers/video/fbdev/omap2/omapfb/dss/dsi.c REG_FLD_MOD(dsidev, DSI_CTRL, enable, 0, 0); /* IF_EN */ REG_FLD_MOD 1306 drivers/video/fbdev/omap2/omapfb/dss/dsi.c REG_FLD_MOD(dsidev, DSI_CLK_CTRL, lp_clk_div, 12, 0); REG_FLD_MOD 1309 drivers/video/fbdev/omap2/omapfb/dss/dsi.c REG_FLD_MOD(dsidev, DSI_CLK_CTRL, dsi_fclk > 30000000 ? 1 : 0, 21, 21); REG_FLD_MOD 1319 drivers/video/fbdev/omap2/omapfb/dss/dsi.c REG_FLD_MOD(dsidev, DSI_CLK_CTRL, 1, 14, 14); /* CIO_CLK_ICG */ REG_FLD_MOD 1328 drivers/video/fbdev/omap2/omapfb/dss/dsi.c REG_FLD_MOD(dsidev, DSI_CLK_CTRL, 0, 14, 14); /* CIO_CLK_ICG */ REG_FLD_MOD 1349 drivers/video/fbdev/omap2/omapfb/dss/dsi.c REG_FLD_MOD(dsidev, DSI_CLK_CTRL, state, 31, 30); REG_FLD_MOD 1748 drivers/video/fbdev/omap2/omapfb/dss/dsi.c REG_FLD_MOD(dsidev, DSI_COMPLEXIO_CFG1, state, 28, 27); REG_FLD_MOD 1973 drivers/video/fbdev/omap2/omapfb/dss/dsi.c REG_FLD_MOD(dsidev, DSI_DSIPHY_CFG10, l, lptxscp_start, 17); REG_FLD_MOD 1978 drivers/video/fbdev/omap2/omapfb/dss/dsi.c REG_FLD_MOD(dsidev, DSI_DSIPHY_CFG10, 1, 27, 27); REG_FLD_MOD 1984 drivers/video/fbdev/omap2/omapfb/dss/dsi.c REG_FLD_MOD(dsidev, DSI_DSIPHY_CFG10, 0, 27, 27); /* ENLPTXSCPDAT */ REG_FLD_MOD 1987 drivers/video/fbdev/omap2/omapfb/dss/dsi.c REG_FLD_MOD(dsidev, DSI_DSIPHY_CFG10, 0, 22, 17); REG_FLD_MOD 2128 drivers/video/fbdev/omap2/omapfb/dss/dsi.c REG_FLD_MOD(dsidev, DSI_CLK_CTRL, 1, 20, 20); /* LP_CLK_ENABLE */ REG_FLD_MOD 2146 drivers/video/fbdev/omap2/omapfb/dss/dsi.c REG_FLD_MOD(dsidev, DSI_TIMING1, 0, 15, 15); REG_FLD_MOD 2152 drivers/video/fbdev/omap2/omapfb/dss/dsi.c REG_FLD_MOD(dsidev, DSI_CLK_CTRL, REG_FLD_MOD 2163 drivers/video/fbdev/omap2/omapfb/dss/dsi.c REG_FLD_MOD(dsidev, DSI_CLK_CTRL, 0, 20, 20); /* LP_CLK_ENABLE */ REG_FLD_MOD 2180 drivers/video/fbdev/omap2/omapfb/dss/dsi.c REG_FLD_MOD(dsidev, DSI_CLK_CTRL, 0, 13, 13); REG_FLD_MOD 2401 drivers/video/fbdev/omap2/omapfb/dss/dsi.c REG_FLD_MOD(dsidev, DSI_VC_CTRL(channel), enable, 0, 0); REG_FLD_MOD 2464 drivers/video/fbdev/omap2/omapfb/dss/dsi.c REG_FLD_MOD(dsidev, DSI_VC_CTRL(channel), source, 1, 1); REG_FLD_MOD 2469 drivers/video/fbdev/omap2/omapfb/dss/dsi.c REG_FLD_MOD(dsidev, DSI_VC_CTRL(channel), enable, 30, 30); REG_FLD_MOD 2492 drivers/video/fbdev/omap2/omapfb/dss/dsi.c REG_FLD_MOD(dsidev, DSI_VC_CTRL(channel), enable, 9, 9); REG_FLD_MOD 2599 drivers/video/fbdev/omap2/omapfb/dss/dsi.c REG_FLD_MOD(dsidev, DSI_VC_CTRL(channel), 1, 6, 6); /* BTA_EN */ REG_FLD_MOD 3124 drivers/video/fbdev/omap2/omapfb/dss/dsi.c REG_FLD_MOD(dsidev, DSI_CLK_CTRL, 0, 13, 13); REG_FLD_MOD 3164 drivers/video/fbdev/omap2/omapfb/dss/dsi.c REG_FLD_MOD(dsidev, DSI_COMPLEXIO_CFG2, mask, 9, 5); REG_FLD_MOD 3180 drivers/video/fbdev/omap2/omapfb/dss/dsi.c REG_FLD_MOD(dsidev, DSI_COMPLEXIO_CFG2, 0, 9, 5); REG_FLD_MOD 3329 drivers/video/fbdev/omap2/omapfb/dss/dsi.c REG_FLD_MOD(dsidev, DSI_CTRL, num_line_buffers, 13, 12); REG_FLD_MOD 3847 drivers/video/fbdev/omap2/omapfb/dss/dsi.c REG_FLD_MOD(dsidev, DSI_VC_CTRL(channel), 1, 4, 4); REG_FLD_MOD 3886 drivers/video/fbdev/omap2/omapfb/dss/dsi.c REG_FLD_MOD(dsidev, DSI_VC_CTRL(channel), 0, 4, 4); REG_FLD_MOD 3969 drivers/video/fbdev/omap2/omapfb/dss/dsi.c REG_FLD_MOD(dsidev, DSI_TIMING2, 0, 15, 15); /* LP_RX_TO */ REG_FLD_MOD 3995 drivers/video/fbdev/omap2/omapfb/dss/dsi.c REG_FLD_MOD(dsidev, DSI_TIMING2, 1, 15, 15); /* LP_RX_TO */ REG_FLD_MOD 285 drivers/video/fbdev/omap2/omapfb/dss/dss.c REG_FLD_MOD(DSS_PLL_CONTROL, 1, 18, 18); /* SDI_PLL_SYSRESET */ REG_FLD_MOD 289 drivers/video/fbdev/omap2/omapfb/dss/dss.c REG_FLD_MOD(DSS_PLL_CONTROL, 1, 28, 28); /* SDI_PLL_GOBIT */ REG_FLD_MOD 301 drivers/video/fbdev/omap2/omapfb/dss/dss.c REG_FLD_MOD(DSS_PLL_CONTROL, 0, 28, 28); REG_FLD_MOD 329 drivers/video/fbdev/omap2/omapfb/dss/dss.c REG_FLD_MOD(DSS_PLL_CONTROL, 0, 18, 18); /* SDI_PLL_SYSRESET */ REG_FLD_MOD 343 drivers/video/fbdev/omap2/omapfb/dss/dss.c REG_FLD_MOD(DSS_PLL_CONTROL, 0, 18, 18); /* SDI_PLL_SYSRESET */ REG_FLD_MOD 417 drivers/video/fbdev/omap2/omapfb/dss/dss.c REG_FLD_MOD(DSS_CONTROL, b, start, end); /* DISPC_CLK_SWITCH */ REG_FLD_MOD 445 drivers/video/fbdev/omap2/omapfb/dss/dss.c REG_FLD_MOD(DSS_CONTROL, b, pos, pos); /* DSIx_CLK_SWITCH */ REG_FLD_MOD 480 drivers/video/fbdev/omap2/omapfb/dss/dss.c REG_FLD_MOD(DSS_CONTROL, b, pos, pos); /* LCDx_CLK_SWITCH */ REG_FLD_MOD 616 drivers/video/fbdev/omap2/omapfb/dss/dss.c REG_FLD_MOD(DSS_CONTROL, l, 6, 6); REG_FLD_MOD 621 drivers/video/fbdev/omap2/omapfb/dss/dss.c REG_FLD_MOD(DSS_CONTROL, enable, 5, 5); /* DAC Power-Down Control */ REG_FLD_MOD 635 drivers/video/fbdev/omap2/omapfb/dss/dss.c REG_FLD_MOD(DSS_CONTROL, src, 15, 15); /* VENC_HDMI_SWITCH */ REG_FLD_MOD 675 drivers/video/fbdev/omap2/omapfb/dss/dss.c REG_FLD_MOD(DSS_CONTROL, val, 17, 17); REG_FLD_MOD 701 drivers/video/fbdev/omap2/omapfb/dss/dss.c REG_FLD_MOD(DSS_CONTROL, val, 17, 16); REG_FLD_MOD 1118 drivers/video/fbdev/omap2/omapfb/dss/dss.c REG_FLD_MOD(DSS_CONTROL, 0, 0, 0); REG_FLD_MOD 1123 drivers/video/fbdev/omap2/omapfb/dss/dss.c REG_FLD_MOD(DSS_CONTROL, 1, 4, 4); /* venc dac demen */ REG_FLD_MOD 1124 drivers/video/fbdev/omap2/omapfb/dss/dss.c REG_FLD_MOD(DSS_CONTROL, 1, 3, 3); /* venc clock 4x enable */ REG_FLD_MOD 1125 drivers/video/fbdev/omap2/omapfb/dss/dss.c REG_FLD_MOD(DSS_CONTROL, 0, 2, 2); /* venc clock mode = normal */ REG_FLD_MOD 41 drivers/video/fbdev/omap2/omapfb/dss/hdmi4_core.c REG_FLD_MOD(base, HDMI_CORE_AV_DPD, 0x7, 2, 0); REG_FLD_MOD 46 drivers/video/fbdev/omap2/omapfb/dss/hdmi4_core.c REG_FLD_MOD(base, HDMI_CORE_DDC_CMD, 0xf, 3, 0); REG_FLD_MOD 56 drivers/video/fbdev/omap2/omapfb/dss/hdmi4_core.c REG_FLD_MOD(base, HDMI_CORE_DDC_CMD, 0xA, 3, 0); REG_FLD_MOD 66 drivers/video/fbdev/omap2/omapfb/dss/hdmi4_core.c REG_FLD_MOD(base, HDMI_CORE_DDC_CMD, 0x9, 3, 0); REG_FLD_MOD 97 drivers/video/fbdev/omap2/omapfb/dss/hdmi4_core.c REG_FLD_MOD(base, HDMI_CORE_DDC_SEGM, ext / 2, 7, 0); REG_FLD_MOD 100 drivers/video/fbdev/omap2/omapfb/dss/hdmi4_core.c REG_FLD_MOD(base, HDMI_CORE_DDC_ADDR, 0xA0 >> 1, 7, 1); REG_FLD_MOD 103 drivers/video/fbdev/omap2/omapfb/dss/hdmi4_core.c REG_FLD_MOD(base, HDMI_CORE_DDC_OFFSET, offset, 7, 0); REG_FLD_MOD 106 drivers/video/fbdev/omap2/omapfb/dss/hdmi4_core.c REG_FLD_MOD(base, HDMI_CORE_DDC_COUNT1, 0x80, 7, 0); REG_FLD_MOD 107 drivers/video/fbdev/omap2/omapfb/dss/hdmi4_core.c REG_FLD_MOD(base, HDMI_CORE_DDC_COUNT2, 0x0, 1, 0); REG_FLD_MOD 111 drivers/video/fbdev/omap2/omapfb/dss/hdmi4_core.c REG_FLD_MOD(base, HDMI_CORE_DDC_CMD, 0x4, 3, 0); REG_FLD_MOD 113 drivers/video/fbdev/omap2/omapfb/dss/hdmi4_core.c REG_FLD_MOD(base, HDMI_CORE_DDC_CMD, 0x2, 3, 0); REG_FLD_MOD 203 drivers/video/fbdev/omap2/omapfb/dss/hdmi4_core.c REG_FLD_MOD(core->base, HDMI_CORE_SYS_SYS_CTRL1, 0x0, 0, 0); REG_FLD_MOD 209 drivers/video/fbdev/omap2/omapfb/dss/hdmi4_core.c REG_FLD_MOD(core->base, HDMI_CORE_SYS_SRST, 0x0, 0, 0); REG_FLD_MOD 215 drivers/video/fbdev/omap2/omapfb/dss/hdmi4_core.c REG_FLD_MOD(core->base, HDMI_CORE_SYS_SRST, 0x1, 0, 0); REG_FLD_MOD 234 drivers/video/fbdev/omap2/omapfb/dss/hdmi4_core.c REG_FLD_MOD(core_sys_base, REG_FLD_MOD 258 drivers/video/fbdev/omap2/omapfb/dss/hdmi4_core.c REG_FLD_MOD(core_sys_base, REG_FLD_MOD 529 drivers/video/fbdev/omap2/omapfb/dss/hdmi4_core.c REG_FLD_MOD(av_base, HDMI_CORE_AV_N_SVAL1, cfg->n, 7, 0); REG_FLD_MOD 530 drivers/video/fbdev/omap2/omapfb/dss/hdmi4_core.c REG_FLD_MOD(av_base, HDMI_CORE_AV_N_SVAL2, cfg->n >> 8, 7, 0); REG_FLD_MOD 531 drivers/video/fbdev/omap2/omapfb/dss/hdmi4_core.c REG_FLD_MOD(av_base, HDMI_CORE_AV_N_SVAL3, cfg->n >> 16, 7, 0); REG_FLD_MOD 534 drivers/video/fbdev/omap2/omapfb/dss/hdmi4_core.c REG_FLD_MOD(av_base, HDMI_CORE_AV_CTS_SVAL1, cfg->cts, 7, 0); REG_FLD_MOD 535 drivers/video/fbdev/omap2/omapfb/dss/hdmi4_core.c REG_FLD_MOD(av_base, REG_FLD_MOD 537 drivers/video/fbdev/omap2/omapfb/dss/hdmi4_core.c REG_FLD_MOD(av_base, REG_FLD_MOD 540 drivers/video/fbdev/omap2/omapfb/dss/hdmi4_core.c REG_FLD_MOD(av_base, HDMI_CORE_AV_AUD_PAR_BUSCLK_1, REG_FLD_MOD 542 drivers/video/fbdev/omap2/omapfb/dss/hdmi4_core.c REG_FLD_MOD(av_base, HDMI_CORE_AV_AUD_PAR_BUSCLK_2, REG_FLD_MOD 544 drivers/video/fbdev/omap2/omapfb/dss/hdmi4_core.c REG_FLD_MOD(av_base, HDMI_CORE_AV_AUD_PAR_BUSCLK_3, REG_FLD_MOD 549 drivers/video/fbdev/omap2/omapfb/dss/hdmi4_core.c REG_FLD_MOD(av_base, REG_FLD_MOD 565 drivers/video/fbdev/omap2/omapfb/dss/hdmi4_core.c REG_FLD_MOD(av_base, HDMI_CORE_AV_ACR_CTRL, 1, 2, 2); REG_FLD_MOD 568 drivers/video/fbdev/omap2/omapfb/dss/hdmi4_core.c REG_FLD_MOD(av_base, HDMI_CORE_AV_SPDIF_CTRL, REG_FLD_MOD 598 drivers/video/fbdev/omap2/omapfb/dss/hdmi4_core.c REG_FLD_MOD(av_base, HDMI_CORE_AV_I2S_IN_LEN, REG_FLD_MOD 602 drivers/video/fbdev/omap2/omapfb/dss/hdmi4_core.c REG_FLD_MOD(av_base, HDMI_CORE_AV_HDMI_CTRL, cfg->layout, 2, 1); REG_FLD_MOD 616 drivers/video/fbdev/omap2/omapfb/dss/hdmi4_core.c REG_FLD_MOD(av_base, HDMI_CORE_AV_SWAP_I2S, 1, 5, 5); REG_FLD_MOD 860 drivers/video/fbdev/omap2/omapfb/dss/hdmi4_core.c REG_FLD_MOD(hdmi_av_base(core), REG_FLD_MOD 870 drivers/video/fbdev/omap2/omapfb/dss/hdmi4_core.c REG_FLD_MOD(hdmi_av_base(core), REG_FLD_MOD 98 drivers/video/fbdev/omap2/omapfb/dss/hdmi5.c REG_FLD_MOD(hdmi.phy.base, HDMI_TXPHY_PAD_CFG_CTRL, 0, 15, 15); REG_FLD_MOD 319 drivers/video/fbdev/omap2/omapfb/dss/hdmi5.c REG_FLD_MOD(hdmi.wp.base, HDMI_WP_SYSCONFIG, 1, 3, 2); REG_FLD_MOD 323 drivers/video/fbdev/omap2/omapfb/dss/hdmi5.c REG_FLD_MOD(hdmi.wp.base, HDMI_WP_SYSCONFIG, idlemode, 3, 2); REG_FLD_MOD 333 drivers/video/fbdev/omap2/omapfb/dss/hdmi5.c REG_FLD_MOD(hdmi.wp.base, HDMI_WP_SYSCONFIG, 1, 3, 2); REG_FLD_MOD 342 drivers/video/fbdev/omap2/omapfb/dss/hdmi5.c REG_FLD_MOD(hd->wp.base, HDMI_WP_SYSCONFIG, hd->wp_idlemode, 3, 2); REG_FLD_MOD 56 drivers/video/fbdev/omap2/omapfb/dss/hdmi5_core.c REG_FLD_MOD(base, HDMI_CORE_I2CM_SOFTRSTZ, 0, 0, 0); REG_FLD_MOD 62 drivers/video/fbdev/omap2/omapfb/dss/hdmi5_core.c REG_FLD_MOD(base, HDMI_CORE_I2CM_DIV, 0, 3, 3); REG_FLD_MOD 66 drivers/video/fbdev/omap2/omapfb/dss/hdmi5_core.c REG_FLD_MOD(base, HDMI_CORE_I2CM_SS_SCL_HCNT_1_ADDR, REG_FLD_MOD 68 drivers/video/fbdev/omap2/omapfb/dss/hdmi5_core.c REG_FLD_MOD(base, HDMI_CORE_I2CM_SS_SCL_HCNT_0_ADDR, REG_FLD_MOD 73 drivers/video/fbdev/omap2/omapfb/dss/hdmi5_core.c REG_FLD_MOD(base, HDMI_CORE_I2CM_SS_SCL_LCNT_1_ADDR, REG_FLD_MOD 75 drivers/video/fbdev/omap2/omapfb/dss/hdmi5_core.c REG_FLD_MOD(base, HDMI_CORE_I2CM_SS_SCL_LCNT_0_ADDR, REG_FLD_MOD 80 drivers/video/fbdev/omap2/omapfb/dss/hdmi5_core.c REG_FLD_MOD(base, HDMI_CORE_I2CM_FS_SCL_HCNT_1_ADDR, REG_FLD_MOD 82 drivers/video/fbdev/omap2/omapfb/dss/hdmi5_core.c REG_FLD_MOD(base, HDMI_CORE_I2CM_FS_SCL_HCNT_0_ADDR, REG_FLD_MOD 87 drivers/video/fbdev/omap2/omapfb/dss/hdmi5_core.c REG_FLD_MOD(base, HDMI_CORE_I2CM_FS_SCL_LCNT_1_ADDR, REG_FLD_MOD 89 drivers/video/fbdev/omap2/omapfb/dss/hdmi5_core.c REG_FLD_MOD(base, HDMI_CORE_I2CM_FS_SCL_LCNT_0_ADDR, REG_FLD_MOD 94 drivers/video/fbdev/omap2/omapfb/dss/hdmi5_core.c REG_FLD_MOD(base, HDMI_CORE_I2CM_SDA_HOLD_ADDR, v & 0xff, 7, 0); REG_FLD_MOD 96 drivers/video/fbdev/omap2/omapfb/dss/hdmi5_core.c REG_FLD_MOD(base, HDMI_CORE_I2CM_SLAVE, 0x50, 6, 0); REG_FLD_MOD 97 drivers/video/fbdev/omap2/omapfb/dss/hdmi5_core.c REG_FLD_MOD(base, HDMI_CORE_I2CM_SEGADDR, 0x30, 6, 0); REG_FLD_MOD 100 drivers/video/fbdev/omap2/omapfb/dss/hdmi5_core.c REG_FLD_MOD(base, HDMI_CORE_I2CM_CTLINT, 0x1, 7, 7); REG_FLD_MOD 103 drivers/video/fbdev/omap2/omapfb/dss/hdmi5_core.c REG_FLD_MOD(base, HDMI_CORE_I2CM_CTLINT, 0x0, 6, 6); REG_FLD_MOD 106 drivers/video/fbdev/omap2/omapfb/dss/hdmi5_core.c REG_FLD_MOD(base, HDMI_CORE_I2CM_CTLINT, 0x1, 3, 3); REG_FLD_MOD 109 drivers/video/fbdev/omap2/omapfb/dss/hdmi5_core.c REG_FLD_MOD(base, HDMI_CORE_I2CM_CTLINT, 0x0, 2, 2); REG_FLD_MOD 112 drivers/video/fbdev/omap2/omapfb/dss/hdmi5_core.c REG_FLD_MOD(base, HDMI_CORE_I2CM_INT, 0x1, 3, 3); REG_FLD_MOD 115 drivers/video/fbdev/omap2/omapfb/dss/hdmi5_core.c REG_FLD_MOD(base, HDMI_CORE_I2CM_INT, 0x0, 2, 2); REG_FLD_MOD 123 drivers/video/fbdev/omap2/omapfb/dss/hdmi5_core.c REG_FLD_MOD(base, HDMI_CORE_I2CM_CTLINT, 0x1, 6, 6); REG_FLD_MOD 124 drivers/video/fbdev/omap2/omapfb/dss/hdmi5_core.c REG_FLD_MOD(base, HDMI_CORE_I2CM_CTLINT, 0x1, 2, 2); REG_FLD_MOD 125 drivers/video/fbdev/omap2/omapfb/dss/hdmi5_core.c REG_FLD_MOD(base, HDMI_CORE_I2CM_INT, 0x1, 2, 2); REG_FLD_MOD 137 drivers/video/fbdev/omap2/omapfb/dss/hdmi5_core.c REG_FLD_MOD(base, HDMI_CORE_I2CM_SEGPTR, seg_ptr, 7, 0); REG_FLD_MOD 147 drivers/video/fbdev/omap2/omapfb/dss/hdmi5_core.c REG_FLD_MOD(base, HDMI_CORE_IH_I2CM_STAT0, 0x3, 1, 0); REG_FLD_MOD 149 drivers/video/fbdev/omap2/omapfb/dss/hdmi5_core.c REG_FLD_MOD(base, HDMI_CORE_I2CM_ADDRESS, REG_FLD_MOD 153 drivers/video/fbdev/omap2/omapfb/dss/hdmi5_core.c REG_FLD_MOD(base, HDMI_CORE_I2CM_OPERATION, 1, 1, 1); REG_FLD_MOD 155 drivers/video/fbdev/omap2/omapfb/dss/hdmi5_core.c REG_FLD_MOD(base, HDMI_CORE_I2CM_OPERATION, 1, 0, 0); REG_FLD_MOD 328 drivers/video/fbdev/omap2/omapfb/dss/hdmi5_core.c REG_FLD_MOD(base, HDMI_CORE_FC_INHACTIV1, REG_FLD_MOD 330 drivers/video/fbdev/omap2/omapfb/dss/hdmi5_core.c REG_FLD_MOD(base, HDMI_CORE_FC_INHACTIV0, REG_FLD_MOD 334 drivers/video/fbdev/omap2/omapfb/dss/hdmi5_core.c REG_FLD_MOD(base, HDMI_CORE_FC_INVACTIV1, REG_FLD_MOD 336 drivers/video/fbdev/omap2/omapfb/dss/hdmi5_core.c REG_FLD_MOD(base, HDMI_CORE_FC_INVACTIV0, REG_FLD_MOD 340 drivers/video/fbdev/omap2/omapfb/dss/hdmi5_core.c REG_FLD_MOD(base, HDMI_CORE_FC_INHBLANK1, cfg->hblank >> 8, 4, 0); REG_FLD_MOD 341 drivers/video/fbdev/omap2/omapfb/dss/hdmi5_core.c REG_FLD_MOD(base, HDMI_CORE_FC_INHBLANK0, cfg->hblank & 0xFF, 7, 0); REG_FLD_MOD 344 drivers/video/fbdev/omap2/omapfb/dss/hdmi5_core.c REG_FLD_MOD(base, HDMI_CORE_FC_INVBLANK, cfg->vblank, 7, 0); REG_FLD_MOD 347 drivers/video/fbdev/omap2/omapfb/dss/hdmi5_core.c REG_FLD_MOD(base, HDMI_CORE_FC_HSYNCINDELAY1, REG_FLD_MOD 349 drivers/video/fbdev/omap2/omapfb/dss/hdmi5_core.c REG_FLD_MOD(base, HDMI_CORE_FC_HSYNCINDELAY0, REG_FLD_MOD 353 drivers/video/fbdev/omap2/omapfb/dss/hdmi5_core.c REG_FLD_MOD(base, HDMI_CORE_FC_VSYNCINDELAY, REG_FLD_MOD 357 drivers/video/fbdev/omap2/omapfb/dss/hdmi5_core.c REG_FLD_MOD(base, HDMI_CORE_FC_HSYNCINWIDTH1, REG_FLD_MOD 359 drivers/video/fbdev/omap2/omapfb/dss/hdmi5_core.c REG_FLD_MOD(base, HDMI_CORE_FC_HSYNCINWIDTH0, REG_FLD_MOD 363 drivers/video/fbdev/omap2/omapfb/dss/hdmi5_core.c REG_FLD_MOD(base, HDMI_CORE_FC_VSYNCINWIDTH, REG_FLD_MOD 367 drivers/video/fbdev/omap2/omapfb/dss/hdmi5_core.c REG_FLD_MOD(base, HDMI_CORE_FC_INVIDCONF, REG_FLD_MOD 377 drivers/video/fbdev/omap2/omapfb/dss/hdmi5_core.c REG_FLD_MOD(base, HDMI_CORE_VP_PR_CD, clr_depth, 7, 4); REG_FLD_MOD 379 drivers/video/fbdev/omap2/omapfb/dss/hdmi5_core.c REG_FLD_MOD(base, HDMI_CORE_VP_CONF, clr_depth ? 0 : 1, 6, 6); REG_FLD_MOD 381 drivers/video/fbdev/omap2/omapfb/dss/hdmi5_core.c REG_FLD_MOD(base, HDMI_CORE_VP_CONF, clr_depth ? 1 : 0, 5, 5); REG_FLD_MOD 383 drivers/video/fbdev/omap2/omapfb/dss/hdmi5_core.c REG_FLD_MOD(base, HDMI_CORE_VP_CONF, 0, 3, 3); REG_FLD_MOD 385 drivers/video/fbdev/omap2/omapfb/dss/hdmi5_core.c REG_FLD_MOD(base, HDMI_CORE_VP_STUFF, clr_depth ? 1 : 0, 1, 1); REG_FLD_MOD 387 drivers/video/fbdev/omap2/omapfb/dss/hdmi5_core.c REG_FLD_MOD(base, HDMI_CORE_VP_STUFF, 1, 2, 2); REG_FLD_MOD 389 drivers/video/fbdev/omap2/omapfb/dss/hdmi5_core.c REG_FLD_MOD(base, HDMI_CORE_VP_CONF, clr_depth ? 0 : 2, 1, 0); REG_FLD_MOD 397 drivers/video/fbdev/omap2/omapfb/dss/hdmi5_core.c REG_FLD_MOD(core->base, HDMI_CORE_CSC_SCALE, clr_depth, 7, 4); REG_FLD_MOD 405 drivers/video/fbdev/omap2/omapfb/dss/hdmi5_core.c REG_FLD_MOD(core->base, HDMI_CORE_TX_INVID0, video_mapping, 4, 0); REG_FLD_MOD 461 drivers/video/fbdev/omap2/omapfb/dss/hdmi5_core.c REG_FLD_MOD(base, HDMI_CORE_FC_PRCONF, pr, 3, 0); REG_FLD_MOD 469 drivers/video/fbdev/omap2/omapfb/dss/hdmi5_core.c REG_FLD_MOD(base, HDMI_CORE_CSC_COEF_A1_MSB, csc_coeff.a1 >> 8 , 6, 0); REG_FLD_MOD 470 drivers/video/fbdev/omap2/omapfb/dss/hdmi5_core.c REG_FLD_MOD(base, HDMI_CORE_CSC_COEF_A1_LSB, csc_coeff.a1, 7, 0); REG_FLD_MOD 471 drivers/video/fbdev/omap2/omapfb/dss/hdmi5_core.c REG_FLD_MOD(base, HDMI_CORE_CSC_COEF_A2_MSB, csc_coeff.a2 >> 8, 6, 0); REG_FLD_MOD 472 drivers/video/fbdev/omap2/omapfb/dss/hdmi5_core.c REG_FLD_MOD(base, HDMI_CORE_CSC_COEF_A2_LSB, csc_coeff.a2, 7, 0); REG_FLD_MOD 473 drivers/video/fbdev/omap2/omapfb/dss/hdmi5_core.c REG_FLD_MOD(base, HDMI_CORE_CSC_COEF_A3_MSB, csc_coeff.a3 >> 8, 6, 0); REG_FLD_MOD 474 drivers/video/fbdev/omap2/omapfb/dss/hdmi5_core.c REG_FLD_MOD(base, HDMI_CORE_CSC_COEF_A3_LSB, csc_coeff.a3, 7, 0); REG_FLD_MOD 475 drivers/video/fbdev/omap2/omapfb/dss/hdmi5_core.c REG_FLD_MOD(base, HDMI_CORE_CSC_COEF_A4_MSB, csc_coeff.a4 >> 8, 6, 0); REG_FLD_MOD 476 drivers/video/fbdev/omap2/omapfb/dss/hdmi5_core.c REG_FLD_MOD(base, HDMI_CORE_CSC_COEF_A4_LSB, csc_coeff.a4, 7, 0); REG_FLD_MOD 477 drivers/video/fbdev/omap2/omapfb/dss/hdmi5_core.c REG_FLD_MOD(base, HDMI_CORE_CSC_COEF_B1_MSB, csc_coeff.b1 >> 8, 6, 0); REG_FLD_MOD 478 drivers/video/fbdev/omap2/omapfb/dss/hdmi5_core.c REG_FLD_MOD(base, HDMI_CORE_CSC_COEF_B1_LSB, csc_coeff.b1, 7, 0); REG_FLD_MOD 479 drivers/video/fbdev/omap2/omapfb/dss/hdmi5_core.c REG_FLD_MOD(base, HDMI_CORE_CSC_COEF_B2_MSB, csc_coeff.b2 >> 8, 6, 0); REG_FLD_MOD 480 drivers/video/fbdev/omap2/omapfb/dss/hdmi5_core.c REG_FLD_MOD(base, HDMI_CORE_CSC_COEF_B2_LSB, csc_coeff.b2, 7, 0); REG_FLD_MOD 481 drivers/video/fbdev/omap2/omapfb/dss/hdmi5_core.c REG_FLD_MOD(base, HDMI_CORE_CSC_COEF_B3_MSB, csc_coeff.b3 >> 8, 6, 0); REG_FLD_MOD 482 drivers/video/fbdev/omap2/omapfb/dss/hdmi5_core.c REG_FLD_MOD(base, HDMI_CORE_CSC_COEF_B3_LSB, csc_coeff.b3, 7, 0); REG_FLD_MOD 483 drivers/video/fbdev/omap2/omapfb/dss/hdmi5_core.c REG_FLD_MOD(base, HDMI_CORE_CSC_COEF_B4_MSB, csc_coeff.b4 >> 8, 6, 0); REG_FLD_MOD 484 drivers/video/fbdev/omap2/omapfb/dss/hdmi5_core.c REG_FLD_MOD(base, HDMI_CORE_CSC_COEF_B4_LSB, csc_coeff.b4, 7, 0); REG_FLD_MOD 485 drivers/video/fbdev/omap2/omapfb/dss/hdmi5_core.c REG_FLD_MOD(base, HDMI_CORE_CSC_COEF_C1_MSB, csc_coeff.c1 >> 8, 6, 0); REG_FLD_MOD 486 drivers/video/fbdev/omap2/omapfb/dss/hdmi5_core.c REG_FLD_MOD(base, HDMI_CORE_CSC_COEF_C1_LSB, csc_coeff.c1, 7, 0); REG_FLD_MOD 487 drivers/video/fbdev/omap2/omapfb/dss/hdmi5_core.c REG_FLD_MOD(base, HDMI_CORE_CSC_COEF_C2_MSB, csc_coeff.c2 >> 8, 6, 0); REG_FLD_MOD 488 drivers/video/fbdev/omap2/omapfb/dss/hdmi5_core.c REG_FLD_MOD(base, HDMI_CORE_CSC_COEF_C2_LSB, csc_coeff.c2, 7, 0); REG_FLD_MOD 489 drivers/video/fbdev/omap2/omapfb/dss/hdmi5_core.c REG_FLD_MOD(base, HDMI_CORE_CSC_COEF_C3_MSB, csc_coeff.c3 >> 8, 6, 0); REG_FLD_MOD 490 drivers/video/fbdev/omap2/omapfb/dss/hdmi5_core.c REG_FLD_MOD(base, HDMI_CORE_CSC_COEF_C3_LSB, csc_coeff.c3, 7, 0); REG_FLD_MOD 491 drivers/video/fbdev/omap2/omapfb/dss/hdmi5_core.c REG_FLD_MOD(base, HDMI_CORE_CSC_COEF_C4_MSB, csc_coeff.c4 >> 8, 6, 0); REG_FLD_MOD 492 drivers/video/fbdev/omap2/omapfb/dss/hdmi5_core.c REG_FLD_MOD(base, HDMI_CORE_CSC_COEF_C4_LSB, csc_coeff.c4, 7, 0); REG_FLD_MOD 494 drivers/video/fbdev/omap2/omapfb/dss/hdmi5_core.c REG_FLD_MOD(base, HDMI_CORE_MC_FLOWCTRL, 0x1, 0, 0); REG_FLD_MOD 513 drivers/video/fbdev/omap2/omapfb/dss/hdmi5_core.c REG_FLD_MOD(base, HDMI_CORE_FC_CTRLDUR, 0x0C, 7, 0); REG_FLD_MOD 514 drivers/video/fbdev/omap2/omapfb/dss/hdmi5_core.c REG_FLD_MOD(base, HDMI_CORE_FC_EXCTRLDUR, 0x20, 7, 0); REG_FLD_MOD 515 drivers/video/fbdev/omap2/omapfb/dss/hdmi5_core.c REG_FLD_MOD(base, HDMI_CORE_FC_EXCTRLSPAC, 0x01, 7, 0); REG_FLD_MOD 516 drivers/video/fbdev/omap2/omapfb/dss/hdmi5_core.c REG_FLD_MOD(base, HDMI_CORE_FC_CH0PREAM, 0x0B, 7, 0); REG_FLD_MOD 517 drivers/video/fbdev/omap2/omapfb/dss/hdmi5_core.c REG_FLD_MOD(base, HDMI_CORE_FC_CH1PREAM, 0x16, 5, 0); REG_FLD_MOD 518 drivers/video/fbdev/omap2/omapfb/dss/hdmi5_core.c REG_FLD_MOD(base, HDMI_CORE_FC_CH2PREAM, 0x21, 5, 0); REG_FLD_MOD 519 drivers/video/fbdev/omap2/omapfb/dss/hdmi5_core.c REG_FLD_MOD(base, HDMI_CORE_MC_CLKDIS, 0x00, 0, 0); REG_FLD_MOD 520 drivers/video/fbdev/omap2/omapfb/dss/hdmi5_core.c REG_FLD_MOD(base, HDMI_CORE_MC_CLKDIS, 0x00, 1, 1); REG_FLD_MOD 528 drivers/video/fbdev/omap2/omapfb/dss/hdmi5_core.c REG_FLD_MOD(base, HDMI_CORE_IH_MUTE, 0x3, 1, 0); REG_FLD_MOD 532 drivers/video/fbdev/omap2/omapfb/dss/hdmi5_core.c REG_FLD_MOD(base, HDMI_CORE_VP_MASK, 0xff, 7, 0); REG_FLD_MOD 533 drivers/video/fbdev/omap2/omapfb/dss/hdmi5_core.c REG_FLD_MOD(base, HDMI_CORE_FC_MASK0, 0xe7, 7, 0); REG_FLD_MOD 534 drivers/video/fbdev/omap2/omapfb/dss/hdmi5_core.c REG_FLD_MOD(base, HDMI_CORE_FC_MASK1, 0xfb, 7, 0); REG_FLD_MOD 535 drivers/video/fbdev/omap2/omapfb/dss/hdmi5_core.c REG_FLD_MOD(base, HDMI_CORE_FC_MASK2, 0x3, 1, 0); REG_FLD_MOD 537 drivers/video/fbdev/omap2/omapfb/dss/hdmi5_core.c REG_FLD_MOD(base, HDMI_CORE_AUD_INT, 0x3, 3, 2); REG_FLD_MOD 538 drivers/video/fbdev/omap2/omapfb/dss/hdmi5_core.c REG_FLD_MOD(base, HDMI_CORE_AUD_GP_MASK, 0x3, 1, 0); REG_FLD_MOD 540 drivers/video/fbdev/omap2/omapfb/dss/hdmi5_core.c REG_FLD_MOD(base, HDMI_CORE_CEC_MASK, 0x7f, 6, 0); REG_FLD_MOD 542 drivers/video/fbdev/omap2/omapfb/dss/hdmi5_core.c REG_FLD_MOD(base, HDMI_CORE_I2CM_CTLINT, 0x1, 6, 6); REG_FLD_MOD 543 drivers/video/fbdev/omap2/omapfb/dss/hdmi5_core.c REG_FLD_MOD(base, HDMI_CORE_I2CM_CTLINT, 0x1, 2, 2); REG_FLD_MOD 544 drivers/video/fbdev/omap2/omapfb/dss/hdmi5_core.c REG_FLD_MOD(base, HDMI_CORE_I2CM_INT, 0x1, 2, 2); REG_FLD_MOD 546 drivers/video/fbdev/omap2/omapfb/dss/hdmi5_core.c REG_FLD_MOD(base, HDMI_CORE_PHY_MASK0, 0xf3, 7, 0); REG_FLD_MOD 548 drivers/video/fbdev/omap2/omapfb/dss/hdmi5_core.c REG_FLD_MOD(base, HDMI_CORE_IH_PHY_STAT0, 0xff, 7, 0); REG_FLD_MOD 552 drivers/video/fbdev/omap2/omapfb/dss/hdmi5_core.c REG_FLD_MOD(base, HDMI_CORE_IH_VP_STAT0, 0xff, 7, 0); REG_FLD_MOD 553 drivers/video/fbdev/omap2/omapfb/dss/hdmi5_core.c REG_FLD_MOD(base, HDMI_CORE_IH_FC_STAT0, 0xe7, 7, 0); REG_FLD_MOD 554 drivers/video/fbdev/omap2/omapfb/dss/hdmi5_core.c REG_FLD_MOD(base, HDMI_CORE_IH_FC_STAT1, 0xfb, 7, 0); REG_FLD_MOD 555 drivers/video/fbdev/omap2/omapfb/dss/hdmi5_core.c REG_FLD_MOD(base, HDMI_CORE_IH_FC_STAT2, 0x3, 1, 0); REG_FLD_MOD 557 drivers/video/fbdev/omap2/omapfb/dss/hdmi5_core.c REG_FLD_MOD(base, HDMI_CORE_IH_AS_STAT0, 0x7, 2, 0); REG_FLD_MOD 559 drivers/video/fbdev/omap2/omapfb/dss/hdmi5_core.c REG_FLD_MOD(base, HDMI_CORE_IH_CEC_STAT0, 0x7f, 6, 0); REG_FLD_MOD 561 drivers/video/fbdev/omap2/omapfb/dss/hdmi5_core.c REG_FLD_MOD(base, HDMI_CORE_IH_I2CM_STAT0, 0x3, 1, 0); REG_FLD_MOD 563 drivers/video/fbdev/omap2/omapfb/dss/hdmi5_core.c REG_FLD_MOD(base, HDMI_CORE_IH_PHY_STAT0, 0xff, 7, 0); REG_FLD_MOD 569 drivers/video/fbdev/omap2/omapfb/dss/hdmi5_core.c REG_FLD_MOD(core->base, HDMI_CORE_IH_MUTE, 0x0, 1, 0); REG_FLD_MOD 576 drivers/video/fbdev/omap2/omapfb/dss/hdmi5_core.c REG_FLD_MOD(base, HDMI_CORE_IH_FC_STAT0, 0xff, 7, 0); REG_FLD_MOD 577 drivers/video/fbdev/omap2/omapfb/dss/hdmi5_core.c REG_FLD_MOD(base, HDMI_CORE_IH_FC_STAT1, 0xff, 7, 0); REG_FLD_MOD 578 drivers/video/fbdev/omap2/omapfb/dss/hdmi5_core.c REG_FLD_MOD(base, HDMI_CORE_IH_FC_STAT2, 0xff, 7, 0); REG_FLD_MOD 579 drivers/video/fbdev/omap2/omapfb/dss/hdmi5_core.c REG_FLD_MOD(base, HDMI_CORE_IH_AS_STAT0, 0xff, 7, 0); REG_FLD_MOD 580 drivers/video/fbdev/omap2/omapfb/dss/hdmi5_core.c REG_FLD_MOD(base, HDMI_CORE_IH_PHY_STAT0, 0xff, 7, 0); REG_FLD_MOD 581 drivers/video/fbdev/omap2/omapfb/dss/hdmi5_core.c REG_FLD_MOD(base, HDMI_CORE_IH_I2CM_STAT0, 0xff, 7, 0); REG_FLD_MOD 582 drivers/video/fbdev/omap2/omapfb/dss/hdmi5_core.c REG_FLD_MOD(base, HDMI_CORE_IH_CEC_STAT0, 0xff, 7, 0); REG_FLD_MOD 583 drivers/video/fbdev/omap2/omapfb/dss/hdmi5_core.c REG_FLD_MOD(base, HDMI_CORE_IH_VP_STAT0, 0xff, 7, 0); REG_FLD_MOD 584 drivers/video/fbdev/omap2/omapfb/dss/hdmi5_core.c REG_FLD_MOD(base, HDMI_CORE_IH_I2CMPHY_STAT0, 0xff, 7, 0); REG_FLD_MOD 641 drivers/video/fbdev/omap2/omapfb/dss/hdmi5_core.c REG_FLD_MOD(base, HDMI_CORE_FC_AUDSCONF, 0xf, 7, 4); REG_FLD_MOD 644 drivers/video/fbdev/omap2/omapfb/dss/hdmi5_core.c REG_FLD_MOD(base, HDMI_CORE_AUD_N1, cfg->n, 7, 0); REG_FLD_MOD 645 drivers/video/fbdev/omap2/omapfb/dss/hdmi5_core.c REG_FLD_MOD(base, HDMI_CORE_AUD_N2, cfg->n >> 8, 7, 0); REG_FLD_MOD 646 drivers/video/fbdev/omap2/omapfb/dss/hdmi5_core.c REG_FLD_MOD(base, HDMI_CORE_AUD_N3, cfg->n >> 16, 3, 0); REG_FLD_MOD 652 drivers/video/fbdev/omap2/omapfb/dss/hdmi5_core.c REG_FLD_MOD(base, HDMI_CORE_AUD_CTS3, 1, 4, 4); REG_FLD_MOD 653 drivers/video/fbdev/omap2/omapfb/dss/hdmi5_core.c REG_FLD_MOD(base, HDMI_CORE_AUD_CTS1, cfg->cts, 7, 0); REG_FLD_MOD 654 drivers/video/fbdev/omap2/omapfb/dss/hdmi5_core.c REG_FLD_MOD(base, HDMI_CORE_AUD_CTS2, cfg->cts >> 8, 7, 0); REG_FLD_MOD 655 drivers/video/fbdev/omap2/omapfb/dss/hdmi5_core.c REG_FLD_MOD(base, HDMI_CORE_AUD_CTS3, cfg->cts >> 16, 3, 0); REG_FLD_MOD 659 drivers/video/fbdev/omap2/omapfb/dss/hdmi5_core.c REG_FLD_MOD(base, HDMI_CORE_FC_AUDSCONF, 0, 0, 0); REG_FLD_MOD 661 drivers/video/fbdev/omap2/omapfb/dss/hdmi5_core.c REG_FLD_MOD(base, HDMI_CORE_FC_AUDSCONF, 1, 0, 0); REG_FLD_MOD 665 drivers/video/fbdev/omap2/omapfb/dss/hdmi5_core.c REG_FLD_MOD(base, HDMI_CORE_FC_AUDSV, 0, 0, 0); REG_FLD_MOD 666 drivers/video/fbdev/omap2/omapfb/dss/hdmi5_core.c REG_FLD_MOD(base, HDMI_CORE_FC_AUDSV, 0, 4, 4); REG_FLD_MOD 674 drivers/video/fbdev/omap2/omapfb/dss/hdmi5_core.c REG_FLD_MOD(base, HDMI_CORE_FC_AUDSV, val, 1, 1); REG_FLD_MOD 675 drivers/video/fbdev/omap2/omapfb/dss/hdmi5_core.c REG_FLD_MOD(base, HDMI_CORE_FC_AUDSV, val, 5, 5); REG_FLD_MOD 676 drivers/video/fbdev/omap2/omapfb/dss/hdmi5_core.c REG_FLD_MOD(base, HDMI_CORE_FC_AUDSV, val, 2, 2); REG_FLD_MOD 677 drivers/video/fbdev/omap2/omapfb/dss/hdmi5_core.c REG_FLD_MOD(base, HDMI_CORE_FC_AUDSV, val, 6, 6); REG_FLD_MOD 681 drivers/video/fbdev/omap2/omapfb/dss/hdmi5_core.c REG_FLD_MOD(base, HDMI_CORE_FC_AUDSV, val, 3, 3); REG_FLD_MOD 682 drivers/video/fbdev/omap2/omapfb/dss/hdmi5_core.c REG_FLD_MOD(base, HDMI_CORE_FC_AUDSV, val, 7, 7); REG_FLD_MOD 686 drivers/video/fbdev/omap2/omapfb/dss/hdmi5_core.c REG_FLD_MOD(base, HDMI_CORE_FC_AUDSU, 0, 7, 0); REG_FLD_MOD 691 drivers/video/fbdev/omap2/omapfb/dss/hdmi5_core.c REG_FLD_MOD(base, HDMI_CORE_FC_AUDSCHNLS(0), val, 5, 4); REG_FLD_MOD 696 drivers/video/fbdev/omap2/omapfb/dss/hdmi5_core.c REG_FLD_MOD(base, HDMI_CORE_FC_AUDSCHNLS(0), val, 0, 0); REG_FLD_MOD 704 drivers/video/fbdev/omap2/omapfb/dss/hdmi5_core.c REG_FLD_MOD(base, HDMI_CORE_FC_AUDSCHNLS(2), val, 6, 4); REG_FLD_MOD 708 drivers/video/fbdev/omap2/omapfb/dss/hdmi5_core.c REG_FLD_MOD(base, HDMI_CORE_FC_AUDSCHNLS(2), val, 3, 0); REG_FLD_MOD 711 drivers/video/fbdev/omap2/omapfb/dss/hdmi5_core.c REG_FLD_MOD(base, HDMI_CORE_FC_AUDSCHNLS(3), 2, 3, 0); REG_FLD_MOD 713 drivers/video/fbdev/omap2/omapfb/dss/hdmi5_core.c REG_FLD_MOD(base, HDMI_CORE_FC_AUDSCHNLS(3), 4, 7, 4); REG_FLD_MOD 715 drivers/video/fbdev/omap2/omapfb/dss/hdmi5_core.c REG_FLD_MOD(base, HDMI_CORE_FC_AUDSCHNLS(4), 6, 3, 0); REG_FLD_MOD 717 drivers/video/fbdev/omap2/omapfb/dss/hdmi5_core.c REG_FLD_MOD(base, HDMI_CORE_FC_AUDSCHNLS(4), 8, 7, 4); REG_FLD_MOD 719 drivers/video/fbdev/omap2/omapfb/dss/hdmi5_core.c REG_FLD_MOD(base, HDMI_CORE_FC_AUDSCHNLS(5), 1, 3, 0); REG_FLD_MOD 721 drivers/video/fbdev/omap2/omapfb/dss/hdmi5_core.c REG_FLD_MOD(base, HDMI_CORE_FC_AUDSCHNLS(5), 3, 7, 4); REG_FLD_MOD 723 drivers/video/fbdev/omap2/omapfb/dss/hdmi5_core.c REG_FLD_MOD(base, HDMI_CORE_FC_AUDSCHNLS(6), 5, 3, 0); REG_FLD_MOD 725 drivers/video/fbdev/omap2/omapfb/dss/hdmi5_core.c REG_FLD_MOD(base, HDMI_CORE_FC_AUDSCHNLS(6), 7, 7, 4); REG_FLD_MOD 736 drivers/video/fbdev/omap2/omapfb/dss/hdmi5_core.c REG_FLD_MOD(base, HDMI_CORE_AUD_INT, 3, 3, 2); REG_FLD_MOD 742 drivers/video/fbdev/omap2/omapfb/dss/hdmi5_core.c REG_FLD_MOD(base, HDMI_CORE_AUD_CONF0, 0, 5, 5); REG_FLD_MOD 744 drivers/video/fbdev/omap2/omapfb/dss/hdmi5_core.c REG_FLD_MOD(base, HDMI_CORE_AUD_GP_CONF1, 3, 7, 0); REG_FLD_MOD 747 drivers/video/fbdev/omap2/omapfb/dss/hdmi5_core.c REG_FLD_MOD(base, HDMI_CORE_AUD_CONF0, 0, 5, 5); REG_FLD_MOD 749 drivers/video/fbdev/omap2/omapfb/dss/hdmi5_core.c REG_FLD_MOD(base, HDMI_CORE_AUD_GP_CONF1, 0x3F, 7, 0); REG_FLD_MOD 752 drivers/video/fbdev/omap2/omapfb/dss/hdmi5_core.c REG_FLD_MOD(base, HDMI_CORE_AUD_CONF0, 0, 5, 5); REG_FLD_MOD 754 drivers/video/fbdev/omap2/omapfb/dss/hdmi5_core.c REG_FLD_MOD(base, HDMI_CORE_AUD_GP_CONF1, 0xFF, 7, 0); REG_FLD_MOD 758 drivers/video/fbdev/omap2/omapfb/dss/hdmi5_core.c REG_FLD_MOD(base, HDMI_CORE_AUD_GP_CONF2, 0, 0, 0); REG_FLD_MOD 760 drivers/video/fbdev/omap2/omapfb/dss/hdmi5_core.c REG_FLD_MOD(base, HDMI_CORE_AUD_GP_CONF2, 1, 1, 1); REG_FLD_MOD 762 drivers/video/fbdev/omap2/omapfb/dss/hdmi5_core.c REG_FLD_MOD(base, HDMI_CORE_AUD_GP_MASK, 3, 1, 0); REG_FLD_MOD 764 drivers/video/fbdev/omap2/omapfb/dss/hdmi5_core.c REG_FLD_MOD(base, HDMI_CORE_AUD_GP_POL, 1, 0, 0); REG_FLD_MOD 767 drivers/video/fbdev/omap2/omapfb/dss/hdmi5_core.c REG_FLD_MOD(base, HDMI_CORE_FC_AUDSCONF, 0, 7, 4); REG_FLD_MOD 128 drivers/video/fbdev/omap2/omapfb/dss/hdmi_phy.c REG_FLD_MOD(phy->base, HDMI_TXPHY_PAD_CFG_CTRL, lane_cfg_val, 26, 22); REG_FLD_MOD 129 drivers/video/fbdev/omap2/omapfb/dss/hdmi_phy.c REG_FLD_MOD(phy->base, HDMI_TXPHY_PAD_CFG_CTRL, pol_val, 30, 27); REG_FLD_MOD 148 drivers/video/fbdev/omap2/omapfb/dss/hdmi_phy.c REG_FLD_MOD(phy->base, HDMI_TXPHY_BIST_CONTROL, 1, 11, 11); REG_FLD_MOD 165 drivers/video/fbdev/omap2/omapfb/dss/hdmi_phy.c REG_FLD_MOD(phy->base, HDMI_TXPHY_TX_CTRL, freqout, 31, 30); REG_FLD_MOD 172 drivers/video/fbdev/omap2/omapfb/dss/hdmi_phy.c REG_FLD_MOD(phy->base, HDMI_TXPHY_POWER_CTRL, 0xB, 3, 0); REG_FLD_MOD 75 drivers/video/fbdev/omap2/omapfb/dss/hdmi_wp.c REG_FLD_MOD(wp->base, HDMI_WP_PWR_CTRL, val, 7, 6); REG_FLD_MOD 91 drivers/video/fbdev/omap2/omapfb/dss/hdmi_wp.c REG_FLD_MOD(wp->base, HDMI_WP_PWR_CTRL, val, 3, 2); REG_FLD_MOD 105 drivers/video/fbdev/omap2/omapfb/dss/hdmi_wp.c REG_FLD_MOD(wp->base, HDMI_WP_VIDEO_CFG, true, 31, 31); REG_FLD_MOD 116 drivers/video/fbdev/omap2/omapfb/dss/hdmi_wp.c REG_FLD_MOD(wp->base, HDMI_WP_VIDEO_CFG, false, 31, 31); REG_FLD_MOD 136 drivers/video/fbdev/omap2/omapfb/dss/hdmi_wp.c REG_FLD_MOD(wp->base, HDMI_WP_VIDEO_CFG, video_fmt->packing_mode, REG_FLD_MOD 246 drivers/video/fbdev/omap2/omapfb/dss/hdmi_wp.c REG_FLD_MOD(wp->base, HDMI_WP_AUDIO_CTRL, enable, 31, 31); REG_FLD_MOD 253 drivers/video/fbdev/omap2/omapfb/dss/hdmi_wp.c REG_FLD_MOD(wp->base, HDMI_WP_AUDIO_CTRL, enable, 30, 30);