REG_FIELD_SHIFT  1114 drivers/gpu/drm/amd/amdgpu/amdgpu.h 	 (REG_FIELD_MASK(reg, field) & ((field_val) << REG_FIELD_SHIFT(reg, field))))
REG_FIELD_SHIFT  1117 drivers/gpu/drm/amd/amdgpu/amdgpu.h 	(((value) & REG_FIELD_MASK(reg, field)) >> REG_FIELD_SHIFT(reg, field))
REG_FIELD_SHIFT  1120 drivers/gpu/drm/amd/amdgpu/amdgpu.h 	WREG32(mm##reg, (RREG32(mm##reg) & ~REG_FIELD_MASK(reg, field)) | (val) << REG_FIELD_SHIFT(reg, field))
REG_FIELD_SHIFT  1123 drivers/gpu/drm/amd/amdgpu/amdgpu.h 	WREG32(mm##reg + offset, (RREG32(mm##reg + offset) & ~REG_FIELD_MASK(reg, field)) | (val) << REG_FIELD_SHIFT(reg, field))
REG_FIELD_SHIFT    33 drivers/gpu/drm/amd/amdgpu/soc15_common.h 	& ~REG_FIELD_MASK(reg, field)) | (val) << REG_FIELD_SHIFT(reg, field))
REG_FIELD_SHIFT   125 drivers/gpu/drm/amd/amdgpu/soc15_common.h     & ~REG_FIELD_MASK(reg, field)) | (val) << REG_FIELD_SHIFT(reg, field))
REG_FIELD_SHIFT   661 drivers/gpu/drm/amd/amdgpu/uvd_v5_0.c 		(1 << REG_FIELD_SHIFT(UVD_CGC_CTRL, CLK_GATE_DLY_TIMER)) |
REG_FIELD_SHIFT   662 drivers/gpu/drm/amd/amdgpu/uvd_v5_0.c 		(4 << REG_FIELD_SHIFT(UVD_CGC_CTRL, CLK_OFF_DELAY));
REG_FIELD_SHIFT  1316 drivers/gpu/drm/amd/amdgpu/uvd_v6_0.c 		(1 << REG_FIELD_SHIFT(UVD_CGC_CTRL, CLK_GATE_DLY_TIMER)) |
REG_FIELD_SHIFT  1317 drivers/gpu/drm/amd/amdgpu/uvd_v6_0.c 		(4 << REG_FIELD_SHIFT(UVD_CGC_CTRL, CLK_OFF_DELAY));
REG_FIELD_SHIFT  1599 drivers/gpu/drm/amd/amdgpu/uvd_v7_0.c 		(1 << REG_FIELD_SHIFT(UVD_CGC_CTRL, CLK_GATE_DLY_TIMER)) |
REG_FIELD_SHIFT  1600 drivers/gpu/drm/amd/amdgpu/uvd_v7_0.c 		(4 << REG_FIELD_SHIFT(UVD_CGC_CTRL, CLK_OFF_DELAY));
REG_FIELD_SHIFT  1053 drivers/misc/habanalabs/habanalabs.h 			(val) << REG_FIELD_SHIFT(reg, field))