REG_FIELD_PREP 6568 drivers/gpu/drm/i915/display/intel_dp.c pp_on = REG_FIELD_PREP(PANEL_POWER_UP_DELAY_MASK, seq->t1_t3) | REG_FIELD_PREP 6569 drivers/gpu/drm/i915/display/intel_dp.c REG_FIELD_PREP(PANEL_LIGHT_ON_DELAY_MASK, seq->t8); REG_FIELD_PREP 6570 drivers/gpu/drm/i915/display/intel_dp.c pp_off = REG_FIELD_PREP(PANEL_LIGHT_OFF_DELAY_MASK, seq->t9) | REG_FIELD_PREP 6571 drivers/gpu/drm/i915/display/intel_dp.c REG_FIELD_PREP(PANEL_POWER_DOWN_DELAY_MASK, seq->t10); REG_FIELD_PREP 6604 drivers/gpu/drm/i915/display/intel_dp.c REG_FIELD_PREP(PP_REFERENCE_DIVIDER_MASK, (100 * div) / 2 - 1) | REG_FIELD_PREP 6605 drivers/gpu/drm/i915/display/intel_dp.c REG_FIELD_PREP(PANEL_POWER_CYCLE_DELAY_MASK, DIV_ROUND_UP(seq->t11_t12, 1000))); REG_FIELD_PREP 6611 drivers/gpu/drm/i915/display/intel_dp.c pp_ctl |= REG_FIELD_PREP(BXT_POWER_CYCLE_DELAY_MASK, DIV_ROUND_UP(seq->t11_t12, 1000)); REG_FIELD_PREP 213 drivers/gpu/drm/i915/display/intel_lvds.c REG_FIELD_PREP(PANEL_PORT_SELECT_MASK, pps->port) | REG_FIELD_PREP 214 drivers/gpu/drm/i915/display/intel_lvds.c REG_FIELD_PREP(PANEL_POWER_UP_DELAY_MASK, pps->t1_t2) | REG_FIELD_PREP 215 drivers/gpu/drm/i915/display/intel_lvds.c REG_FIELD_PREP(PANEL_LIGHT_ON_DELAY_MASK, pps->t5)); REG_FIELD_PREP 218 drivers/gpu/drm/i915/display/intel_lvds.c REG_FIELD_PREP(PANEL_POWER_DOWN_DELAY_MASK, pps->t3) | REG_FIELD_PREP 219 drivers/gpu/drm/i915/display/intel_lvds.c REG_FIELD_PREP(PANEL_LIGHT_OFF_DELAY_MASK, pps->tx)); REG_FIELD_PREP 222 drivers/gpu/drm/i915/display/intel_lvds.c REG_FIELD_PREP(PP_REFERENCE_DIVIDER_MASK, pps->divider) | REG_FIELD_PREP 223 drivers/gpu/drm/i915/display/intel_lvds.c REG_FIELD_PREP(PANEL_POWER_CYCLE_DELAY_MASK, REG_FIELD_PREP 478 drivers/gpu/drm/i915/i915_irq.c u32 events = REG_FIELD_PREP(ENGINE1_MASK, GUC_INTR_GUC2HOST); REG_FIELD_PREP 4730 drivers/gpu/drm/i915/i915_reg.h #define PP_SEQUENCE_NONE REG_FIELD_PREP(PP_SEQUENCE_MASK, 0) REG_FIELD_PREP 4731 drivers/gpu/drm/i915/i915_reg.h #define PP_SEQUENCE_POWER_UP REG_FIELD_PREP(PP_SEQUENCE_MASK, 1) REG_FIELD_PREP 4732 drivers/gpu/drm/i915/i915_reg.h #define PP_SEQUENCE_POWER_DOWN REG_FIELD_PREP(PP_SEQUENCE_MASK, 2) REG_FIELD_PREP 4735 drivers/gpu/drm/i915/i915_reg.h #define PP_SEQUENCE_STATE_OFF_IDLE REG_FIELD_PREP(PP_SEQUENCE_STATE_MASK, 0x0) REG_FIELD_PREP 4736 drivers/gpu/drm/i915/i915_reg.h #define PP_SEQUENCE_STATE_OFF_S0_1 REG_FIELD_PREP(PP_SEQUENCE_STATE_MASK, 0x1) REG_FIELD_PREP 4737 drivers/gpu/drm/i915/i915_reg.h #define PP_SEQUENCE_STATE_OFF_S0_2 REG_FIELD_PREP(PP_SEQUENCE_STATE_MASK, 0x2) REG_FIELD_PREP 4738 drivers/gpu/drm/i915/i915_reg.h #define PP_SEQUENCE_STATE_OFF_S0_3 REG_FIELD_PREP(PP_SEQUENCE_STATE_MASK, 0x3) REG_FIELD_PREP 4739 drivers/gpu/drm/i915/i915_reg.h #define PP_SEQUENCE_STATE_ON_IDLE REG_FIELD_PREP(PP_SEQUENCE_STATE_MASK, 0x8) REG_FIELD_PREP 4740 drivers/gpu/drm/i915/i915_reg.h #define PP_SEQUENCE_STATE_ON_S1_1 REG_FIELD_PREP(PP_SEQUENCE_STATE_MASK, 0x9) REG_FIELD_PREP 4741 drivers/gpu/drm/i915/i915_reg.h #define PP_SEQUENCE_STATE_ON_S1_2 REG_FIELD_PREP(PP_SEQUENCE_STATE_MASK, 0xa) REG_FIELD_PREP 4742 drivers/gpu/drm/i915/i915_reg.h #define PP_SEQUENCE_STATE_ON_S1_3 REG_FIELD_PREP(PP_SEQUENCE_STATE_MASK, 0xb) REG_FIELD_PREP 4743 drivers/gpu/drm/i915/i915_reg.h #define PP_SEQUENCE_STATE_RESET REG_FIELD_PREP(PP_SEQUENCE_STATE_MASK, 0xf) REG_FIELD_PREP 4748 drivers/gpu/drm/i915/i915_reg.h #define PANEL_UNLOCK_REGS REG_FIELD_PREP(PANEL_UNLOCK_MASK, 0xabcd) REG_FIELD_PREP 4758 drivers/gpu/drm/i915/i915_reg.h #define PANEL_PORT_SELECT_LVDS REG_FIELD_PREP(PANEL_PORT_SELECT_MASK, 0) REG_FIELD_PREP 4759 drivers/gpu/drm/i915/i915_reg.h #define PANEL_PORT_SELECT_DPA REG_FIELD_PREP(PANEL_PORT_SELECT_MASK, 1) REG_FIELD_PREP 4760 drivers/gpu/drm/i915/i915_reg.h #define PANEL_PORT_SELECT_DPC REG_FIELD_PREP(PANEL_PORT_SELECT_MASK, 2) REG_FIELD_PREP 4761 drivers/gpu/drm/i915/i915_reg.h #define PANEL_PORT_SELECT_DPD REG_FIELD_PREP(PANEL_PORT_SELECT_MASK, 3) REG_FIELD_PREP 4762 drivers/gpu/drm/i915/i915_reg.h #define PANEL_PORT_SELECT_VLV(port) REG_FIELD_PREP(PANEL_PORT_SELECT_MASK, port)