REG_FIELD_MASK 1113 drivers/gpu/drm/amd/amdgpu/amdgpu.h (((orig_val) & ~REG_FIELD_MASK(reg, field)) | \ REG_FIELD_MASK 1114 drivers/gpu/drm/amd/amdgpu/amdgpu.h (REG_FIELD_MASK(reg, field) & ((field_val) << REG_FIELD_SHIFT(reg, field)))) REG_FIELD_MASK 1117 drivers/gpu/drm/amd/amdgpu/amdgpu.h (((value) & REG_FIELD_MASK(reg, field)) >> REG_FIELD_SHIFT(reg, field)) REG_FIELD_MASK 1120 drivers/gpu/drm/amd/amdgpu/amdgpu.h WREG32(mm##reg, (RREG32(mm##reg) & ~REG_FIELD_MASK(reg, field)) | (val) << REG_FIELD_SHIFT(reg, field)) REG_FIELD_MASK 1123 drivers/gpu/drm/amd/amdgpu/amdgpu.h WREG32(mm##reg + offset, (RREG32(mm##reg + offset) & ~REG_FIELD_MASK(reg, field)) | (val) << REG_FIELD_SHIFT(reg, field)) REG_FIELD_MASK 5763 drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c REG_FIELD_MASK(CPC_EDC_SCRATCH_CNT, SEC_COUNT), REG_FIELD_MASK 5764 drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c REG_FIELD_MASK(CPC_EDC_SCRATCH_CNT, DED_COUNT) }, REG_FIELD_MASK 5766 drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c REG_FIELD_MASK(CPC_EDC_UCODE_CNT, SEC_COUNT), REG_FIELD_MASK 5767 drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c REG_FIELD_MASK(CPC_EDC_UCODE_CNT, DED_COUNT) }, REG_FIELD_MASK 5769 drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c REG_FIELD_MASK(CPF_EDC_ROQ_CNT, COUNT_ME1), 0 }, REG_FIELD_MASK 5771 drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c REG_FIELD_MASK(CPF_EDC_ROQ_CNT, COUNT_ME2), 0 }, REG_FIELD_MASK 5773 drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c REG_FIELD_MASK(CPF_EDC_TAG_CNT, SEC_COUNT), REG_FIELD_MASK 5774 drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c REG_FIELD_MASK(CPF_EDC_TAG_CNT, DED_COUNT) }, REG_FIELD_MASK 5776 drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c REG_FIELD_MASK(CPG_EDC_DMA_CNT, ROQ_COUNT), 0 }, REG_FIELD_MASK 5778 drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c REG_FIELD_MASK(CPG_EDC_DMA_CNT, TAG_SEC_COUNT), REG_FIELD_MASK 5779 drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c REG_FIELD_MASK(CPG_EDC_DMA_CNT, TAG_DED_COUNT) }, REG_FIELD_MASK 5781 drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c REG_FIELD_MASK(CPG_EDC_TAG_CNT, SEC_COUNT), REG_FIELD_MASK 5782 drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c REG_FIELD_MASK(CPG_EDC_TAG_CNT, DED_COUNT) }, REG_FIELD_MASK 5784 drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c REG_FIELD_MASK(DC_EDC_CSINVOC_CNT, COUNT_ME1), 0 }, REG_FIELD_MASK 5786 drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c REG_FIELD_MASK(DC_EDC_RESTORE_CNT, COUNT_ME1), 0 }, REG_FIELD_MASK 5788 drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c REG_FIELD_MASK(DC_EDC_STATE_CNT, COUNT_ME1), 0 }, REG_FIELD_MASK 5790 drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c REG_FIELD_MASK(GDS_EDC_CNT, GDS_MEM_SEC), REG_FIELD_MASK 5791 drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c REG_FIELD_MASK(GDS_EDC_CNT, GDS_MEM_DED) }, REG_FIELD_MASK 5793 drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c REG_FIELD_MASK(GDS_EDC_CNT, GDS_INPUT_QUEUE_SED), 0 }, REG_FIELD_MASK 5795 drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c 0, 1, REG_FIELD_MASK(GDS_EDC_OA_PHY_CNT, ME0_CS_PIPE_MEM_SEC), REG_FIELD_MASK 5796 drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c REG_FIELD_MASK(GDS_EDC_OA_PHY_CNT, ME0_CS_PIPE_MEM_DED) }, REG_FIELD_MASK 5799 drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c REG_FIELD_MASK(GDS_EDC_OA_PHY_CNT, PHY_CMD_RAM_MEM_SEC), REG_FIELD_MASK 5800 drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c REG_FIELD_MASK(GDS_EDC_OA_PHY_CNT, PHY_CMD_RAM_MEM_DED) }, REG_FIELD_MASK 5803 drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c REG_FIELD_MASK(GDS_EDC_OA_PHY_CNT, PHY_DATA_RAM_MEM_SED), 0 }, REG_FIELD_MASK 5806 drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c REG_FIELD_MASK(GDS_EDC_OA_PIPE_CNT, ME1_PIPE0_PIPE_MEM_SEC), REG_FIELD_MASK 5807 drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c REG_FIELD_MASK(GDS_EDC_OA_PIPE_CNT, ME1_PIPE0_PIPE_MEM_DED) }, REG_FIELD_MASK 5810 drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c REG_FIELD_MASK(GDS_EDC_OA_PIPE_CNT, ME1_PIPE1_PIPE_MEM_SEC), REG_FIELD_MASK 5811 drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c REG_FIELD_MASK(GDS_EDC_OA_PIPE_CNT, ME1_PIPE1_PIPE_MEM_DED) }, REG_FIELD_MASK 5814 drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c REG_FIELD_MASK(GDS_EDC_OA_PIPE_CNT, ME1_PIPE2_PIPE_MEM_SEC), REG_FIELD_MASK 5815 drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c REG_FIELD_MASK(GDS_EDC_OA_PIPE_CNT, ME1_PIPE2_PIPE_MEM_DED) }, REG_FIELD_MASK 5818 drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c REG_FIELD_MASK(GDS_EDC_OA_PIPE_CNT, ME1_PIPE3_PIPE_MEM_SEC), REG_FIELD_MASK 5819 drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c REG_FIELD_MASK(GDS_EDC_OA_PIPE_CNT, ME1_PIPE3_PIPE_MEM_DED) }, REG_FIELD_MASK 5821 drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c REG_FIELD_MASK(SPI_EDC_CNT, SPI_SR_MEM_SED_COUNT), 0 }, REG_FIELD_MASK 5823 drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c REG_FIELD_MASK(TA_EDC_CNT, TA_FS_DFIFO_SEC_COUNT), REG_FIELD_MASK 5824 drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c REG_FIELD_MASK(TA_EDC_CNT, TA_FS_DFIFO_DED_COUNT) }, REG_FIELD_MASK 5826 drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c REG_FIELD_MASK(TA_EDC_CNT, TA_FS_AFIFO_SED_COUNT), 0 }, REG_FIELD_MASK 5828 drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c REG_FIELD_MASK(TA_EDC_CNT, TA_FL_LFIFO_SED_COUNT), 0 }, REG_FIELD_MASK 5830 drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c REG_FIELD_MASK(TA_EDC_CNT, TA_FX_LFIFO_SED_COUNT), 0 }, REG_FIELD_MASK 5832 drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c REG_FIELD_MASK(TA_EDC_CNT, TA_FS_CFIFO_SED_COUNT), 0 }, REG_FIELD_MASK 5834 drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c REG_FIELD_MASK(TCA_EDC_CNT, HOLE_FIFO_SED_COUNT), 0 }, REG_FIELD_MASK 5836 drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c REG_FIELD_MASK(TCA_EDC_CNT, REQ_FIFO_SED_COUNT), 0 }, REG_FIELD_MASK 5838 drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c REG_FIELD_MASK(TCC_EDC_CNT, CACHE_DATA_SEC_COUNT), REG_FIELD_MASK 5839 drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c REG_FIELD_MASK(TCC_EDC_CNT, CACHE_DATA_DED_COUNT) }, REG_FIELD_MASK 5841 drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c REG_FIELD_MASK(TCC_EDC_CNT, CACHE_DIRTY_SEC_COUNT), REG_FIELD_MASK 5842 drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c REG_FIELD_MASK(TCC_EDC_CNT, CACHE_DIRTY_DED_COUNT) }, REG_FIELD_MASK 5844 drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c REG_FIELD_MASK(TCC_EDC_CNT, HIGH_RATE_TAG_SEC_COUNT), REG_FIELD_MASK 5845 drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c REG_FIELD_MASK(TCC_EDC_CNT, HIGH_RATE_TAG_DED_COUNT) }, REG_FIELD_MASK 5847 drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c REG_FIELD_MASK(TCC_EDC_CNT, LOW_RATE_TAG_SEC_COUNT), REG_FIELD_MASK 5848 drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c REG_FIELD_MASK(TCC_EDC_CNT, LOW_RATE_TAG_DED_COUNT) }, REG_FIELD_MASK 5850 drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c REG_FIELD_MASK(TCC_EDC_CNT, SRC_FIFO_SEC_COUNT), REG_FIELD_MASK 5851 drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c REG_FIELD_MASK(TCC_EDC_CNT, SRC_FIFO_DED_COUNT) }, REG_FIELD_MASK 5853 drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c REG_FIELD_MASK(TCC_EDC_CNT, IN_USE_DEC_SED_COUNT), 0 }, REG_FIELD_MASK 5855 drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c REG_FIELD_MASK(TCC_EDC_CNT, IN_USE_TRANSFER_SED_COUNT), 0 }, REG_FIELD_MASK 5857 drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c REG_FIELD_MASK(TCC_EDC_CNT, LATENCY_FIFO_SED_COUNT), 0 }, REG_FIELD_MASK 5859 drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c REG_FIELD_MASK(TCC_EDC_CNT, RETURN_DATA_SED_COUNT), 0 }, REG_FIELD_MASK 5861 drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c REG_FIELD_MASK(TCC_EDC_CNT, RETURN_CONTROL_SED_COUNT), 0 }, REG_FIELD_MASK 5863 drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c REG_FIELD_MASK(TCC_EDC_CNT, UC_ATOMIC_FIFO_SED_COUNT), 0 }, REG_FIELD_MASK 5865 drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c REG_FIELD_MASK(TCC_EDC_CNT2, WRITE_RETURN_SED_COUNT), 0 }, REG_FIELD_MASK 5867 drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c REG_FIELD_MASK(TCC_EDC_CNT2, WRITE_CACHE_READ_SED_COUNT), 0 }, REG_FIELD_MASK 5869 drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c 16, REG_FIELD_MASK(TCC_EDC_CNT2, SRC_FIFO_NEXT_RAM_SED_COUNT), 0 }, REG_FIELD_MASK 5871 drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c 0, 16, REG_FIELD_MASK(TCC_EDC_CNT2, LATENCY_FIFO_NEXT_RAM_SED_COUNT), REG_FIELD_MASK 5874 drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c 16, REG_FIELD_MASK(TCC_EDC_CNT2, CACHE_TAG_PROBE_FIFO_SED_COUNT), 0 }, REG_FIELD_MASK 5876 drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c 0, 16, REG_FIELD_MASK(TCC_EDC_CNT2, WRRET_TAG_WRITE_RETURN_SED_COUNT), REG_FIELD_MASK 5879 drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c 16, REG_FIELD_MASK(TCC_EDC_CNT2, ATOMIC_RETURN_BUFFER_SED_COUNT), 0 }, REG_FIELD_MASK 5881 drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c REG_FIELD_MASK(TCI_EDC_CNT, WRITE_RAM_SED_COUNT), 0 }, REG_FIELD_MASK 5883 drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c REG_FIELD_MASK(TCP_EDC_CNT_NEW, CACHE_RAM_SEC_COUNT), REG_FIELD_MASK 5884 drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c REG_FIELD_MASK(TCP_EDC_CNT_NEW, CACHE_RAM_DED_COUNT) }, REG_FIELD_MASK 5886 drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c REG_FIELD_MASK(TCP_EDC_CNT_NEW, LFIFO_RAM_SEC_COUNT), REG_FIELD_MASK 5887 drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c REG_FIELD_MASK(TCP_EDC_CNT_NEW, LFIFO_RAM_DED_COUNT) }, REG_FIELD_MASK 5889 drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c REG_FIELD_MASK(TCP_EDC_CNT_NEW, CMD_FIFO_SED_COUNT), 0 }, REG_FIELD_MASK 5891 drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c REG_FIELD_MASK(TCP_EDC_CNT_NEW, VM_FIFO_SEC_COUNT), 0 }, REG_FIELD_MASK 5893 drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c REG_FIELD_MASK(TCP_EDC_CNT_NEW, DB_RAM_SED_COUNT), 0 }, REG_FIELD_MASK 5895 drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c REG_FIELD_MASK(TCP_EDC_CNT_NEW, UTCL1_LFIFO0_SEC_COUNT), REG_FIELD_MASK 5896 drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c REG_FIELD_MASK(TCP_EDC_CNT_NEW, UTCL1_LFIFO0_DED_COUNT) }, REG_FIELD_MASK 5898 drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c REG_FIELD_MASK(TCP_EDC_CNT_NEW, UTCL1_LFIFO1_SEC_COUNT), REG_FIELD_MASK 5899 drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c REG_FIELD_MASK(TCP_EDC_CNT_NEW, UTCL1_LFIFO1_DED_COUNT) }, REG_FIELD_MASK 5901 drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c REG_FIELD_MASK(TD_EDC_CNT, SS_FIFO_LO_SEC_COUNT), REG_FIELD_MASK 5902 drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c REG_FIELD_MASK(TD_EDC_CNT, SS_FIFO_LO_DED_COUNT) }, REG_FIELD_MASK 5904 drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c REG_FIELD_MASK(TD_EDC_CNT, SS_FIFO_HI_SEC_COUNT), REG_FIELD_MASK 5905 drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c REG_FIELD_MASK(TD_EDC_CNT, SS_FIFO_HI_DED_COUNT) }, REG_FIELD_MASK 5907 drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c REG_FIELD_MASK(TD_EDC_CNT, CS_FIFO_SED_COUNT), 0 }, REG_FIELD_MASK 5909 drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c REG_FIELD_MASK(SQ_EDC_CNT, LDS_D_SEC_COUNT), REG_FIELD_MASK 5910 drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c REG_FIELD_MASK(SQ_EDC_CNT, LDS_D_DED_COUNT) }, REG_FIELD_MASK 5912 drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c REG_FIELD_MASK(SQ_EDC_CNT, LDS_I_SEC_COUNT), REG_FIELD_MASK 5913 drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c REG_FIELD_MASK(SQ_EDC_CNT, LDS_I_DED_COUNT) }, REG_FIELD_MASK 5915 drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c REG_FIELD_MASK(SQ_EDC_CNT, SGPR_SEC_COUNT), REG_FIELD_MASK 5916 drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c REG_FIELD_MASK(SQ_EDC_CNT, SGPR_DED_COUNT) }, REG_FIELD_MASK 5918 drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c REG_FIELD_MASK(SQ_EDC_CNT, VGPR0_SEC_COUNT), REG_FIELD_MASK 5919 drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c REG_FIELD_MASK(SQ_EDC_CNT, VGPR0_DED_COUNT) }, REG_FIELD_MASK 5921 drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c REG_FIELD_MASK(SQ_EDC_CNT, VGPR1_SEC_COUNT), REG_FIELD_MASK 5922 drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c REG_FIELD_MASK(SQ_EDC_CNT, VGPR1_DED_COUNT) }, REG_FIELD_MASK 5924 drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c REG_FIELD_MASK(SQ_EDC_CNT, VGPR2_SEC_COUNT), REG_FIELD_MASK 5925 drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c REG_FIELD_MASK(SQ_EDC_CNT, VGPR2_DED_COUNT) }, REG_FIELD_MASK 5927 drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c REG_FIELD_MASK(SQ_EDC_CNT, VGPR3_SEC_COUNT), REG_FIELD_MASK 5928 drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c REG_FIELD_MASK(SQ_EDC_CNT, VGPR3_DED_COUNT) }, REG_FIELD_MASK 5930 drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c 1, 6, REG_FIELD_MASK(SQC_EDC_CNT, DATA_CU0_WRITE_DATA_BUF_SEC_COUNT), REG_FIELD_MASK 5931 drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c REG_FIELD_MASK(SQC_EDC_CNT, DATA_CU0_WRITE_DATA_BUF_DED_COUNT) }, REG_FIELD_MASK 5933 drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c 6, REG_FIELD_MASK(SQC_EDC_CNT, DATA_CU0_UTCL1_LFIFO_SEC_COUNT), REG_FIELD_MASK 5934 drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c REG_FIELD_MASK(SQC_EDC_CNT, DATA_CU0_UTCL1_LFIFO_DED_COUNT) }, REG_FIELD_MASK 5936 drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c 1, 6, REG_FIELD_MASK(SQC_EDC_CNT, DATA_CU1_WRITE_DATA_BUF_SEC_COUNT), REG_FIELD_MASK 5937 drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c REG_FIELD_MASK(SQC_EDC_CNT, DATA_CU1_WRITE_DATA_BUF_DED_COUNT) }, REG_FIELD_MASK 5939 drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c 6, REG_FIELD_MASK(SQC_EDC_CNT, DATA_CU1_UTCL1_LFIFO_SEC_COUNT), REG_FIELD_MASK 5940 drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c REG_FIELD_MASK(SQC_EDC_CNT, DATA_CU1_UTCL1_LFIFO_DED_COUNT) }, REG_FIELD_MASK 5942 drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c 1, 6, REG_FIELD_MASK(SQC_EDC_CNT, DATA_CU2_WRITE_DATA_BUF_SEC_COUNT), REG_FIELD_MASK 5943 drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c REG_FIELD_MASK(SQC_EDC_CNT, DATA_CU2_WRITE_DATA_BUF_DED_COUNT) }, REG_FIELD_MASK 5945 drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c 6, REG_FIELD_MASK(SQC_EDC_CNT, DATA_CU2_UTCL1_LFIFO_SEC_COUNT), REG_FIELD_MASK 5946 drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c REG_FIELD_MASK(SQC_EDC_CNT, DATA_CU2_UTCL1_LFIFO_DED_COUNT) }, REG_FIELD_MASK 5948 drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c 6, REG_FIELD_MASK(SQC_EDC_CNT2, INST_BANKA_TAG_RAM_SEC_COUNT), REG_FIELD_MASK 5949 drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c REG_FIELD_MASK(SQC_EDC_CNT2, INST_BANKA_TAG_RAM_DED_COUNT) }, REG_FIELD_MASK 5951 drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c 6, REG_FIELD_MASK(SQC_EDC_CNT2, INST_BANKA_BANK_RAM_SEC_COUNT), REG_FIELD_MASK 5952 drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c REG_FIELD_MASK(SQC_EDC_CNT2, INST_BANKA_BANK_RAM_DED_COUNT) }, REG_FIELD_MASK 5954 drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c 6, REG_FIELD_MASK(SQC_EDC_CNT2, DATA_BANKA_TAG_RAM_SEC_COUNT), REG_FIELD_MASK 5955 drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c REG_FIELD_MASK(SQC_EDC_CNT2, DATA_BANKA_TAG_RAM_DED_COUNT) }, REG_FIELD_MASK 5957 drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c 6, REG_FIELD_MASK(SQC_EDC_CNT2, DATA_BANKA_BANK_RAM_SEC_COUNT), REG_FIELD_MASK 5958 drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c REG_FIELD_MASK(SQC_EDC_CNT2, DATA_BANKA_BANK_RAM_DED_COUNT) }, REG_FIELD_MASK 5961 drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c REG_FIELD_MASK(SQC_EDC_CNT2, INST_BANKA_UTCL1_MISS_FIFO_SED_COUNT), REG_FIELD_MASK 5964 drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c 6, REG_FIELD_MASK(SQC_EDC_CNT2, INST_BANKA_MISS_FIFO_SED_COUNT), 0 }, REG_FIELD_MASK 5966 drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c 6, REG_FIELD_MASK(SQC_EDC_CNT2, DATA_BANKA_HIT_FIFO_SED_COUNT), 0 }, REG_FIELD_MASK 5968 drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c 6, REG_FIELD_MASK(SQC_EDC_CNT2, DATA_BANKA_MISS_FIFO_SED_COUNT), 0 }, REG_FIELD_MASK 5971 drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c REG_FIELD_MASK(SQC_EDC_CNT2, DATA_BANKA_DIRTY_BIT_RAM_SED_COUNT), 0 }, REG_FIELD_MASK 5973 drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c REG_FIELD_MASK(SQC_EDC_CNT2, INST_UTCL1_LFIFO_SEC_COUNT), REG_FIELD_MASK 5974 drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c REG_FIELD_MASK(SQC_EDC_CNT2, INST_UTCL1_LFIFO_DED_COUNT) }, REG_FIELD_MASK 5976 drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c 6, REG_FIELD_MASK(SQC_EDC_CNT3, INST_BANKB_TAG_RAM_SEC_COUNT), REG_FIELD_MASK 5977 drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c REG_FIELD_MASK(SQC_EDC_CNT3, INST_BANKB_TAG_RAM_DED_COUNT) }, REG_FIELD_MASK 5979 drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c 6, REG_FIELD_MASK(SQC_EDC_CNT3, INST_BANKB_BANK_RAM_SEC_COUNT), REG_FIELD_MASK 5980 drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c REG_FIELD_MASK(SQC_EDC_CNT3, INST_BANKB_BANK_RAM_DED_COUNT) }, REG_FIELD_MASK 5982 drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c 6, REG_FIELD_MASK(SQC_EDC_CNT3, DATA_BANKB_TAG_RAM_SEC_COUNT), REG_FIELD_MASK 5983 drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c REG_FIELD_MASK(SQC_EDC_CNT3, DATA_BANKB_TAG_RAM_DED_COUNT) }, REG_FIELD_MASK 5985 drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c 6, REG_FIELD_MASK(SQC_EDC_CNT3, DATA_BANKB_BANK_RAM_SEC_COUNT), REG_FIELD_MASK 5986 drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c REG_FIELD_MASK(SQC_EDC_CNT3, DATA_BANKB_BANK_RAM_DED_COUNT) }, REG_FIELD_MASK 5989 drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c REG_FIELD_MASK(SQC_EDC_CNT3, INST_BANKB_UTCL1_MISS_FIFO_SED_COUNT), REG_FIELD_MASK 5992 drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c 6, REG_FIELD_MASK(SQC_EDC_CNT3, INST_BANKB_MISS_FIFO_SED_COUNT), 0 }, REG_FIELD_MASK 5994 drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c 6, REG_FIELD_MASK(SQC_EDC_CNT3, DATA_BANKB_HIT_FIFO_SED_COUNT), 0 }, REG_FIELD_MASK 5996 drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c 6, REG_FIELD_MASK(SQC_EDC_CNT3, DATA_BANKB_MISS_FIFO_SED_COUNT), 0 }, REG_FIELD_MASK 5999 drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c REG_FIELD_MASK(SQC_EDC_CNT3, DATA_BANKB_DIRTY_BIT_RAM_SED_COUNT), 0 }, REG_FIELD_MASK 6001 drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c REG_FIELD_MASK(GCEA_EDC_CNT, DRAMRD_CMDMEM_SEC_COUNT), REG_FIELD_MASK 6002 drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c REG_FIELD_MASK(GCEA_EDC_CNT, DRAMRD_CMDMEM_DED_COUNT) }, REG_FIELD_MASK 6004 drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c REG_FIELD_MASK(GCEA_EDC_CNT, DRAMWR_CMDMEM_SEC_COUNT), REG_FIELD_MASK 6005 drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c REG_FIELD_MASK(GCEA_EDC_CNT, DRAMWR_CMDMEM_DED_COUNT) }, REG_FIELD_MASK 6007 drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c REG_FIELD_MASK(GCEA_EDC_CNT, DRAMWR_DATAMEM_SEC_COUNT), REG_FIELD_MASK 6008 drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c REG_FIELD_MASK(GCEA_EDC_CNT, DRAMWR_DATAMEM_DED_COUNT) }, REG_FIELD_MASK 6010 drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c REG_FIELD_MASK(GCEA_EDC_CNT, RRET_TAGMEM_SEC_COUNT), REG_FIELD_MASK 6011 drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c REG_FIELD_MASK(GCEA_EDC_CNT, RRET_TAGMEM_DED_COUNT) }, REG_FIELD_MASK 6013 drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c REG_FIELD_MASK(GCEA_EDC_CNT, WRET_TAGMEM_SEC_COUNT), REG_FIELD_MASK 6014 drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c REG_FIELD_MASK(GCEA_EDC_CNT, WRET_TAGMEM_DED_COUNT) }, REG_FIELD_MASK 6016 drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c REG_FIELD_MASK(GCEA_EDC_CNT, DRAMRD_PAGEMEM_SED_COUNT), 0 }, REG_FIELD_MASK 6018 drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c REG_FIELD_MASK(GCEA_EDC_CNT, DRAMWR_PAGEMEM_SED_COUNT), 0 }, REG_FIELD_MASK 6020 drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c REG_FIELD_MASK(GCEA_EDC_CNT, IORD_CMDMEM_SED_COUNT), 0 }, REG_FIELD_MASK 6022 drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c REG_FIELD_MASK(GCEA_EDC_CNT, IOWR_CMDMEM_SED_COUNT), 0 }, REG_FIELD_MASK 6024 drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c REG_FIELD_MASK(GCEA_EDC_CNT, IOWR_DATAMEM_SED_COUNT), 0 }, REG_FIELD_MASK 6026 drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c REG_FIELD_MASK(GCEA_EDC_CNT2, GMIRD_CMDMEM_SEC_COUNT), REG_FIELD_MASK 6027 drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c REG_FIELD_MASK(GCEA_EDC_CNT2, GMIRD_CMDMEM_DED_COUNT) }, REG_FIELD_MASK 6029 drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c REG_FIELD_MASK(GCEA_EDC_CNT2, GMIWR_CMDMEM_SEC_COUNT), REG_FIELD_MASK 6030 drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c REG_FIELD_MASK(GCEA_EDC_CNT2, GMIWR_CMDMEM_DED_COUNT) }, REG_FIELD_MASK 6032 drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c REG_FIELD_MASK(GCEA_EDC_CNT2, GMIWR_DATAMEM_SEC_COUNT), REG_FIELD_MASK 6033 drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c REG_FIELD_MASK(GCEA_EDC_CNT2, GMIWR_DATAMEM_DED_COUNT) }, REG_FIELD_MASK 6035 drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c REG_FIELD_MASK(GCEA_EDC_CNT2, GMIRD_PAGEMEM_SED_COUNT), 0 }, REG_FIELD_MASK 6037 drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c REG_FIELD_MASK(GCEA_EDC_CNT2, GMIWR_PAGEMEM_SED_COUNT), 0 }, REG_FIELD_MASK 6039 drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c REG_FIELD_MASK(GCEA_EDC_CNT2, MAM_D0MEM_SED_COUNT), 0 }, REG_FIELD_MASK 6041 drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c REG_FIELD_MASK(GCEA_EDC_CNT2, MAM_D1MEM_SED_COUNT), 0 }, REG_FIELD_MASK 6043 drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c REG_FIELD_MASK(GCEA_EDC_CNT2, MAM_D2MEM_SED_COUNT), 0 }, REG_FIELD_MASK 6045 drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c REG_FIELD_MASK(GCEA_EDC_CNT2, MAM_D3MEM_SED_COUNT), 0 }, REG_FIELD_MASK 321 drivers/gpu/drm/amd/amdgpu/mxgpu_vi.c u32 mask = REG_FIELD_MASK(MAILBOX_CONTROL, RCV_MSG_VALID); REG_FIELD_MASK 368 drivers/gpu/drm/amd/amdgpu/mxgpu_vi.c u32 mask = REG_FIELD_MASK(MAILBOX_CONTROL, RCV_MSG_VALID); REG_FIELD_MASK 390 drivers/gpu/drm/amd/amdgpu/mxgpu_vi.c u32 mask = REG_FIELD_MASK(MAILBOX_CONTROL, TRN_MSG_ACK); REG_FIELD_MASK 33 drivers/gpu/drm/amd/amdgpu/soc15_common.h & ~REG_FIELD_MASK(reg, field)) | (val) << REG_FIELD_SHIFT(reg, field)) REG_FIELD_MASK 125 drivers/gpu/drm/amd/amdgpu/soc15_common.h & ~REG_FIELD_MASK(reg, field)) | (val) << REG_FIELD_SHIFT(reg, field)) REG_FIELD_MASK 1052 drivers/misc/habanalabs/habanalabs.h WREG32(mm##reg, (RREG32(mm##reg) & ~REG_FIELD_MASK(reg, field)) | \