REG_FIELD_GET    6396 drivers/gpu/drm/i915/display/intel_dp.c 	seq->t1_t3 = REG_FIELD_GET(PANEL_POWER_UP_DELAY_MASK, pp_on);
REG_FIELD_GET    6397 drivers/gpu/drm/i915/display/intel_dp.c 	seq->t8 = REG_FIELD_GET(PANEL_LIGHT_ON_DELAY_MASK, pp_on);
REG_FIELD_GET    6398 drivers/gpu/drm/i915/display/intel_dp.c 	seq->t9 = REG_FIELD_GET(PANEL_LIGHT_OFF_DELAY_MASK, pp_off);
REG_FIELD_GET    6399 drivers/gpu/drm/i915/display/intel_dp.c 	seq->t10 = REG_FIELD_GET(PANEL_POWER_DOWN_DELAY_MASK, pp_off);
REG_FIELD_GET    6406 drivers/gpu/drm/i915/display/intel_dp.c 		seq->t11_t12 = REG_FIELD_GET(PANEL_POWER_CYCLE_DELAY_MASK, pp_div) * 1000;
REG_FIELD_GET    6408 drivers/gpu/drm/i915/display/intel_dp.c 		seq->t11_t12 = REG_FIELD_GET(BXT_POWER_CYCLE_DELAY_MASK, pp_ctl) * 1000;
REG_FIELD_GET     162 drivers/gpu/drm/i915/display/intel_lvds.c 	pps->port = REG_FIELD_GET(PANEL_PORT_SELECT_MASK, val);
REG_FIELD_GET     163 drivers/gpu/drm/i915/display/intel_lvds.c 	pps->t1_t2 = REG_FIELD_GET(PANEL_POWER_UP_DELAY_MASK, val);
REG_FIELD_GET     164 drivers/gpu/drm/i915/display/intel_lvds.c 	pps->t5 = REG_FIELD_GET(PANEL_LIGHT_ON_DELAY_MASK, val);
REG_FIELD_GET     167 drivers/gpu/drm/i915/display/intel_lvds.c 	pps->t3 = REG_FIELD_GET(PANEL_POWER_DOWN_DELAY_MASK, val);
REG_FIELD_GET     168 drivers/gpu/drm/i915/display/intel_lvds.c 	pps->tx = REG_FIELD_GET(PANEL_LIGHT_OFF_DELAY_MASK, val);
REG_FIELD_GET     171 drivers/gpu/drm/i915/display/intel_lvds.c 	pps->divider = REG_FIELD_GET(PP_REFERENCE_DIVIDER_MASK, val);
REG_FIELD_GET     172 drivers/gpu/drm/i915/display/intel_lvds.c 	val = REG_FIELD_GET(PANEL_POWER_CYCLE_DELAY_MASK, val);