REG_DSI_28nm_PHY_PLL_SDM_CFG1  184 drivers/gpu/drm/msm/dsi/pll/dsi_pll_28nm.c 	sdm_cfg1 = pll_read(base + REG_DSI_28nm_PHY_PLL_SDM_CFG1);
REG_DSI_28nm_PHY_PLL_SDM_CFG1  216 drivers/gpu/drm/msm/dsi/pll/dsi_pll_28nm.c 	pll_write(base + REG_DSI_28nm_PHY_PLL_SDM_CFG1, sdm_cfg1);
REG_DSI_28nm_PHY_PLL_SDM_CFG1  281 drivers/gpu/drm/msm/dsi/pll/dsi_pll_28nm.c 				pll_read(base + REG_DSI_28nm_PHY_PLL_SDM_CFG1),