REG_DSI_28nm_PHY_PLL_LKDET_CFG2 214 drivers/gpu/drm/msm/dsi/pll/dsi_pll_28nm.c pll_write(base + REG_DSI_28nm_PHY_PLL_LKDET_CFG2, 0x0d); REG_DSI_28nm_PHY_PLL_LKDET_CFG2 345 drivers/gpu/drm/msm/dsi/pll/dsi_pll_28nm.c pll_write_udelay(base + REG_DSI_28nm_PHY_PLL_LKDET_CFG2, REG_DSI_28nm_PHY_PLL_LKDET_CFG2 347 drivers/gpu/drm/msm/dsi/pll/dsi_pll_28nm.c pll_write(base + REG_DSI_28nm_PHY_PLL_LKDET_CFG2, 0x0d); REG_DSI_28nm_PHY_PLL_LKDET_CFG2 418 drivers/gpu/drm/msm/dsi/pll/dsi_pll_28nm.c pll_write_ndelay(base + REG_DSI_28nm_PHY_PLL_LKDET_CFG2, 0x04, 500); REG_DSI_28nm_PHY_PLL_LKDET_CFG2 419 drivers/gpu/drm/msm/dsi/pll/dsi_pll_28nm.c pll_write_udelay(base + REG_DSI_28nm_PHY_PLL_LKDET_CFG2, 0x05, 512);