REG_DSI_28nm_PHY_PLL_GLB_CFG  332 drivers/gpu/drm/msm/dsi/pll/dsi_pll_28nm.c 	pll_write_udelay(base + REG_DSI_28nm_PHY_PLL_GLB_CFG, val, 1);
REG_DSI_28nm_PHY_PLL_GLB_CFG  335 drivers/gpu/drm/msm/dsi/pll/dsi_pll_28nm.c 	pll_write_udelay(base + REG_DSI_28nm_PHY_PLL_GLB_CFG, val, 200);
REG_DSI_28nm_PHY_PLL_GLB_CFG  338 drivers/gpu/drm/msm/dsi/pll/dsi_pll_28nm.c 	pll_write_udelay(base + REG_DSI_28nm_PHY_PLL_GLB_CFG, val, 500);
REG_DSI_28nm_PHY_PLL_GLB_CFG  341 drivers/gpu/drm/msm/dsi/pll/dsi_pll_28nm.c 	pll_write_udelay(base + REG_DSI_28nm_PHY_PLL_GLB_CFG, val, 600);
REG_DSI_28nm_PHY_PLL_GLB_CFG  362 drivers/gpu/drm/msm/dsi/pll/dsi_pll_28nm.c 		pll_write_udelay(base + REG_DSI_28nm_PHY_PLL_GLB_CFG, val, 1);
REG_DSI_28nm_PHY_PLL_GLB_CFG  365 drivers/gpu/drm/msm/dsi/pll/dsi_pll_28nm.c 		pll_write_udelay(base + REG_DSI_28nm_PHY_PLL_GLB_CFG, val, 200);
REG_DSI_28nm_PHY_PLL_GLB_CFG  368 drivers/gpu/drm/msm/dsi/pll/dsi_pll_28nm.c 		pll_write_udelay(base + REG_DSI_28nm_PHY_PLL_GLB_CFG, val, 250);
REG_DSI_28nm_PHY_PLL_GLB_CFG  371 drivers/gpu/drm/msm/dsi/pll/dsi_pll_28nm.c 		pll_write_udelay(base + REG_DSI_28nm_PHY_PLL_GLB_CFG, val, 200);
REG_DSI_28nm_PHY_PLL_GLB_CFG  374 drivers/gpu/drm/msm/dsi/pll/dsi_pll_28nm.c 		pll_write_udelay(base + REG_DSI_28nm_PHY_PLL_GLB_CFG, val, 500);
REG_DSI_28nm_PHY_PLL_GLB_CFG  377 drivers/gpu/drm/msm/dsi/pll/dsi_pll_28nm.c 		pll_write_udelay(base + REG_DSI_28nm_PHY_PLL_GLB_CFG, val, 600);
REG_DSI_28nm_PHY_PLL_GLB_CFG  408 drivers/gpu/drm/msm/dsi/pll/dsi_pll_28nm.c 	pll_write_ndelay(base + REG_DSI_28nm_PHY_PLL_GLB_CFG, val, 500);
REG_DSI_28nm_PHY_PLL_GLB_CFG  411 drivers/gpu/drm/msm/dsi/pll/dsi_pll_28nm.c 	pll_write_ndelay(base + REG_DSI_28nm_PHY_PLL_GLB_CFG, val, 500);
REG_DSI_28nm_PHY_PLL_GLB_CFG  415 drivers/gpu/drm/msm/dsi/pll/dsi_pll_28nm.c 	pll_write_ndelay(base + REG_DSI_28nm_PHY_PLL_GLB_CFG, val, 500);
REG_DSI_28nm_PHY_PLL_GLB_CFG  436 drivers/gpu/drm/msm/dsi/pll/dsi_pll_28nm.c 	pll_write(pll_28nm->mmio + REG_DSI_28nm_PHY_PLL_GLB_CFG, 0x00);