REG_DSI_10nm_PHY_CMN_CTRL_0  120 drivers/gpu/drm/msm/dsi/phy/dsi_phy_10nm.c 	dsi_phy_write(base + REG_DSI_10nm_PHY_CMN_CTRL_0, data);
REG_DSI_10nm_PHY_CMN_CTRL_0  165 drivers/gpu/drm/msm/dsi/phy/dsi_phy_10nm.c 	dsi_phy_write(base + REG_DSI_10nm_PHY_CMN_CTRL_0, 0x7f);
REG_DSI_10nm_PHY_CMN_CTRL_0  168 drivers/gpu/drm/msm/dsi/phy/dsi_phy_10nm.c 	data = dsi_phy_read(base + REG_DSI_10nm_PHY_CMN_CTRL_0);
REG_DSI_10nm_PHY_CMN_CTRL_0  172 drivers/gpu/drm/msm/dsi/phy/dsi_phy_10nm.c 	dsi_phy_write(base + REG_DSI_10nm_PHY_CMN_CTRL_0, data);
REG_DSI_10nm_PHY_CMN_CTRL_0  368 drivers/gpu/drm/msm/dsi/pll/dsi_pll_10nm.c 	u32 data = pll_read(pll->phy_cmn_mmio + REG_DSI_10nm_PHY_CMN_CTRL_0);
REG_DSI_10nm_PHY_CMN_CTRL_0  371 drivers/gpu/drm/msm/dsi/pll/dsi_pll_10nm.c 	pll_write(pll->phy_cmn_mmio + REG_DSI_10nm_PHY_CMN_CTRL_0,
REG_DSI_10nm_PHY_CMN_CTRL_0  378 drivers/gpu/drm/msm/dsi/pll/dsi_pll_10nm.c 	u32 data = pll_read(pll->phy_cmn_mmio + REG_DSI_10nm_PHY_CMN_CTRL_0);
REG_DSI_10nm_PHY_CMN_CTRL_0  380 drivers/gpu/drm/msm/dsi/pll/dsi_pll_10nm.c 	pll_write(pll->phy_cmn_mmio + REG_DSI_10nm_PHY_CMN_CTRL_0,