REG_DSI_10nm_PHY_CMN_CLK_CFG1  390 drivers/gpu/drm/msm/dsi/pll/dsi_pll_10nm.c 	data = pll_read(pll->phy_cmn_mmio + REG_DSI_10nm_PHY_CMN_CLK_CFG1);
REG_DSI_10nm_PHY_CMN_CLK_CFG1  391 drivers/gpu/drm/msm/dsi/pll/dsi_pll_10nm.c 	pll_write(pll->phy_cmn_mmio + REG_DSI_10nm_PHY_CMN_CLK_CFG1,
REG_DSI_10nm_PHY_CMN_CLK_CFG1  399 drivers/gpu/drm/msm/dsi/pll/dsi_pll_10nm.c 	data = pll_read(pll->phy_cmn_mmio + REG_DSI_10nm_PHY_CMN_CLK_CFG1);
REG_DSI_10nm_PHY_CMN_CLK_CFG1  400 drivers/gpu/drm/msm/dsi/pll/dsi_pll_10nm.c 	pll_write(pll->phy_cmn_mmio + REG_DSI_10nm_PHY_CMN_CLK_CFG1,
REG_DSI_10nm_PHY_CMN_CLK_CFG1  548 drivers/gpu/drm/msm/dsi/pll/dsi_pll_10nm.c 	cmn_clk_cfg1 = pll_read(phy_base + REG_DSI_10nm_PHY_CMN_CLK_CFG1);
REG_DSI_10nm_PHY_CMN_CLK_CFG1  571 drivers/gpu/drm/msm/dsi/pll/dsi_pll_10nm.c 	val = pll_read(phy_base + REG_DSI_10nm_PHY_CMN_CLK_CFG1);
REG_DSI_10nm_PHY_CMN_CLK_CFG1  574 drivers/gpu/drm/msm/dsi/pll/dsi_pll_10nm.c 	pll_write(phy_base + REG_DSI_10nm_PHY_CMN_CLK_CFG1, val);
REG_DSI_10nm_PHY_CMN_CLK_CFG1  604 drivers/gpu/drm/msm/dsi/pll/dsi_pll_10nm.c 	pll_write(base + REG_DSI_10nm_PHY_CMN_CLK_CFG1, (data << 2));
REG_DSI_10nm_PHY_CMN_CLK_CFG1  763 drivers/gpu/drm/msm/dsi/pll/dsi_pll_10nm.c 				 REG_DSI_10nm_PHY_CMN_CLK_CFG1,