REG_CON0           59 drivers/clk/mediatek/clk-pll.c 	return (readl(pll->base_addr + REG_CON0) & CON0_BASE_EN) != 0;
REG_CON0          250 drivers/clk/mediatek/clk-pll.c 	r = readl(pll->base_addr + REG_CON0);
REG_CON0          252 drivers/clk/mediatek/clk-pll.c 	writel(r, pll->base_addr + REG_CON0);
REG_CON0          259 drivers/clk/mediatek/clk-pll.c 		r = readl(pll->base_addr + REG_CON0);
REG_CON0          261 drivers/clk/mediatek/clk-pll.c 		writel(r, pll->base_addr + REG_CON0);
REG_CON0          273 drivers/clk/mediatek/clk-pll.c 		r = readl(pll->base_addr + REG_CON0);
REG_CON0          275 drivers/clk/mediatek/clk-pll.c 		writel(r, pll->base_addr + REG_CON0);
REG_CON0          280 drivers/clk/mediatek/clk-pll.c 	r = readl(pll->base_addr + REG_CON0);
REG_CON0          282 drivers/clk/mediatek/clk-pll.c 	writel(r, pll->base_addr + REG_CON0);