REG_BIT          1963 drivers/gpu/drm/i915/i915_reg.h #define   ICL_DPHY_CHKN_AFE_OVER_PPI_STRAP	REG_BIT(7)
REG_BIT          2428 drivers/gpu/drm/i915/i915_reg.h #define   RESET_CTL_CAT_ERROR	   REG_BIT(2)
REG_BIT          2429 drivers/gpu/drm/i915/i915_reg.h #define   RESET_CTL_READY_TO_RESET REG_BIT(1)
REG_BIT          2430 drivers/gpu/drm/i915/i915_reg.h #define   RESET_CTL_REQUEST_RESET  REG_BIT(0)
REG_BIT          2869 drivers/gpu/drm/i915/i915_reg.h #define   ECO_CONSTANT_BUFFER_SR_DISABLE REG_BIT(4)
REG_BIT          4052 drivers/gpu/drm/i915/i915_reg.h #define   VFUNIT_CLKGATE_DIS		REG_BIT(20)
REG_BIT          4053 drivers/gpu/drm/i915/i915_reg.h #define   HSUNIT_CLKGATE_DIS		REG_BIT(8)
REG_BIT          4054 drivers/gpu/drm/i915/i915_reg.h #define   VSUNIT_CLKGATE_DIS		REG_BIT(3)
REG_BIT          4057 drivers/gpu/drm/i915/i915_reg.h #define   VSUNIT_CLKGATE_DIS_TGL	REG_BIT(19)
REG_BIT          4058 drivers/gpu/drm/i915/i915_reg.h #define   PSDUNIT_CLKGATE_DIS		REG_BIT(5)
REG_BIT          4710 drivers/gpu/drm/i915/i915_reg.h #define   PP_ON				REG_BIT(31)
REG_BIT          4717 drivers/gpu/drm/i915/i915_reg.h #define  VDD_OVERRIDE_FORCE		REG_BIT(3)
REG_BIT          4718 drivers/gpu/drm/i915/i915_reg.h #define  BACKLIGHT_ENABLE		REG_BIT(2)
REG_BIT          4719 drivers/gpu/drm/i915/i915_reg.h #define  PWR_DOWN_ON_RESET		REG_BIT(1)
REG_BIT          4720 drivers/gpu/drm/i915/i915_reg.h #define  PWR_STATE_TARGET		REG_BIT(0)
REG_BIT          4728 drivers/gpu/drm/i915/i915_reg.h #define   PP_READY			REG_BIT(30)
REG_BIT          4733 drivers/gpu/drm/i915/i915_reg.h #define   PP_CYCLE_DELAY_ACTIVE		REG_BIT(27)
REG_BIT          4750 drivers/gpu/drm/i915/i915_reg.h #define  EDP_FORCE_VDD			REG_BIT(3)
REG_BIT          4751 drivers/gpu/drm/i915/i915_reg.h #define  EDP_BLC_ENABLE			REG_BIT(2)
REG_BIT          4752 drivers/gpu/drm/i915/i915_reg.h #define  PANEL_POWER_RESET		REG_BIT(1)
REG_BIT          4753 drivers/gpu/drm/i915/i915_reg.h #define  PANEL_POWER_ON			REG_BIT(0)
REG_BIT          8752 drivers/gpu/drm/i915/i915_reg.h #define GEN9_RENDER_PG_ENABLE			REG_BIT(0)
REG_BIT          8753 drivers/gpu/drm/i915/i915_reg.h #define GEN9_MEDIA_PG_ENABLE			REG_BIT(1)
REG_BIT          8754 drivers/gpu/drm/i915/i915_reg.h #define GEN11_MEDIA_SAMPLER_PG_ENABLE		REG_BIT(2)
REG_BIT          8928 drivers/gpu/drm/i915/i915_reg.h #define   GEN11_SAMPLER_ENABLE_HEADLESS_MSG	REG_BIT(5)
REG_BIT          10274 drivers/gpu/drm/i915/i915_reg.h #define  PAL_PREC_MULTI_SEGMENT_AUTO_INCREMENT		REG_BIT(15)