REG_BASE_ADDR 167 drivers/scsi/aic94xx/aic94xx_hwi.c pci_write_config_dword(pcidev, PCI_CONF_MBAR0_SWA, REG_BASE_ADDR); REG_BASE_ADDR 171 drivers/scsi/aic94xx/aic94xx_hwi.c asd_ha->io_handle[0].swa_base = REG_BASE_ADDR; REG_BASE_ADDR 34 drivers/scsi/aic94xx/aic94xx_reg_def.h #define COMBIST (REG_BASE_ADDR + 0x00) REG_BASE_ADDR 63 drivers/scsi/aic94xx/aic94xx_reg_def.h #define COMSTAT (REG_BASE_ADDR + 0x04) REG_BASE_ADDR 76 drivers/scsi/aic94xx/aic94xx_reg_def.h #define COMSTATEN (REG_BASE_ADDR + 0x08) REG_BASE_ADDR 85 drivers/scsi/aic94xx/aic94xx_reg_def.h #define SCBPRO (REG_BASE_ADDR + 0x0C) REG_BASE_ADDR 90 drivers/scsi/aic94xx/aic94xx_reg_def.h #define CHIMREQMBX (REG_BASE_ADDR + 0x10) REG_BASE_ADDR 92 drivers/scsi/aic94xx/aic94xx_reg_def.h #define CHIMRSPMBX (REG_BASE_ADDR + 0x14) REG_BASE_ADDR 94 drivers/scsi/aic94xx/aic94xx_reg_def.h #define CHIMINT (REG_BASE_ADDR + 0x18) REG_BASE_ADDR 114 drivers/scsi/aic94xx/aic94xx_reg_def.h #define CHIMINTEN (REG_BASE_ADDR + 0x1C) REG_BASE_ADDR 144 drivers/scsi/aic94xx/aic94xx_reg_def.h #define OVLYDMACTL (REG_BASE_ADDR + 0x20) REG_BASE_ADDR 156 drivers/scsi/aic94xx/aic94xx_reg_def.h #define OVLYDMACNT (REG_BASE_ADDR + 0x24) REG_BASE_ADDR 163 drivers/scsi/aic94xx/aic94xx_reg_def.h #define OVLYDMAADR (REG_BASE_ADDR + 0x28) REG_BASE_ADDR 165 drivers/scsi/aic94xx/aic94xx_reg_def.h #define DMAERR (REG_BASE_ADDR + 0x30) REG_BASE_ADDR 170 drivers/scsi/aic94xx/aic94xx_reg_def.h #define SPIODATA (REG_BASE_ADDR + 0x34) REG_BASE_ADDR 174 drivers/scsi/aic94xx/aic94xx_reg_def.h #define T1CNTRLR (REG_BASE_ADDR + 0x40) REG_BASE_ADDR 182 drivers/scsi/aic94xx/aic94xx_reg_def.h #define T1CMPR (REG_BASE_ADDR + 0x44) REG_BASE_ADDR 184 drivers/scsi/aic94xx/aic94xx_reg_def.h #define T1CNTR (REG_BASE_ADDR + 0x48) REG_BASE_ADDR 186 drivers/scsi/aic94xx/aic94xx_reg_def.h #define T2CNTRLR (REG_BASE_ADDR + 0x4C) REG_BASE_ADDR 193 drivers/scsi/aic94xx/aic94xx_reg_def.h #define T2CMPR (REG_BASE_ADDR + 0x50) REG_BASE_ADDR 195 drivers/scsi/aic94xx/aic94xx_reg_def.h #define T2CNTR (REG_BASE_ADDR + 0x54) REG_BASE_ADDR 202 drivers/scsi/aic94xx/aic94xx_reg_def.h #define CMDCTXBASE (REG_BASE_ADDR + 0x800) REG_BASE_ADDR 204 drivers/scsi/aic94xx/aic94xx_reg_def.h #define DEVCTXBASE (REG_BASE_ADDR + 0x808) REG_BASE_ADDR 206 drivers/scsi/aic94xx/aic94xx_reg_def.h #define CTXDOMAIN (REG_BASE_ADDR + 0x810) REG_BASE_ADDR 213 drivers/scsi/aic94xx/aic94xx_reg_def.h #define DCHCTL (REG_BASE_ADDR + 0x814) REG_BASE_ADDR 237 drivers/scsi/aic94xx/aic94xx_reg_def.h #define DCHREVISION (REG_BASE_ADDR + 0x818) REG_BASE_ADDR 241 drivers/scsi/aic94xx/aic94xx_reg_def.h #define DCHSTATUS (REG_BASE_ADDR + 0x81C) REG_BASE_ADDR 259 drivers/scsi/aic94xx/aic94xx_reg_def.h #define DCHDFIFDEBUG (REG_BASE_ADDR + 0x820) REG_BASE_ADDR 265 drivers/scsi/aic94xx/aic94xx_reg_def.h #define ATOMICSTATCTL (REG_BASE_ADDR + 0x824) REG_BASE_ADDR 273 drivers/scsi/aic94xx/aic94xx_reg_def.h #define ALTCIOADR (REG_BASE_ADDR + 0x828) REG_BASE_ADDR 276 drivers/scsi/aic94xx/aic94xx_reg_def.h #define ASCBPTR (REG_BASE_ADDR + 0x82C) REG_BASE_ADDR 279 drivers/scsi/aic94xx/aic94xx_reg_def.h #define ADDBPTR (REG_BASE_ADDR + 0x82E) REG_BASE_ADDR 282 drivers/scsi/aic94xx/aic94xx_reg_def.h #define ANEWDATA (REG_BASE_ADDR + 0x830) REG_BASE_ADDR 285 drivers/scsi/aic94xx/aic94xx_reg_def.h #define AOLDDATA (REG_BASE_ADDR + 0x834) REG_BASE_ADDR 288 drivers/scsi/aic94xx/aic94xx_reg_def.h #define CTXACCESS (REG_BASE_ADDR + 0x838)