REG_ADDR 73 drivers/hwmon/ultra45_env.c writeb(ireg, p->regs + REG_ADDR); REG_ADDR 83 drivers/hwmon/ultra45_env.c writeb(ireg, p->regs + REG_ADDR); REG_ADDR 38 drivers/mfd/htc-pasic3.c void __iomem *addr = asic->mapping + (REG_ADDR << bus_shift); REG_ADDR 53 drivers/mfd/htc-pasic3.c void __iomem *addr = asic->mapping + (REG_ADDR << bus_shift); REG_ADDR 19 drivers/net/ethernet/apm/xgene-v2/mdio.c SET_REG_BITS(&val, REG_ADDR, reg); REG_ADDR 43 drivers/net/ethernet/apm/xgene-v2/mdio.c SET_REG_BITS(&val, REG_ADDR, reg); REG_ADDR 119 drivers/net/ethernet/apm/xgene/xgene_enet_sgmac.c addr = PHY_ADDR(phy_id) | REG_ADDR(reg); REG_ADDR 140 drivers/net/ethernet/apm/xgene/xgene_enet_sgmac.c addr = PHY_ADDR(phy_id) | REG_ADDR(reg); REG_ADDR 165 drivers/net/ethernet/broadcom/bnx2x/bnx2x.h #define REG_RD(bp, offset) readl(REG_ADDR(bp, offset)) REG_ADDR 166 drivers/net/ethernet/broadcom/bnx2x/bnx2x.h #define REG_RD8(bp, offset) readb(REG_ADDR(bp, offset)) REG_ADDR 167 drivers/net/ethernet/broadcom/bnx2x/bnx2x.h #define REG_RD16(bp, offset) readw(REG_ADDR(bp, offset)) REG_ADDR 170 drivers/net/ethernet/broadcom/bnx2x/bnx2x.h writel_relaxed((u32)val, REG_ADDR(bp, offset)) REG_ADDR 173 drivers/net/ethernet/broadcom/bnx2x/bnx2x.h writew_relaxed((u16)val, REG_ADDR(bp, offset)) REG_ADDR 175 drivers/net/ethernet/broadcom/bnx2x/bnx2x.h #define REG_WR(bp, offset, val) writel((u32)val, REG_ADDR(bp, offset)) REG_ADDR 176 drivers/net/ethernet/broadcom/bnx2x/bnx2x.h #define REG_WR8(bp, offset, val) writeb((u8)val, REG_ADDR(bp, offset)) REG_ADDR 177 drivers/net/ethernet/broadcom/bnx2x/bnx2x.h #define REG_WR16(bp, offset, val) writew((u16)val, REG_ADDR(bp, offset)) REG_ADDR 144 drivers/net/ethernet/broadcom/bnx2x/bnx2x_vfpf.c REG_ADDR(bp, PXP_VF_ADDR_CSDM_GLOBAL_START); REG_ADDR 35 drivers/net/ethernet/chelsio/cxgb/my3126.c #define OFFSET(REG_ADDR) (REG_ADDR << 2) REG_ADDR 48 drivers/net/ethernet/chelsio/cxgb/pm3393.c #define OFFSET(REG_ADDR) ((REG_ADDR) << 2) REG_ADDR 960 drivers/net/ethernet/qlogic/qed/qed.h #define REG_RD(cdev, offset) readl(REG_ADDR(cdev, offset)) REG_ADDR 961 drivers/net/ethernet/qlogic/qed/qed.h #define REG_WR(cdev, offset, val) writel((u32)val, REG_ADDR(cdev, offset)) REG_ADDR 962 drivers/net/ethernet/qlogic/qed/qed.h #define REG_WR16(cdev, offset, val) writew((u16)val, REG_ADDR(cdev, offset)) REG_ADDR 272 drivers/net/ethernet/qlogic/qed/qed_hw.c reg_addr = (u32 __iomem *)REG_ADDR(p_hwfn, hw_offset); REG_ADDR 86 drivers/net/phy/mdio-xgene.c data = SET_VAL(PHY_ADDR, phy_id) | SET_VAL(REG_ADDR, reg); REG_ADDR 112 drivers/net/phy/mdio-xgene.c val = SET_VAL(PHY_ADDR, phy_id) | SET_VAL(REG_ADDR, reg);