REG_A6XX_GMU_HOST2GMU_INTR_SET  251 drivers/gpu/drm/msm/adreno/a6xx_gmu.c 	gmu_write(gmu, REG_A6XX_GMU_HOST2GMU_INTR_SET, 1 << request);
REG_A6XX_GMU_HOST2GMU_INTR_SET  274 drivers/gpu/drm/msm/adreno/a6xx_gmu.c 		gmu_write(gmu, REG_A6XX_GMU_HOST2GMU_INTR_SET,
REG_A6XX_GMU_HOST2GMU_INTR_SET  278 drivers/gpu/drm/msm/adreno/a6xx_gmu.c 		gmu_write(gmu, REG_A6XX_GMU_HOST2GMU_INTR_SET,
REG_A6XX_GMU_HOST2GMU_INTR_SET  282 drivers/gpu/drm/msm/adreno/a6xx_gmu.c 		gmu_write(gmu, REG_A6XX_GMU_HOST2GMU_INTR_SET,
REG_A6XX_GMU_HOST2GMU_INTR_SET   78 drivers/gpu/drm/msm/adreno/a6xx_hfi.c 	gmu_write(gmu, REG_A6XX_GMU_HOST2GMU_INTR_SET, 0x01);