REG 99 arch/arm64/include/asm/hw_breakpoint.h #define AARCH64_DBG_READ(N, REG, VAL) do {\ REG 100 arch/arm64/include/asm/hw_breakpoint.h VAL = read_sysreg(dbg##REG##N##_el1);\ REG 103 arch/arm64/include/asm/hw_breakpoint.h #define AARCH64_DBG_WRITE(N, REG, VAL) do {\ REG 104 arch/arm64/include/asm/hw_breakpoint.h write_sysreg(VAL, dbg##REG##N##_el1);\ REG 59 arch/arm64/kernel/hw_breakpoint.c #define READ_WB_REG_CASE(OFF, N, REG, VAL) \ REG 61 arch/arm64/kernel/hw_breakpoint.c AARCH64_DBG_READ(N, REG, VAL); \ REG 64 arch/arm64/kernel/hw_breakpoint.c #define WRITE_WB_REG_CASE(OFF, N, REG, VAL) \ REG 66 arch/arm64/kernel/hw_breakpoint.c AARCH64_DBG_WRITE(N, REG, VAL); \ REG 69 arch/arm64/kernel/hw_breakpoint.c #define GEN_READ_WB_REG_CASES(OFF, REG, VAL) \ REG 70 arch/arm64/kernel/hw_breakpoint.c READ_WB_REG_CASE(OFF, 0, REG, VAL); \ REG 71 arch/arm64/kernel/hw_breakpoint.c READ_WB_REG_CASE(OFF, 1, REG, VAL); \ REG 72 arch/arm64/kernel/hw_breakpoint.c READ_WB_REG_CASE(OFF, 2, REG, VAL); \ REG 73 arch/arm64/kernel/hw_breakpoint.c READ_WB_REG_CASE(OFF, 3, REG, VAL); \ REG 74 arch/arm64/kernel/hw_breakpoint.c READ_WB_REG_CASE(OFF, 4, REG, VAL); \ REG 75 arch/arm64/kernel/hw_breakpoint.c READ_WB_REG_CASE(OFF, 5, REG, VAL); \ REG 76 arch/arm64/kernel/hw_breakpoint.c READ_WB_REG_CASE(OFF, 6, REG, VAL); \ REG 77 arch/arm64/kernel/hw_breakpoint.c READ_WB_REG_CASE(OFF, 7, REG, VAL); \ REG 78 arch/arm64/kernel/hw_breakpoint.c READ_WB_REG_CASE(OFF, 8, REG, VAL); \ REG 79 arch/arm64/kernel/hw_breakpoint.c READ_WB_REG_CASE(OFF, 9, REG, VAL); \ REG 80 arch/arm64/kernel/hw_breakpoint.c READ_WB_REG_CASE(OFF, 10, REG, VAL); \ REG 81 arch/arm64/kernel/hw_breakpoint.c READ_WB_REG_CASE(OFF, 11, REG, VAL); \ REG 82 arch/arm64/kernel/hw_breakpoint.c READ_WB_REG_CASE(OFF, 12, REG, VAL); \ REG 83 arch/arm64/kernel/hw_breakpoint.c READ_WB_REG_CASE(OFF, 13, REG, VAL); \ REG 84 arch/arm64/kernel/hw_breakpoint.c READ_WB_REG_CASE(OFF, 14, REG, VAL); \ REG 85 arch/arm64/kernel/hw_breakpoint.c READ_WB_REG_CASE(OFF, 15, REG, VAL) REG 87 arch/arm64/kernel/hw_breakpoint.c #define GEN_WRITE_WB_REG_CASES(OFF, REG, VAL) \ REG 88 arch/arm64/kernel/hw_breakpoint.c WRITE_WB_REG_CASE(OFF, 0, REG, VAL); \ REG 89 arch/arm64/kernel/hw_breakpoint.c WRITE_WB_REG_CASE(OFF, 1, REG, VAL); \ REG 90 arch/arm64/kernel/hw_breakpoint.c WRITE_WB_REG_CASE(OFF, 2, REG, VAL); \ REG 91 arch/arm64/kernel/hw_breakpoint.c WRITE_WB_REG_CASE(OFF, 3, REG, VAL); \ REG 92 arch/arm64/kernel/hw_breakpoint.c WRITE_WB_REG_CASE(OFF, 4, REG, VAL); \ REG 93 arch/arm64/kernel/hw_breakpoint.c WRITE_WB_REG_CASE(OFF, 5, REG, VAL); \ REG 94 arch/arm64/kernel/hw_breakpoint.c WRITE_WB_REG_CASE(OFF, 6, REG, VAL); \ REG 95 arch/arm64/kernel/hw_breakpoint.c WRITE_WB_REG_CASE(OFF, 7, REG, VAL); \ REG 96 arch/arm64/kernel/hw_breakpoint.c WRITE_WB_REG_CASE(OFF, 8, REG, VAL); \ REG 97 arch/arm64/kernel/hw_breakpoint.c WRITE_WB_REG_CASE(OFF, 9, REG, VAL); \ REG 98 arch/arm64/kernel/hw_breakpoint.c WRITE_WB_REG_CASE(OFF, 10, REG, VAL); \ REG 99 arch/arm64/kernel/hw_breakpoint.c WRITE_WB_REG_CASE(OFF, 11, REG, VAL); \ REG 100 arch/arm64/kernel/hw_breakpoint.c WRITE_WB_REG_CASE(OFF, 12, REG, VAL); \ REG 101 arch/arm64/kernel/hw_breakpoint.c WRITE_WB_REG_CASE(OFF, 13, REG, VAL); \ REG 102 arch/arm64/kernel/hw_breakpoint.c WRITE_WB_REG_CASE(OFF, 14, REG, VAL); \ REG 103 arch/arm64/kernel/hw_breakpoint.c WRITE_WB_REG_CASE(OFF, 15, REG, VAL) REG 42 arch/mips/ar7/irq.c REG(ESR_OFFSET(d->irq - ar7_irq_base))); REG 48 arch/mips/ar7/irq.c REG(ECR_OFFSET(d->irq - ar7_irq_base))); REG 54 arch/mips/ar7/irq.c REG(CR_OFFSET(d->irq - ar7_irq_base))); REG 59 arch/mips/ar7/irq.c writel(1 << (d->irq - ar7_irq_base - 40), REG(SEC_ESR_OFFSET)); REG 64 arch/mips/ar7/irq.c writel(1 << (d->irq - ar7_irq_base - 40), REG(SEC_ECR_OFFSET)); REG 69 arch/mips/ar7/irq.c writel(1 << (d->irq - ar7_irq_base - 40), REG(SEC_CR_OFFSET)); REG 98 arch/mips/ar7/irq.c writel(0xffffffff, REG(ECR_OFFSET(0))); REG 99 arch/mips/ar7/irq.c writel(0xff, REG(ECR_OFFSET(32))); REG 100 arch/mips/ar7/irq.c writel(0xffffffff, REG(SEC_ECR_OFFSET)); REG 101 arch/mips/ar7/irq.c writel(0xffffffff, REG(CR_OFFSET(0))); REG 102 arch/mips/ar7/irq.c writel(0xff, REG(CR_OFFSET(32))); REG 103 arch/mips/ar7/irq.c writel(0xffffffff, REG(SEC_CR_OFFSET)); REG 108 arch/mips/ar7/irq.c writel(i, REG(CHNL_OFFSET(i))); REG 136 arch/mips/ar7/irq.c irq = readl(REG(PIR_OFFSET)) & 0x3f; REG 143 arch/mips/ar7/irq.c writel(1, REG(CR_OFFSET(irq))); REG 144 arch/mips/ar7/irq.c status = readl(REG(SEC_SR_OFFSET)); REG 143 arch/mips/kvm/trace.h #define KVM_TRACE_COP0(REG, SEL) ((KVM_TRACE_HWR_COP0 << 8) | \ REG 144 arch/mips/kvm/trace.h ((REG) << 3) | (SEL)) REG 145 arch/mips/kvm/trace.h #define KVM_TRACE_HWR(REG, SEL) ((KVM_TRACE_HWR_HWR << 8) | \ REG 146 arch/mips/kvm/trace.h ((REG) << 3) | (SEL)) REG 1229 arch/powerpc/include/asm/reg.h #define MTFSF_L(REG) \ REG 1230 arch/powerpc/include/asm/reg.h .long (0xfc00058e | ((0xff) << 17) | ((REG) << 11) | (1 << 25)) REG 1232 arch/powerpc/include/asm/reg.h #define MTFSF_L(REG) mtfsf 0xff, (REG) REG 1394 arch/powerpc/kernel/process.c printk("NIP: "REG" LR: "REG" CTR: "REG"\n", REG 1398 arch/powerpc/kernel/process.c printk("MSR: "REG" ", regs->msr); REG 1403 arch/powerpc/kernel/process.c pr_cont("CFAR: "REG" ", regs->orig_gpr3); REG 1406 arch/powerpc/kernel/process.c pr_cont("DEAR: "REG" ESR: "REG" ", regs->dar, regs->dsisr); REG 1408 arch/powerpc/kernel/process.c pr_cont("DAR: "REG" DSISR: %08lx ", regs->dar, regs->dsisr); REG 1421 arch/powerpc/kernel/process.c pr_cont(REG " ", regs->gpr[i]); REG 1431 arch/powerpc/kernel/process.c printk("NIP ["REG"] %pS\n", regs->nip, (void *)regs->nip); REG 1432 arch/powerpc/kernel/process.c printk("LR ["REG"] %pS\n", regs->link, (void *)regs->link); REG 2065 arch/powerpc/kernel/process.c printk("["REG"] ["REG"] %pS", sp, ip, (void *)ip); REG 158 arch/powerpc/mm/ptdump/ptdump.c pt_dump_seq_printf(st->seq, REG "-" REG " ", st->start_address, addr - 1); REG 160 arch/powerpc/mm/ptdump/ptdump.c pt_dump_seq_printf(st->seq, "[" REG "]", st->start_pa); REG 163 arch/powerpc/mm/ptdump/ptdump.c pt_dump_seq_printf(st->seq, " " REG " ", st->start_pa); REG 1320 arch/powerpc/xmon/xmon.c printf("csum stopped at "REG"\n", adrs+i); REG 1465 arch/powerpc/xmon/xmon.c printf(" data "REG" [", dabr.address); REG 1612 arch/powerpc/xmon/xmon.c printf("["REG"] ", sp); REG 1618 arch/powerpc/xmon/xmon.c printf("["REG"] ", sp); REG 1739 arch/powerpc/xmon/xmon.c printf("*** Error reading registers from "REG"\n", REG 1750 arch/powerpc/xmon/xmon.c printf("R%.2d = "REG" R%.2d = "REG"\n", REG 1754 arch/powerpc/xmon/xmon.c printf("R%.2d = "REG" R%.2d = "REG"\n", REG 1775 arch/powerpc/xmon/xmon.c printf("msr = "REG" cr = %.8lx\n", fp->msr, fp->ccr); REG 1776 arch/powerpc/xmon/xmon.c printf("ctr = "REG" xer = "REG" trap = %4lx\n", REG 1780 arch/powerpc/xmon/xmon.c printf("dar = "REG" dsisr = %.8lx\n", fp->dar, fp->dsisr); REG 1999 arch/powerpc/xmon/xmon.c printf("msr = "REG" sprg0 = "REG"\n", REG 2001 arch/powerpc/xmon/xmon.c printf("pvr = "REG" sprg1 = "REG"\n", REG 2003 arch/powerpc/xmon/xmon.c printf("dec = "REG" sprg2 = "REG"\n", REG 2005 arch/powerpc/xmon/xmon.c printf("sp = "REG" sprg3 = "REG"\n", sp, mfspr(SPRN_SPRG3)); REG 2006 arch/powerpc/xmon/xmon.c printf("toc = "REG" dar = "REG"\n", toc, mfspr(SPRN_DAR)); REG 2117 arch/powerpc/xmon/xmon.c printf("*** Error writing address "REG"\n", adrs + n); REG 2245 arch/powerpc/xmon/xmon.c printf(REG"%c", adrs, brev? 'r': ' '); REG 2687 arch/powerpc/xmon/xmon.c printf(REG, addr); REG 2690 arch/powerpc/xmon/xmon.c printf("\nFaulted reading %d bytes from 0x"REG"\n", 16, addr); REG 2801 arch/powerpc/xmon/xmon.c printf(REG, adrs); REG 2853 arch/powerpc/xmon/xmon.c printf(REG" %s%s%s%s\n", adr, x, x, x, x); REG 2868 arch/powerpc/xmon/xmon.c printf(REG" %.8x", adr, inst); REG 3538 arch/powerpc/xmon/xmon.c printf(REG, address); REG 14 arch/sparc/include/asm/asm.h #define BRANCH_REG_ZERO(PREDICT, REG, DEST) \ REG 15 arch/sparc/include/asm/asm.h brz,PREDICT REG, DEST REG 16 arch/sparc/include/asm/asm.h #define BRANCH_REG_ZERO_ANNUL(PREDICT, REG, DEST) \ REG 17 arch/sparc/include/asm/asm.h brz,a,PREDICT REG, DEST REG 18 arch/sparc/include/asm/asm.h #define BRANCH_REG_NOT_ZERO(PREDICT, REG, DEST) \ REG 19 arch/sparc/include/asm/asm.h brnz,PREDICT REG, DEST REG 20 arch/sparc/include/asm/asm.h #define BRANCH_REG_NOT_ZERO_ANNUL(PREDICT, REG, DEST) \ REG 21 arch/sparc/include/asm/asm.h brnz,a,PREDICT REG, DEST REG 27 arch/sparc/include/asm/asm.h #define BRANCH_REG_ZERO(PREDICT, REG, DEST) \ REG 28 arch/sparc/include/asm/asm.h cmp REG, 0; \ REG 30 arch/sparc/include/asm/asm.h #define BRANCH_REG_ZERO_ANNUL(PREDICT, REG, DEST) \ REG 31 arch/sparc/include/asm/asm.h cmp REG, 0; \ REG 33 arch/sparc/include/asm/asm.h #define BRANCH_REG_NOT_ZERO(PREDICT, REG, DEST) \ REG 34 arch/sparc/include/asm/asm.h cmp REG, 0; \ REG 36 arch/sparc/include/asm/asm.h #define BRANCH_REG_NOT_ZERO_ANNUL(PREDICT, REG, DEST) \ REG 37 arch/sparc/include/asm/asm.h cmp REG, 0; \ REG 118 arch/sparc/include/asm/trap_block.h #define __GET_CPUID(REG) \ REG 120 arch/sparc/include/asm/trap_block.h 661: ldxa [%g0] ASI_UPA_CONFIG, REG; \ REG 121 arch/sparc/include/asm/trap_block.h srlx REG, 17, REG; \ REG 122 arch/sparc/include/asm/trap_block.h and REG, 0x1f, REG; \ REG 128 arch/sparc/include/asm/trap_block.h ldxa [%g0] ASI_SAFARI_CONFIG, REG; \ REG 129 arch/sparc/include/asm/trap_block.h srlx REG, 17, REG; \ REG 130 arch/sparc/include/asm/trap_block.h and REG, 0x3ff, REG; \ REG 133 arch/sparc/include/asm/trap_block.h ldxa [%g0] ASI_JBUS_CONFIG, REG; \ REG 134 arch/sparc/include/asm/trap_block.h srlx REG, 17, REG; \ REG 135 arch/sparc/include/asm/trap_block.h and REG, 0x1f, REG; \ REG 138 arch/sparc/include/asm/trap_block.h sethi %hi(0x1fff40000d0 >> 9), REG; \ REG 139 arch/sparc/include/asm/trap_block.h sllx REG, 9, REG; \ REG 140 arch/sparc/include/asm/trap_block.h or REG, 0xd0, REG; \ REG 141 arch/sparc/include/asm/trap_block.h lduwa [REG] ASI_PHYS_BYPASS_EC_E, REG;\ REG 143 arch/sparc/include/asm/trap_block.h mov SCRATCHPAD_CPUID, REG; \ REG 144 arch/sparc/include/asm/trap_block.h ldxa [REG] ASI_SCRATCHPAD, REG; \ REG 77 arch/sparc/include/asm/tsb.h #define TSB_LOAD_QUAD(TSB, REG) \ REG 78 arch/sparc/include/asm/tsb.h 661: ldda [TSB] ASI_NUCLEUS_QUAD_LDD, REG; \ REG 81 arch/sparc/include/asm/tsb.h ldda [TSB] ASI_QUAD_LDD_PHYS, REG; \ REG 82 arch/sparc/include/asm/tsb.h ldda [TSB] ASI_QUAD_LDD_PHYS_4V, REG; \ REG 85 arch/sparc/include/asm/tsb.h #define TSB_LOAD_TAG_HIGH(TSB, REG) \ REG 86 arch/sparc/include/asm/tsb.h 661: lduwa [TSB] ASI_N, REG; \ REG 89 arch/sparc/include/asm/tsb.h lduwa [TSB] ASI_PHYS_USE_EC, REG; \ REG 92 arch/sparc/include/asm/tsb.h #define TSB_LOAD_TAG(TSB, REG) \ REG 93 arch/sparc/include/asm/tsb.h 661: ldxa [TSB] ASI_N, REG; \ REG 96 arch/sparc/include/asm/tsb.h ldxa [TSB] ASI_PHYS_USE_EC, REG; \ REG 75 arch/sparc/kernel/pci_schizo.c #define SCHIZO_CONFIG_ENCODE(BUS, DEVFN, REG) \ REG 78 arch/sparc/kernel/pci_schizo.c ((unsigned long)(REG))) REG 102 arch/sparc/kernel/prom_irqtrans.c #define SABRE_CONFIG_ENCODE(BUS, DEVFN, REG) \ REG 105 arch/sparc/kernel/prom_irqtrans.c ((unsigned long)(REG))) REG 15 arch/sparc/kernel/psycho_common.h #define PSYCHO_CONFIG_ENCODE(BUS, DEVFN, REG) \ REG 18 arch/sparc/kernel/psycho_common.h ((unsigned long)(REG))) REG 68 arch/sparc/net/bpf_jit_comp_32.c #define SETHI(K, REG) \ REG 69 arch/sparc/net/bpf_jit_comp_32.c (F2(0, 0x4) | RD(REG) | (((K) >> 10) & 0x3fffff)) REG 70 arch/sparc/net/bpf_jit_comp_32.c #define OR_LO(K, REG) \ REG 71 arch/sparc/net/bpf_jit_comp_32.c (F3(2, 0x02) | IMMED | RS1(REG) | ((K) & 0x3ff) | RD(REG)) REG 121 arch/sparc/net/bpf_jit_comp_32.c #define emit_clear(REG) \ REG 123 arch/sparc/net/bpf_jit_comp_32.c *prog++ = OR | RS1(G0) | RS2(G0) | RD(REG); \ REG 126 arch/sparc/net/bpf_jit_comp_32.c #define emit_set_const(K, REG) \ REG 128 arch/sparc/net/bpf_jit_comp_32.c *prog++ = SETHI(K, REG); \ REG 130 arch/sparc/net/bpf_jit_comp_32.c *prog++ = OR_LO(K, REG); \ REG 220 arch/sparc/net/bpf_jit_comp_32.c #define emit_load_cpu(REG) \ REG 221 arch/sparc/net/bpf_jit_comp_32.c emit_load32(G6, struct thread_info, cpu, REG) REG 223 arch/sparc/net/bpf_jit_comp_32.c #define emit_load_cpu(REG) emit_clear(REG) REG 258 arch/sparc/net/bpf_jit_comp_32.c #define emit_read_y(REG) *prog++ = RD_Y | RD(REG) REG 259 arch/sparc/net/bpf_jit_comp_32.c #define emit_write_y(REG) *prog++ = WR_Y | IMMED | RS1(REG) | S13(0) REG 136 arch/sparc/net/bpf_jit_comp_64.c #define SETHI(K, REG) \ REG 137 arch/sparc/net/bpf_jit_comp_64.c (F2(0, 0x4) | RD(REG) | (((K) >> 10) & 0x3fffff)) REG 138 arch/sparc/net/bpf_jit_comp_64.c #define OR_LO(K, REG) \ REG 139 arch/sparc/net/bpf_jit_comp_64.c (F3(2, 0x02) | IMMED | RS1(REG) | ((K) & 0x3ff) | RD(REG)) REG 643 arch/sparc/net/bpf_jit_comp_64.c #define emit_read_y(REG, CTX) emit(RD_Y | RD(REG), CTX) REG 644 arch/sparc/net/bpf_jit_comp_64.c #define emit_write_y(REG, CTX) emit(WR_Y | IMMED | RS1(REG) | S13(0), CTX) REG 43 drivers/block/swim.c REG(write_data) REG 44 drivers/block/swim.c REG(write_mark) REG 45 drivers/block/swim.c REG(write_CRC) REG 46 drivers/block/swim.c REG(write_parameter) REG 47 drivers/block/swim.c REG(write_phase) REG 48 drivers/block/swim.c REG(write_setup) REG 49 drivers/block/swim.c REG(write_mode0) REG 50 drivers/block/swim.c REG(write_mode1) REG 52 drivers/block/swim.c REG(read_data) REG 53 drivers/block/swim.c REG(read_mark) REG 54 drivers/block/swim.c REG(read_error) REG 55 drivers/block/swim.c REG(read_parameter) REG 56 drivers/block/swim.c REG(read_phase) REG 57 drivers/block/swim.c REG(read_setup) REG 58 drivers/block/swim.c REG(read_status) REG 59 drivers/block/swim.c REG(read_handshake) REG 68 drivers/block/swim.c REG(ph0L) REG 69 drivers/block/swim.c REG(ph0H) REG 70 drivers/block/swim.c REG(ph1L) REG 71 drivers/block/swim.c REG(ph1H) REG 72 drivers/block/swim.c REG(ph2L) REG 73 drivers/block/swim.c REG(ph2H) REG 74 drivers/block/swim.c REG(ph3L) REG 75 drivers/block/swim.c REG(ph3H) REG 76 drivers/block/swim.c REG(mtrOff) REG 77 drivers/block/swim.c REG(mtrOn) REG 78 drivers/block/swim.c REG(intDrive) REG 79 drivers/block/swim.c REG(extDrive) REG 80 drivers/block/swim.c REG(q6L) REG 81 drivers/block/swim.c REG(q6H) REG 82 drivers/block/swim.c REG(q7L) REG 83 drivers/block/swim.c REG(q7H) REG 62 drivers/block/swim3.c REG(data); REG 63 drivers/block/swim3.c REG(timer); /* counts down at 1MHz */ REG 64 drivers/block/swim3.c REG(error); REG 65 drivers/block/swim3.c REG(mode); REG 66 drivers/block/swim3.c REG(select); /* controls CA0, CA1, CA2 and LSTRB signals */ REG 67 drivers/block/swim3.c REG(setup); REG 68 drivers/block/swim3.c REG(control); /* writing bits clears them */ REG 69 drivers/block/swim3.c REG(status); /* writing bits sets them in control */ REG 70 drivers/block/swim3.c REG(intr); REG 71 drivers/block/swim3.c REG(nseek); /* # tracks to seek */ REG 72 drivers/block/swim3.c REG(ctrack); /* current track number */ REG 73 drivers/block/swim3.c REG(csect); /* current sector number */ REG 74 drivers/block/swim3.c REG(gap3); /* size of gap 3 in track format */ REG 75 drivers/block/swim3.c REG(sector); /* sector # to read or write */ REG 76 drivers/block/swim3.c REG(nsect); /* # sectors to read or write */ REG 77 drivers/block/swim3.c REG(intr_enable); REG 84 drivers/clk/clk-lochnagar.c #define LN1_CLK(ID, NAME, REG) \ REG 87 drivers/clk/clk-lochnagar.c .cfg_reg = LOCHNAGAR1_##REG, \ REG 82 drivers/gpio/gpio-it87.c if (!request_muxed_region(REG, 2, KBUILD_MODNAME)) REG 85 drivers/gpio/gpio-it87.c outb(0x87, REG); REG 86 drivers/gpio/gpio-it87.c outb(0x01, REG); REG 87 drivers/gpio/gpio-it87.c outb(0x55, REG); REG 88 drivers/gpio/gpio-it87.c outb(0x55, REG); REG 94 drivers/gpio/gpio-it87.c outb(0x02, REG); REG 96 drivers/gpio/gpio-it87.c release_region(REG, 2); REG 101 drivers/gpio/gpio-it87.c outb(LDNREG, REG); REG 107 drivers/gpio/gpio-it87.c outb(reg, REG); REG 113 drivers/gpio/gpio-it87.c outb(reg, REG); REG 121 drivers/gpio/gpio-it87.c outb(reg++, REG); REG 123 drivers/gpio/gpio-it87.c outb(reg, REG); REG 130 drivers/gpio/gpio-it87.c outb(reg++, REG); REG 132 drivers/gpio/gpio-it87.c outb(reg, REG); REG 111 drivers/gpu/drm/amd/display/dc/dce/dce_aux.c if (REG(AUX_RESET_MASK)) { REG 122 drivers/gpu/drm/amd/display/dc/dce/dce_aux.c if (REG(AUX_RESET_MASK)) { REG 176 drivers/gpu/drm/amd/display/dc/dce/dce_aux.c if (REG(AUXN_IMPCAL)) { REG 240 drivers/gpu/drm/amd/display/dc/dce/dce_dmcu.c dm_write_reg(dmcu->ctx, REG(MASTER_COMM_DATA_REG1), REG 252 drivers/gpu/drm/amd/display/dc/dce/dce_dmcu.c dm_write_reg(dmcu->ctx, REG(MASTER_COMM_DATA_REG2), REG 257 drivers/gpu/drm/amd/display/dc/dce/dce_dmcu.c dm_write_reg(dmcu->ctx, REG(MASTER_COMM_DATA_REG3), REG 305 drivers/gpu/drm/amd/display/dc/dce/dce_dmcu.c dm_write_reg(dmcu->ctx, REG(MASTER_COMM_DATA_REG1), masterCmdData1.u32); REG 653 drivers/gpu/drm/amd/display/dc/dce/dce_dmcu.c dm_write_reg(dmcu->ctx, REG(MASTER_COMM_DATA_REG1), REG 665 drivers/gpu/drm/amd/display/dc/dce/dce_dmcu.c dm_write_reg(dmcu->ctx, REG(MASTER_COMM_DATA_REG2), REG 670 drivers/gpu/drm/amd/display/dc/dce/dce_dmcu.c dm_write_reg(dmcu->ctx, REG(MASTER_COMM_DATA_REG3), REG 705 drivers/gpu/drm/amd/display/dc/dce/dce_dmcu.c dm_write_reg(dmcu->ctx, REG(MASTER_COMM_DATA_REG1), masterCmdData1.u32); REG 111 drivers/gpu/drm/amd/display/dc/dce/dce_hwseq.c if (REG(BLND_CONTROL[blnd_inst]) == REG(BLNDV_CONTROL) || REG 131 drivers/gpu/drm/amd/display/dc/dce/dce_hwseq.c if (REG(DC_MEM_GLOBAL_PWR_REQ_CNTL)) REG 139 drivers/gpu/drm/amd/display/dc/dce/dce_hwseq.c if (REG(DCFEV_CLOCK_CONTROL)) REG 191 drivers/gpu/drm/amd/display/dc/dce/dce_hwseq.c if (REG(PHYPLL_PIXEL_RATE_CNTL[tg_inst])) REG 179 drivers/gpu/drm/amd/display/dc/dce/dce_ipp.c if (REG(DCFE_MEM_PWR_CTRL)) REG 211 drivers/gpu/drm/amd/display/dc/dce/dce_ipp.c if (REG(DCFE_MEM_PWR_CTRL)) REG 269 drivers/gpu/drm/amd/display/dc/dce/dce_link_encoder.c ASSERT(REG(DP_DPHY_INTERNAL_CTRL)); REG 410 drivers/gpu/drm/amd/display/dc/dce/dce_link_encoder.c if (REG(DP_DPHY_HBR2_PATTERN_CONTROL)) REG 201 drivers/gpu/drm/amd/display/dc/dce/dce_mem_input.c if (REG(DPG_PIPE_NB_PSTATE_CHANGE_CONTROL)) { REG 214 drivers/gpu/drm/amd/display/dc/dce/dce_mem_input.c if (REG(DPG_PIPE_LOW_POWER_CONTROL)) { REG 237 drivers/gpu/drm/amd/display/dc/dce/dce_mem_input.c if (REG(DPG_PIPE_STUTTER_CONTROL2)) REG 255 drivers/gpu/drm/amd/display/dc/dce/dce_mem_input.c if (REG(DPG_PIPE_STUTTER_CONTROL2)) REG 295 drivers/gpu/drm/amd/display/dc/dce/dce_opp.c if (REG(FMT_TEMPORAL_DITHER_PATTERN_CONTROL)) { REG 77 drivers/gpu/drm/amd/display/dc/dce/dce_stream_encoder.c if (REG(AFMT_CNTL)) REG 80 drivers/gpu/drm/amd/display/dc/dce/dce_stream_encoder.c if (REG(AFMT_VBI_PACKET_CONTROL1)) { REG 134 drivers/gpu/drm/amd/display/dc/dce/dce_stream_encoder.c if (!REG(AFMT_VBI_PACKET_CONTROL1)) { REG 141 drivers/gpu/drm/amd/display/dc/dce/dce_stream_encoder.c if (REG(AFMT_VBI_PACKET_CONTROL1)) { REG 236 drivers/gpu/drm/amd/display/dc/dce/dce_stream_encoder.c if (REG(HDMI_GENERIC_PACKET_CONTROL2)) REG 243 drivers/gpu/drm/amd/display/dc/dce/dce_stream_encoder.c if (REG(HDMI_GENERIC_PACKET_CONTROL2)) REG 250 drivers/gpu/drm/amd/display/dc/dce/dce_stream_encoder.c if (REG(HDMI_GENERIC_PACKET_CONTROL3)) REG 257 drivers/gpu/drm/amd/display/dc/dce/dce_stream_encoder.c if (REG(HDMI_GENERIC_PACKET_CONTROL3)) REG 344 drivers/gpu/drm/amd/display/dc/dce/dce_stream_encoder.c if (REG(DP_MSA_MISC)) REG 399 drivers/gpu/drm/amd/display/dc/dce/dce_stream_encoder.c if (REG(DP_MSA_TIMING_PARAM1)) { REG 458 drivers/gpu/drm/amd/display/dc/dce/dce_stream_encoder.c if (REG(DP_MSA_COLORIMETRY)) REG 461 drivers/gpu/drm/amd/display/dc/dce/dce_stream_encoder.c if (REG(DP_MSA_MISC)) REG 467 drivers/gpu/drm/amd/display/dc/dce/dce_stream_encoder.c if (REG(DP_MSA_TIMING_PARAM1)) REG 494 drivers/gpu/drm/amd/display/dc/dce/dce_stream_encoder.c if (REG(DP_MSA_TIMING_PARAM2)) REG 499 drivers/gpu/drm/amd/display/dc/dce/dce_stream_encoder.c if (REG(DP_MSA_TIMING_PARAM3)) REG 511 drivers/gpu/drm/amd/display/dc/dce/dce_stream_encoder.c if (REG(DP_MSA_TIMING_PARAM4)) REG 753 drivers/gpu/drm/amd/display/dc/dce/dce_stream_encoder.c if (REG(AFMT_CNTL)) REG 792 drivers/gpu/drm/amd/display/dc/dce/dce_stream_encoder.c if (REG(HDMI_DB_CONTROL)) REG 829 drivers/gpu/drm/amd/display/dc/dce/dce_stream_encoder.c if (REG(HDMI_GENERIC_PACKET_CONTROL2)) REG 838 drivers/gpu/drm/amd/display/dc/dce/dce_stream_encoder.c if (REG(HDMI_GENERIC_PACKET_CONTROL3)) REG 1482 drivers/gpu/drm/amd/display/dc/dce/dce_stream_encoder.c if (REG(AFMT_CNTL) == 0) REG 197 drivers/gpu/drm/amd/display/dc/dce/dce_transform.c if (REG(DCFE_MEM_PWR_CTRL)) { REG 231 drivers/gpu/drm/amd/display/dc/dce/dce_transform.c if (REG(DCFE_MEM_PWR_CTRL)) REG 1147 drivers/gpu/drm/amd/display/dc/dce/dce_transform.c if (REG(DCFE_MEM_PWR_CTRL)) REG 1155 drivers/gpu/drm/amd/display/dc/dce/dce_transform.c if (REG(DCFE_MEM_PWR_STATUS)) { REG 1201 drivers/gpu/drm/amd/display/dc/dce/dce_transform.c if (REG(DCFE_MEM_PWR_CTRL)) REG 1305 drivers/gpu/drm/amd/display/dc/dce/dce_transform.c if (REG(DCFE_MEM_PWR_CTRL)) REG 145 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dpp_cm.c gam_regs.csc_c11_c12 = REG(CM_GAMUT_REMAP_C11_C12); REG 146 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dpp_cm.c gam_regs.csc_c33_c34 = REG(CM_GAMUT_REMAP_C33_C34); REG 155 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dpp_cm.c gam_regs.csc_c11_c12 = REG(CM_COMA_C11_C12); REG 156 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dpp_cm.c gam_regs.csc_c33_c34 = REG(CM_COMA_C33_C34); REG 165 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dpp_cm.c gam_regs.csc_c11_c12 = REG(CM_COMB_C11_C12); REG 166 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dpp_cm.c gam_regs.csc_c33_c34 = REG(CM_COMB_C33_C34); REG 240 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dpp_cm.c gam_regs.csc_c11_c12 = REG(CM_OCSC_C11_C12); REG 241 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dpp_cm.c gam_regs.csc_c33_c34 = REG(CM_OCSC_C33_C34); REG 245 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dpp_cm.c gam_regs.csc_c11_c12 = REG(CM_COMB_C11_C12); REG 246 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dpp_cm.c gam_regs.csc_c33_c34 = REG(CM_COMB_C33_C34); REG 391 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dpp_cm.c gam_regs.start_cntl_b = REG(CM_RGAM_RAMA_START_CNTL_B); REG 392 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dpp_cm.c gam_regs.start_cntl_g = REG(CM_RGAM_RAMA_START_CNTL_G); REG 393 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dpp_cm.c gam_regs.start_cntl_r = REG(CM_RGAM_RAMA_START_CNTL_R); REG 394 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dpp_cm.c gam_regs.start_slope_cntl_b = REG(CM_RGAM_RAMA_SLOPE_CNTL_B); REG 395 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dpp_cm.c gam_regs.start_slope_cntl_g = REG(CM_RGAM_RAMA_SLOPE_CNTL_G); REG 396 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dpp_cm.c gam_regs.start_slope_cntl_r = REG(CM_RGAM_RAMA_SLOPE_CNTL_R); REG 397 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dpp_cm.c gam_regs.start_end_cntl1_b = REG(CM_RGAM_RAMA_END_CNTL1_B); REG 398 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dpp_cm.c gam_regs.start_end_cntl2_b = REG(CM_RGAM_RAMA_END_CNTL2_B); REG 399 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dpp_cm.c gam_regs.start_end_cntl1_g = REG(CM_RGAM_RAMA_END_CNTL1_G); REG 400 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dpp_cm.c gam_regs.start_end_cntl2_g = REG(CM_RGAM_RAMA_END_CNTL2_G); REG 401 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dpp_cm.c gam_regs.start_end_cntl1_r = REG(CM_RGAM_RAMA_END_CNTL1_R); REG 402 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dpp_cm.c gam_regs.start_end_cntl2_r = REG(CM_RGAM_RAMA_END_CNTL2_R); REG 403 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dpp_cm.c gam_regs.region_start = REG(CM_RGAM_RAMA_REGION_0_1); REG 404 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dpp_cm.c gam_regs.region_end = REG(CM_RGAM_RAMA_REGION_32_33); REG 420 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dpp_cm.c gam_regs.start_cntl_b = REG(CM_RGAM_RAMB_START_CNTL_B); REG 421 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dpp_cm.c gam_regs.start_cntl_g = REG(CM_RGAM_RAMB_START_CNTL_G); REG 422 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dpp_cm.c gam_regs.start_cntl_r = REG(CM_RGAM_RAMB_START_CNTL_R); REG 423 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dpp_cm.c gam_regs.start_slope_cntl_b = REG(CM_RGAM_RAMB_SLOPE_CNTL_B); REG 424 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dpp_cm.c gam_regs.start_slope_cntl_g = REG(CM_RGAM_RAMB_SLOPE_CNTL_G); REG 425 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dpp_cm.c gam_regs.start_slope_cntl_r = REG(CM_RGAM_RAMB_SLOPE_CNTL_R); REG 426 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dpp_cm.c gam_regs.start_end_cntl1_b = REG(CM_RGAM_RAMB_END_CNTL1_B); REG 427 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dpp_cm.c gam_regs.start_end_cntl2_b = REG(CM_RGAM_RAMB_END_CNTL2_B); REG 428 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dpp_cm.c gam_regs.start_end_cntl1_g = REG(CM_RGAM_RAMB_END_CNTL1_G); REG 429 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dpp_cm.c gam_regs.start_end_cntl2_g = REG(CM_RGAM_RAMB_END_CNTL2_G); REG 430 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dpp_cm.c gam_regs.start_end_cntl1_r = REG(CM_RGAM_RAMB_END_CNTL1_R); REG 431 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dpp_cm.c gam_regs.start_end_cntl2_r = REG(CM_RGAM_RAMB_END_CNTL2_R); REG 432 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dpp_cm.c gam_regs.region_start = REG(CM_RGAM_RAMB_REGION_0_1); REG 433 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dpp_cm.c gam_regs.region_end = REG(CM_RGAM_RAMB_REGION_32_33); REG 494 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dpp_cm.c gam_regs.csc_c11_c12 = REG(CM_ICSC_C11_C12); REG 495 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dpp_cm.c gam_regs.csc_c33_c34 = REG(CM_ICSC_C33_C34); REG 499 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dpp_cm.c gam_regs.csc_c11_c12 = REG(CM_COMA_C11_C12); REG 500 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dpp_cm.c gam_regs.csc_c33_c34 = REG(CM_COMA_C33_C34); REG 544 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dpp_cm.c gam_regs.start_cntl_b = REG(CM_DGAM_RAMB_START_CNTL_B); REG 545 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dpp_cm.c gam_regs.start_cntl_g = REG(CM_DGAM_RAMB_START_CNTL_G); REG 546 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dpp_cm.c gam_regs.start_cntl_r = REG(CM_DGAM_RAMB_START_CNTL_R); REG 547 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dpp_cm.c gam_regs.start_slope_cntl_b = REG(CM_DGAM_RAMB_SLOPE_CNTL_B); REG 548 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dpp_cm.c gam_regs.start_slope_cntl_g = REG(CM_DGAM_RAMB_SLOPE_CNTL_G); REG 549 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dpp_cm.c gam_regs.start_slope_cntl_r = REG(CM_DGAM_RAMB_SLOPE_CNTL_R); REG 550 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dpp_cm.c gam_regs.start_end_cntl1_b = REG(CM_DGAM_RAMB_END_CNTL1_B); REG 551 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dpp_cm.c gam_regs.start_end_cntl2_b = REG(CM_DGAM_RAMB_END_CNTL2_B); REG 552 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dpp_cm.c gam_regs.start_end_cntl1_g = REG(CM_DGAM_RAMB_END_CNTL1_G); REG 553 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dpp_cm.c gam_regs.start_end_cntl2_g = REG(CM_DGAM_RAMB_END_CNTL2_G); REG 554 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dpp_cm.c gam_regs.start_end_cntl1_r = REG(CM_DGAM_RAMB_END_CNTL1_R); REG 555 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dpp_cm.c gam_regs.start_end_cntl2_r = REG(CM_DGAM_RAMB_END_CNTL2_R); REG 556 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dpp_cm.c gam_regs.region_start = REG(CM_DGAM_RAMB_REGION_0_1); REG 557 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dpp_cm.c gam_regs.region_end = REG(CM_DGAM_RAMB_REGION_14_15); REG 573 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dpp_cm.c gam_regs.start_cntl_b = REG(CM_DGAM_RAMA_START_CNTL_B); REG 574 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dpp_cm.c gam_regs.start_cntl_g = REG(CM_DGAM_RAMA_START_CNTL_G); REG 575 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dpp_cm.c gam_regs.start_cntl_r = REG(CM_DGAM_RAMA_START_CNTL_R); REG 576 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dpp_cm.c gam_regs.start_slope_cntl_b = REG(CM_DGAM_RAMA_SLOPE_CNTL_B); REG 577 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dpp_cm.c gam_regs.start_slope_cntl_g = REG(CM_DGAM_RAMA_SLOPE_CNTL_G); REG 578 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dpp_cm.c gam_regs.start_slope_cntl_r = REG(CM_DGAM_RAMA_SLOPE_CNTL_R); REG 579 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dpp_cm.c gam_regs.start_end_cntl1_b = REG(CM_DGAM_RAMA_END_CNTL1_B); REG 580 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dpp_cm.c gam_regs.start_end_cntl2_b = REG(CM_DGAM_RAMA_END_CNTL2_B); REG 581 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dpp_cm.c gam_regs.start_end_cntl1_g = REG(CM_DGAM_RAMA_END_CNTL1_G); REG 582 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dpp_cm.c gam_regs.start_end_cntl2_g = REG(CM_DGAM_RAMA_END_CNTL2_G); REG 583 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dpp_cm.c gam_regs.start_end_cntl1_r = REG(CM_DGAM_RAMA_END_CNTL1_R); REG 584 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dpp_cm.c gam_regs.start_end_cntl2_r = REG(CM_DGAM_RAMA_END_CNTL2_R); REG 585 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dpp_cm.c gam_regs.region_start = REG(CM_DGAM_RAMA_REGION_0_1); REG 586 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dpp_cm.c gam_regs.region_end = REG(CM_DGAM_RAMA_REGION_14_15); REG 618 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dpp_dscl.c if (REG(SCL_VERT_FILTER_INIT_BOT)) { REG 632 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dpp_dscl.c if (REG(SCL_VERT_FILTER_INIT_BOT_C)) { REG 713 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dpp_dscl.c if (REG(SCL_BLACK_OFFSET)) { REG 56 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hubbub.c if (REG(DCHUBBUB_ARB_ALLOW_SR_ENTER_WATERMARK_A)) { REG 66 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hubbub.c if (REG(DCHUBBUB_ARB_ALLOW_SR_ENTER_WATERMARK_B)) { REG 76 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hubbub.c if (REG(DCHUBBUB_ARB_ALLOW_SR_ENTER_WATERMARK_C)) { REG 86 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hubbub.c if (REG(DCHUBBUB_ARB_ALLOW_SR_ENTER_WATERMARK_D)) { REG 638 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hubbub.c if (REG(DCHUBBUB_SDPIF_FB_TOP) == 0) { REG 605 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hubp.c if (REG(NOM_PARAMETERS_0)) REG 609 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hubp.c if (REG(NOM_PARAMETERS_1)) REG 626 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hubp.c if (REG(NOM_PARAMETERS_2)) REG 630 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hubp.c if (REG(NOM_PARAMETERS_3)) REG 878 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hubp.c if (REG(PREFETCH_SETTINS)) REG 901 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hubp.c if (REG(NOM_PARAMETERS_0)) REG 905 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hubp.c if (REG(NOM_PARAMETERS_1)) REG 923 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hubp.c if (REG(PREFETCH_SETTINS_C)) REG 936 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hubp.c if (REG(NOM_PARAMETERS_2)) REG 940 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hubp.c if (REG(NOM_PARAMETERS_3)) REG 90 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c if (REG(MPC_CRC_RESULT_GB)) REG 93 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c if (REG(DPP_TOP0_DPP_CRC_VAL_B_A)) REG 506 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c if (REG(DOMAIN1_PG_CONFIG) == 0) REG 558 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c if (REG(DOMAIN0_PG_CONFIG) == 0) REG 605 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c if (REG(DC_IP_REQUEST_CNTL)) { REG 1013 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c if (REG(DC_IP_REQUEST_CNTL)) { REG 236 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_link_encoder.c if (!REG(DP_DPHY_INTERNAL_CTRL)) REG 381 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_link_encoder.c if (REG(DP_DPHY_HBR2_PATTERN_CONTROL)) REG 362 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_mpc.c if (REG(MUX[opp_id])) REG 380 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_mpc.c if (opp_id < MAX_OPP && REG(MUX[opp_id])) REG 372 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_opp.c if (REG(OPPBUF_CONTROL1)) REG 251 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_optc.c if (REG(OTG_INTERLACE_CONTROL)) { REG 324 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_optc.c if (REG(OTG_INTERLACE_CONTROL)) { REG 1421 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_stream_encoder.c if (REG(AFMT_CNTL) == 0) REG 243 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dpp_cm.c gam_regs.start_cntl_b = REG(CM_BLNDGAM_RAMA_START_CNTL_B); REG 244 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dpp_cm.c gam_regs.start_cntl_g = REG(CM_BLNDGAM_RAMA_START_CNTL_G); REG 245 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dpp_cm.c gam_regs.start_cntl_r = REG(CM_BLNDGAM_RAMA_START_CNTL_R); REG 246 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dpp_cm.c gam_regs.start_slope_cntl_b = REG(CM_BLNDGAM_RAMA_SLOPE_CNTL_B); REG 247 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dpp_cm.c gam_regs.start_slope_cntl_g = REG(CM_BLNDGAM_RAMA_SLOPE_CNTL_G); REG 248 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dpp_cm.c gam_regs.start_slope_cntl_r = REG(CM_BLNDGAM_RAMA_SLOPE_CNTL_R); REG 249 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dpp_cm.c gam_regs.start_end_cntl1_b = REG(CM_BLNDGAM_RAMA_END_CNTL1_B); REG 250 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dpp_cm.c gam_regs.start_end_cntl2_b = REG(CM_BLNDGAM_RAMA_END_CNTL2_B); REG 251 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dpp_cm.c gam_regs.start_end_cntl1_g = REG(CM_BLNDGAM_RAMA_END_CNTL1_G); REG 252 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dpp_cm.c gam_regs.start_end_cntl2_g = REG(CM_BLNDGAM_RAMA_END_CNTL2_G); REG 253 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dpp_cm.c gam_regs.start_end_cntl1_r = REG(CM_BLNDGAM_RAMA_END_CNTL1_R); REG 254 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dpp_cm.c gam_regs.start_end_cntl2_r = REG(CM_BLNDGAM_RAMA_END_CNTL2_R); REG 255 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dpp_cm.c gam_regs.region_start = REG(CM_BLNDGAM_RAMA_REGION_0_1); REG 256 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dpp_cm.c gam_regs.region_end = REG(CM_BLNDGAM_RAMA_REGION_32_33); REG 271 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dpp_cm.c gam_regs.start_cntl_b = REG(CM_BLNDGAM_RAMB_START_CNTL_B); REG 272 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dpp_cm.c gam_regs.start_cntl_g = REG(CM_BLNDGAM_RAMB_START_CNTL_G); REG 273 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dpp_cm.c gam_regs.start_cntl_r = REG(CM_BLNDGAM_RAMB_START_CNTL_R); REG 274 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dpp_cm.c gam_regs.start_slope_cntl_b = REG(CM_BLNDGAM_RAMB_SLOPE_CNTL_B); REG 275 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dpp_cm.c gam_regs.start_slope_cntl_g = REG(CM_BLNDGAM_RAMB_SLOPE_CNTL_G); REG 276 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dpp_cm.c gam_regs.start_slope_cntl_r = REG(CM_BLNDGAM_RAMB_SLOPE_CNTL_R); REG 277 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dpp_cm.c gam_regs.start_end_cntl1_b = REG(CM_BLNDGAM_RAMB_END_CNTL1_B); REG 278 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dpp_cm.c gam_regs.start_end_cntl2_b = REG(CM_BLNDGAM_RAMB_END_CNTL2_B); REG 279 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dpp_cm.c gam_regs.start_end_cntl1_g = REG(CM_BLNDGAM_RAMB_END_CNTL1_G); REG 280 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dpp_cm.c gam_regs.start_end_cntl2_g = REG(CM_BLNDGAM_RAMB_END_CNTL2_G); REG 281 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dpp_cm.c gam_regs.start_end_cntl1_r = REG(CM_BLNDGAM_RAMB_END_CNTL1_R); REG 282 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dpp_cm.c gam_regs.start_end_cntl2_r = REG(CM_BLNDGAM_RAMB_END_CNTL2_R); REG 283 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dpp_cm.c gam_regs.region_start = REG(CM_BLNDGAM_RAMB_REGION_0_1); REG 284 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dpp_cm.c gam_regs.region_end = REG(CM_BLNDGAM_RAMB_REGION_32_33); REG 406 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hubbub.c if (REG(DCN_VM_FB_LOCATION_TOP) == 0) REG 488 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hubbub.c if (REG(DCHUBBUB_ARB_PTE_META_URGENCY_WATERMARK_A)) REG 490 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hubbub.c if (REG(DCHUBBUB_ARB_ALLOW_SR_ENTER_WATERMARK_A)) { REG 499 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hubbub.c if (REG(DCHUBBUB_ARB_PTE_META_URGENCY_WATERMARK_B)) REG 501 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hubbub.c if (REG(DCHUBBUB_ARB_ALLOW_SR_ENTER_WATERMARK_B)) { REG 510 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hubbub.c if (REG(DCHUBBUB_ARB_PTE_META_URGENCY_WATERMARK_C)) REG 512 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hubbub.c if (REG(DCHUBBUB_ARB_ALLOW_SR_ENTER_WATERMARK_C)) { REG 521 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hubbub.c if (REG(DCHUBBUB_ARB_PTE_META_URGENCY_WATERMARK_D)) REG 523 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hubbub.c if (REG(DCHUBBUB_ARB_ALLOW_SR_ENTER_WATERMARK_D)) { REG 106 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hubp.c if (REG(NOM_PARAMETERS_0)) REG 110 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hubp.c if (REG(NOM_PARAMETERS_1)) REG 127 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hubp.c if (REG(NOM_PARAMETERS_2)) REG 131 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hubp.c if (REG(NOM_PARAMETERS_3)) REG 1076 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hubp.c if (REG(PREFETCH_SETTINS)) REG 1099 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hubp.c if (REG(NOM_PARAMETERS_0)) REG 1103 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hubp.c if (REG(NOM_PARAMETERS_1)) REG 1121 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hubp.c if (REG(PREFETCH_SETTINS_C)) REG 1134 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hubp.c if (REG(NOM_PARAMETERS_2)) REG 1138 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hubp.c if (REG(NOM_PARAMETERS_3)) REG 81 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hwseq.c if (REG(DOMAIN8_PG_CONFIG)) REG 83 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hwseq.c if (REG(DOMAIN10_PG_CONFIG)) REG 91 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hwseq.c if (REG(DOMAIN9_PG_CONFIG)) REG 93 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hwseq.c if (REG(DOMAIN11_PG_CONFIG)) REG 100 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hwseq.c if (REG(DOMAIN19_PG_CONFIG)) REG 102 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hwseq.c if (REG(DOMAIN20_PG_CONFIG)) REG 104 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hwseq.c if (REG(DOMAIN21_PG_CONFIG)) REG 259 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hwseq.c if (REG(DOMAIN16_PG_CONFIG) == 0) REG 335 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hwseq.c if (REG(DOMAIN1_PG_CONFIG) == 0) REG 409 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hwseq.c if (REG(DOMAIN0_PG_CONFIG) == 0) REG 913 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hwseq.c if (REG(DC_IP_REQUEST_CNTL)) { REG 2018 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hwseq.c if (REG(REFCLK_CNTL)) REG 154 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_mpc.c ocsc_regs.csc_c11_c12 = REG(CSC_C11_C12_A[opp_id]); REG 155 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_mpc.c ocsc_regs.csc_c33_c34 = REG(CSC_C33_C34_A[opp_id]); REG 157 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_mpc.c ocsc_regs.csc_c11_c12 = REG(CSC_C11_C12_B[opp_id]); REG 158 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_mpc.c ocsc_regs.csc_c33_c34 = REG(CSC_C33_C34_B[opp_id]); REG 195 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_mpc.c ocsc_regs.csc_c11_c12 = REG(CSC_C11_C12_A[opp_id]); REG 196 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_mpc.c ocsc_regs.csc_c33_c34 = REG(CSC_C33_C34_A[opp_id]); REG 198 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_mpc.c ocsc_regs.csc_c11_c12 = REG(CSC_C11_C12_B[opp_id]); REG 199 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_mpc.c ocsc_regs.csc_c33_c34 = REG(CSC_C33_C34_B[opp_id]); REG 294 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_mpc.c gam_regs.start_cntl_b = REG(MPCC_OGAM_RAMB_START_CNTL_B[mpcc_id]); REG 295 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_mpc.c gam_regs.start_cntl_g = REG(MPCC_OGAM_RAMB_START_CNTL_G[mpcc_id]); REG 296 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_mpc.c gam_regs.start_cntl_r = REG(MPCC_OGAM_RAMB_START_CNTL_R[mpcc_id]); REG 297 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_mpc.c gam_regs.start_slope_cntl_b = REG(MPCC_OGAM_RAMB_SLOPE_CNTL_B[mpcc_id]); REG 298 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_mpc.c gam_regs.start_slope_cntl_g = REG(MPCC_OGAM_RAMB_SLOPE_CNTL_G[mpcc_id]); REG 299 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_mpc.c gam_regs.start_slope_cntl_r = REG(MPCC_OGAM_RAMB_SLOPE_CNTL_R[mpcc_id]); REG 300 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_mpc.c gam_regs.start_end_cntl1_b = REG(MPCC_OGAM_RAMB_END_CNTL1_B[mpcc_id]); REG 301 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_mpc.c gam_regs.start_end_cntl2_b = REG(MPCC_OGAM_RAMB_END_CNTL2_B[mpcc_id]); REG 302 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_mpc.c gam_regs.start_end_cntl1_g = REG(MPCC_OGAM_RAMB_END_CNTL1_G[mpcc_id]); REG 303 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_mpc.c gam_regs.start_end_cntl2_g = REG(MPCC_OGAM_RAMB_END_CNTL2_G[mpcc_id]); REG 304 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_mpc.c gam_regs.start_end_cntl1_r = REG(MPCC_OGAM_RAMB_END_CNTL1_R[mpcc_id]); REG 305 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_mpc.c gam_regs.start_end_cntl2_r = REG(MPCC_OGAM_RAMB_END_CNTL2_R[mpcc_id]); REG 306 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_mpc.c gam_regs.region_start = REG(MPCC_OGAM_RAMB_REGION_0_1[mpcc_id]); REG 307 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_mpc.c gam_regs.region_end = REG(MPCC_OGAM_RAMB_REGION_32_33[mpcc_id]); REG 321 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_mpc.c gam_regs.start_cntl_b = REG(MPCC_OGAM_RAMA_START_CNTL_B[mpcc_id]); REG 322 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_mpc.c gam_regs.start_cntl_g = REG(MPCC_OGAM_RAMA_START_CNTL_G[mpcc_id]); REG 323 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_mpc.c gam_regs.start_cntl_r = REG(MPCC_OGAM_RAMA_START_CNTL_R[mpcc_id]); REG 324 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_mpc.c gam_regs.start_slope_cntl_b = REG(MPCC_OGAM_RAMA_SLOPE_CNTL_B[mpcc_id]); REG 325 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_mpc.c gam_regs.start_slope_cntl_g = REG(MPCC_OGAM_RAMA_SLOPE_CNTL_G[mpcc_id]); REG 326 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_mpc.c gam_regs.start_slope_cntl_r = REG(MPCC_OGAM_RAMA_SLOPE_CNTL_R[mpcc_id]); REG 327 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_mpc.c gam_regs.start_end_cntl1_b = REG(MPCC_OGAM_RAMA_END_CNTL1_B[mpcc_id]); REG 328 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_mpc.c gam_regs.start_end_cntl2_b = REG(MPCC_OGAM_RAMA_END_CNTL2_B[mpcc_id]); REG 329 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_mpc.c gam_regs.start_end_cntl1_g = REG(MPCC_OGAM_RAMA_END_CNTL1_G[mpcc_id]); REG 330 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_mpc.c gam_regs.start_end_cntl2_g = REG(MPCC_OGAM_RAMA_END_CNTL2_G[mpcc_id]); REG 331 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_mpc.c gam_regs.start_end_cntl1_r = REG(MPCC_OGAM_RAMA_END_CNTL1_R[mpcc_id]); REG 332 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_mpc.c gam_regs.start_end_cntl2_r = REG(MPCC_OGAM_RAMA_END_CNTL2_R[mpcc_id]); REG 333 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_mpc.c gam_regs.region_start = REG(MPCC_OGAM_RAMA_REGION_0_1[mpcc_id]); REG 334 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_mpc.c gam_regs.region_end = REG(MPCC_OGAM_RAMA_REGION_32_33[mpcc_id]); REG 258 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_optc.c if (REG(OPTC_MEMORY_CONFIG)) REG 69 drivers/gpu/drm/amd/display/dc/gpio/dce120/hw_translate_dce120.c case REG(DC_GPIO_GENERIC_A): REG 99 drivers/gpu/drm/amd/display/dc/gpio/dce120/hw_translate_dce120.c case REG(DC_GPIO_HPD_A): REG 126 drivers/gpu/drm/amd/display/dc/gpio/dce120/hw_translate_dce120.c case REG(DC_GPIO_SYNCA_A): REG 141 drivers/gpu/drm/amd/display/dc/gpio/dce120/hw_translate_dce120.c case REG(DC_GPIO_GENLK_A): REG 165 drivers/gpu/drm/amd/display/dc/gpio/dce120/hw_translate_dce120.c case REG(DC_GPIO_DDC1_A): REG 168 drivers/gpu/drm/amd/display/dc/gpio/dce120/hw_translate_dce120.c case REG(DC_GPIO_DDC2_A): REG 171 drivers/gpu/drm/amd/display/dc/gpio/dce120/hw_translate_dce120.c case REG(DC_GPIO_DDC3_A): REG 174 drivers/gpu/drm/amd/display/dc/gpio/dce120/hw_translate_dce120.c case REG(DC_GPIO_DDC4_A): REG 177 drivers/gpu/drm/amd/display/dc/gpio/dce120/hw_translate_dce120.c case REG(DC_GPIO_DDC5_A): REG 180 drivers/gpu/drm/amd/display/dc/gpio/dce120/hw_translate_dce120.c case REG(DC_GPIO_DDC6_A): REG 183 drivers/gpu/drm/amd/display/dc/gpio/dce120/hw_translate_dce120.c case REG(DC_GPIO_DDCVGA_A): REG 187 drivers/gpu/drm/amd/display/dc/gpio/dce120/hw_translate_dce120.c case REG(DC_GPIO_I2CPAD_A): REG 191 drivers/gpu/drm/amd/display/dc/gpio/dce120/hw_translate_dce120.c case REG(DC_GPIO_PWRSEQ_A): REG 192 drivers/gpu/drm/amd/display/dc/gpio/dce120/hw_translate_dce120.c case REG(DC_GPIO_PAD_STRENGTH_1): REG 193 drivers/gpu/drm/amd/display/dc/gpio/dce120/hw_translate_dce120.c case REG(DC_GPIO_PAD_STRENGTH_2): REG 194 drivers/gpu/drm/amd/display/dc/gpio/dce120/hw_translate_dce120.c case REG(DC_GPIO_DEBUG): REG 215 drivers/gpu/drm/amd/display/dc/gpio/dce120/hw_translate_dce120.c info->offset = REG(DC_GPIO_DDC1_A); REG 218 drivers/gpu/drm/amd/display/dc/gpio/dce120/hw_translate_dce120.c info->offset = REG(DC_GPIO_DDC2_A); REG 221 drivers/gpu/drm/amd/display/dc/gpio/dce120/hw_translate_dce120.c info->offset = REG(DC_GPIO_DDC3_A); REG 224 drivers/gpu/drm/amd/display/dc/gpio/dce120/hw_translate_dce120.c info->offset = REG(DC_GPIO_DDC4_A); REG 227 drivers/gpu/drm/amd/display/dc/gpio/dce120/hw_translate_dce120.c info->offset = REG(DC_GPIO_DDC5_A); REG 230 drivers/gpu/drm/amd/display/dc/gpio/dce120/hw_translate_dce120.c info->offset = REG(DC_GPIO_DDC6_A); REG 233 drivers/gpu/drm/amd/display/dc/gpio/dce120/hw_translate_dce120.c info->offset = REG(DC_GPIO_DDCVGA_A); REG 236 drivers/gpu/drm/amd/display/dc/gpio/dce120/hw_translate_dce120.c info->offset = REG(DC_GPIO_I2CPAD_A); REG 247 drivers/gpu/drm/amd/display/dc/gpio/dce120/hw_translate_dce120.c info->offset = REG(DC_GPIO_DDC1_A); REG 250 drivers/gpu/drm/amd/display/dc/gpio/dce120/hw_translate_dce120.c info->offset = REG(DC_GPIO_DDC2_A); REG 253 drivers/gpu/drm/amd/display/dc/gpio/dce120/hw_translate_dce120.c info->offset = REG(DC_GPIO_DDC3_A); REG 256 drivers/gpu/drm/amd/display/dc/gpio/dce120/hw_translate_dce120.c info->offset = REG(DC_GPIO_DDC4_A); REG 259 drivers/gpu/drm/amd/display/dc/gpio/dce120/hw_translate_dce120.c info->offset = REG(DC_GPIO_DDC5_A); REG 262 drivers/gpu/drm/amd/display/dc/gpio/dce120/hw_translate_dce120.c info->offset = REG(DC_GPIO_DDC6_A); REG 265 drivers/gpu/drm/amd/display/dc/gpio/dce120/hw_translate_dce120.c info->offset = REG(DC_GPIO_DDCVGA_A); REG 268 drivers/gpu/drm/amd/display/dc/gpio/dce120/hw_translate_dce120.c info->offset = REG(DC_GPIO_I2CPAD_A); REG 276 drivers/gpu/drm/amd/display/dc/gpio/dce120/hw_translate_dce120.c info->offset = REG(DC_GPIO_GENERIC_A); REG 305 drivers/gpu/drm/amd/display/dc/gpio/dce120/hw_translate_dce120.c info->offset = REG(DC_GPIO_HPD_A); REG 333 drivers/gpu/drm/amd/display/dc/gpio/dce120/hw_translate_dce120.c info->offset = REG(DC_GPIO_SYNCA_A); REG 337 drivers/gpu/drm/amd/display/dc/gpio/dce120/hw_translate_dce120.c info->offset = REG(DC_GPIO_SYNCA_A); REG 350 drivers/gpu/drm/amd/display/dc/gpio/dce120/hw_translate_dce120.c info->offset = REG(DC_GPIO_GENLK_A); REG 354 drivers/gpu/drm/amd/display/dc/gpio/dce120/hw_translate_dce120.c info->offset = REG(DC_GPIO_GENLK_A); REG 359 drivers/gpu/drm/amd/display/dc/gpio/dce120/hw_translate_dce120.c info->offset = REG(DC_GPIO_GENLK_A); REG 363 drivers/gpu/drm/amd/display/dc/gpio/dce120/hw_translate_dce120.c info->offset = REG(DC_GPIO_GENLK_A); REG 69 drivers/gpu/drm/amd/display/dc/gpio/dcn10/hw_translate_dcn10.c case REG(DC_GPIO_GENERIC_A): REG 99 drivers/gpu/drm/amd/display/dc/gpio/dcn10/hw_translate_dcn10.c case REG(DC_GPIO_HPD_A): REG 126 drivers/gpu/drm/amd/display/dc/gpio/dcn10/hw_translate_dcn10.c case REG(DC_GPIO_SYNCA_A): REG 141 drivers/gpu/drm/amd/display/dc/gpio/dcn10/hw_translate_dcn10.c case REG(DC_GPIO_GENLK_A): REG 165 drivers/gpu/drm/amd/display/dc/gpio/dcn10/hw_translate_dcn10.c case REG(DC_GPIO_DDC1_A): REG 168 drivers/gpu/drm/amd/display/dc/gpio/dcn10/hw_translate_dcn10.c case REG(DC_GPIO_DDC2_A): REG 171 drivers/gpu/drm/amd/display/dc/gpio/dcn10/hw_translate_dcn10.c case REG(DC_GPIO_DDC3_A): REG 174 drivers/gpu/drm/amd/display/dc/gpio/dcn10/hw_translate_dcn10.c case REG(DC_GPIO_DDC4_A): REG 177 drivers/gpu/drm/amd/display/dc/gpio/dcn10/hw_translate_dcn10.c case REG(DC_GPIO_DDC5_A): REG 180 drivers/gpu/drm/amd/display/dc/gpio/dcn10/hw_translate_dcn10.c case REG(DC_GPIO_DDC6_A): REG 183 drivers/gpu/drm/amd/display/dc/gpio/dcn10/hw_translate_dcn10.c case REG(DC_GPIO_DDCVGA_A): REG 187 drivers/gpu/drm/amd/display/dc/gpio/dcn10/hw_translate_dcn10.c case REG(DC_GPIO_I2CPAD_A): REG 191 drivers/gpu/drm/amd/display/dc/gpio/dcn10/hw_translate_dcn10.c case REG(DC_GPIO_PWRSEQ_A): REG 192 drivers/gpu/drm/amd/display/dc/gpio/dcn10/hw_translate_dcn10.c case REG(DC_GPIO_PAD_STRENGTH_1): REG 193 drivers/gpu/drm/amd/display/dc/gpio/dcn10/hw_translate_dcn10.c case REG(DC_GPIO_PAD_STRENGTH_2): REG 194 drivers/gpu/drm/amd/display/dc/gpio/dcn10/hw_translate_dcn10.c case REG(DC_GPIO_DEBUG): REG 215 drivers/gpu/drm/amd/display/dc/gpio/dcn10/hw_translate_dcn10.c info->offset = REG(DC_GPIO_DDC1_A); REG 218 drivers/gpu/drm/amd/display/dc/gpio/dcn10/hw_translate_dcn10.c info->offset = REG(DC_GPIO_DDC2_A); REG 221 drivers/gpu/drm/amd/display/dc/gpio/dcn10/hw_translate_dcn10.c info->offset = REG(DC_GPIO_DDC3_A); REG 224 drivers/gpu/drm/amd/display/dc/gpio/dcn10/hw_translate_dcn10.c info->offset = REG(DC_GPIO_DDC4_A); REG 227 drivers/gpu/drm/amd/display/dc/gpio/dcn10/hw_translate_dcn10.c info->offset = REG(DC_GPIO_DDC5_A); REG 230 drivers/gpu/drm/amd/display/dc/gpio/dcn10/hw_translate_dcn10.c info->offset = REG(DC_GPIO_DDC6_A); REG 233 drivers/gpu/drm/amd/display/dc/gpio/dcn10/hw_translate_dcn10.c info->offset = REG(DC_GPIO_DDCVGA_A); REG 236 drivers/gpu/drm/amd/display/dc/gpio/dcn10/hw_translate_dcn10.c info->offset = REG(DC_GPIO_I2CPAD_A); REG 247 drivers/gpu/drm/amd/display/dc/gpio/dcn10/hw_translate_dcn10.c info->offset = REG(DC_GPIO_DDC1_A); REG 250 drivers/gpu/drm/amd/display/dc/gpio/dcn10/hw_translate_dcn10.c info->offset = REG(DC_GPIO_DDC2_A); REG 253 drivers/gpu/drm/amd/display/dc/gpio/dcn10/hw_translate_dcn10.c info->offset = REG(DC_GPIO_DDC3_A); REG 256 drivers/gpu/drm/amd/display/dc/gpio/dcn10/hw_translate_dcn10.c info->offset = REG(DC_GPIO_DDC4_A); REG 259 drivers/gpu/drm/amd/display/dc/gpio/dcn10/hw_translate_dcn10.c info->offset = REG(DC_GPIO_DDC5_A); REG 262 drivers/gpu/drm/amd/display/dc/gpio/dcn10/hw_translate_dcn10.c info->offset = REG(DC_GPIO_DDC6_A); REG 265 drivers/gpu/drm/amd/display/dc/gpio/dcn10/hw_translate_dcn10.c info->offset = REG(DC_GPIO_DDCVGA_A); REG 268 drivers/gpu/drm/amd/display/dc/gpio/dcn10/hw_translate_dcn10.c info->offset = REG(DC_GPIO_I2CPAD_A); REG 276 drivers/gpu/drm/amd/display/dc/gpio/dcn10/hw_translate_dcn10.c info->offset = REG(DC_GPIO_GENERIC_A); REG 305 drivers/gpu/drm/amd/display/dc/gpio/dcn10/hw_translate_dcn10.c info->offset = REG(DC_GPIO_HPD_A); REG 333 drivers/gpu/drm/amd/display/dc/gpio/dcn10/hw_translate_dcn10.c info->offset = REG(DC_GPIO_SYNCA_A); REG 337 drivers/gpu/drm/amd/display/dc/gpio/dcn10/hw_translate_dcn10.c info->offset = REG(DC_GPIO_SYNCA_A); REG 350 drivers/gpu/drm/amd/display/dc/gpio/dcn10/hw_translate_dcn10.c info->offset = REG(DC_GPIO_GENLK_A); REG 354 drivers/gpu/drm/amd/display/dc/gpio/dcn10/hw_translate_dcn10.c info->offset = REG(DC_GPIO_GENLK_A); REG 359 drivers/gpu/drm/amd/display/dc/gpio/dcn10/hw_translate_dcn10.c info->offset = REG(DC_GPIO_GENLK_A); REG 363 drivers/gpu/drm/amd/display/dc/gpio/dcn10/hw_translate_dcn10.c info->offset = REG(DC_GPIO_GENLK_A); REG 74 drivers/gpu/drm/amd/display/dc/gpio/dcn20/hw_translate_dcn20.c case REG(DC_GPIO_GENERIC_A): REG 104 drivers/gpu/drm/amd/display/dc/gpio/dcn20/hw_translate_dcn20.c case REG(DC_GPIO_HPD_A): REG 131 drivers/gpu/drm/amd/display/dc/gpio/dcn20/hw_translate_dcn20.c case REG(DC_GPIO_GENLK_A): REG 155 drivers/gpu/drm/amd/display/dc/gpio/dcn20/hw_translate_dcn20.c case REG(DC_GPIO_DDC1_A): REG 158 drivers/gpu/drm/amd/display/dc/gpio/dcn20/hw_translate_dcn20.c case REG(DC_GPIO_DDC2_A): REG 161 drivers/gpu/drm/amd/display/dc/gpio/dcn20/hw_translate_dcn20.c case REG(DC_GPIO_DDC3_A): REG 164 drivers/gpu/drm/amd/display/dc/gpio/dcn20/hw_translate_dcn20.c case REG(DC_GPIO_DDC4_A): REG 167 drivers/gpu/drm/amd/display/dc/gpio/dcn20/hw_translate_dcn20.c case REG(DC_GPIO_DDC5_A): REG 170 drivers/gpu/drm/amd/display/dc/gpio/dcn20/hw_translate_dcn20.c case REG(DC_GPIO_DDC6_A): REG 173 drivers/gpu/drm/amd/display/dc/gpio/dcn20/hw_translate_dcn20.c case REG(DC_GPIO_DDCVGA_A): REG 202 drivers/gpu/drm/amd/display/dc/gpio/dcn20/hw_translate_dcn20.c info->offset = REG(DC_GPIO_DDC1_A); REG 205 drivers/gpu/drm/amd/display/dc/gpio/dcn20/hw_translate_dcn20.c info->offset = REG(DC_GPIO_DDC2_A); REG 208 drivers/gpu/drm/amd/display/dc/gpio/dcn20/hw_translate_dcn20.c info->offset = REG(DC_GPIO_DDC3_A); REG 211 drivers/gpu/drm/amd/display/dc/gpio/dcn20/hw_translate_dcn20.c info->offset = REG(DC_GPIO_DDC4_A); REG 214 drivers/gpu/drm/amd/display/dc/gpio/dcn20/hw_translate_dcn20.c info->offset = REG(DC_GPIO_DDC5_A); REG 217 drivers/gpu/drm/amd/display/dc/gpio/dcn20/hw_translate_dcn20.c info->offset = REG(DC_GPIO_DDC6_A); REG 220 drivers/gpu/drm/amd/display/dc/gpio/dcn20/hw_translate_dcn20.c info->offset = REG(DC_GPIO_DDCVGA_A); REG 232 drivers/gpu/drm/amd/display/dc/gpio/dcn20/hw_translate_dcn20.c info->offset = REG(DC_GPIO_DDC1_A); REG 235 drivers/gpu/drm/amd/display/dc/gpio/dcn20/hw_translate_dcn20.c info->offset = REG(DC_GPIO_DDC2_A); REG 238 drivers/gpu/drm/amd/display/dc/gpio/dcn20/hw_translate_dcn20.c info->offset = REG(DC_GPIO_DDC3_A); REG 241 drivers/gpu/drm/amd/display/dc/gpio/dcn20/hw_translate_dcn20.c info->offset = REG(DC_GPIO_DDC4_A); REG 244 drivers/gpu/drm/amd/display/dc/gpio/dcn20/hw_translate_dcn20.c info->offset = REG(DC_GPIO_DDC5_A); REG 247 drivers/gpu/drm/amd/display/dc/gpio/dcn20/hw_translate_dcn20.c info->offset = REG(DC_GPIO_DDC6_A); REG 250 drivers/gpu/drm/amd/display/dc/gpio/dcn20/hw_translate_dcn20.c info->offset = REG(DC_GPIO_DDCVGA_A); REG 259 drivers/gpu/drm/amd/display/dc/gpio/dcn20/hw_translate_dcn20.c info->offset = REG(DC_GPIO_GENERIC_A); REG 288 drivers/gpu/drm/amd/display/dc/gpio/dcn20/hw_translate_dcn20.c info->offset = REG(DC_GPIO_HPD_A); REG 73 drivers/gpu/drm/amd/display/dc/gpio/dcn21/hw_translate_dcn21.c case REG(DC_GPIO_GENERIC_A): REG 107 drivers/gpu/drm/amd/display/dc/gpio/dcn21/hw_translate_dcn21.c case REG(DC_GPIO_HPD_A): REG 134 drivers/gpu/drm/amd/display/dc/gpio/dcn21/hw_translate_dcn21.c case REG(DC_GPIO_GENLK_A): REG 158 drivers/gpu/drm/amd/display/dc/gpio/dcn21/hw_translate_dcn21.c case REG(DC_GPIO_DDC1_A): REG 161 drivers/gpu/drm/amd/display/dc/gpio/dcn21/hw_translate_dcn21.c case REG(DC_GPIO_DDC2_A): REG 164 drivers/gpu/drm/amd/display/dc/gpio/dcn21/hw_translate_dcn21.c case REG(DC_GPIO_DDC3_A): REG 167 drivers/gpu/drm/amd/display/dc/gpio/dcn21/hw_translate_dcn21.c case REG(DC_GPIO_DDC4_A): REG 170 drivers/gpu/drm/amd/display/dc/gpio/dcn21/hw_translate_dcn21.c case REG(DC_GPIO_DDC5_A): REG 173 drivers/gpu/drm/amd/display/dc/gpio/dcn21/hw_translate_dcn21.c case REG(DC_GPIO_DDCVGA_A): REG 207 drivers/gpu/drm/amd/display/dc/gpio/dcn21/hw_translate_dcn21.c info->offset = REG(DC_GPIO_DDC1_A); REG 210 drivers/gpu/drm/amd/display/dc/gpio/dcn21/hw_translate_dcn21.c info->offset = REG(DC_GPIO_DDC2_A); REG 213 drivers/gpu/drm/amd/display/dc/gpio/dcn21/hw_translate_dcn21.c info->offset = REG(DC_GPIO_DDC3_A); REG 216 drivers/gpu/drm/amd/display/dc/gpio/dcn21/hw_translate_dcn21.c info->offset = REG(DC_GPIO_DDC4_A); REG 219 drivers/gpu/drm/amd/display/dc/gpio/dcn21/hw_translate_dcn21.c info->offset = REG(DC_GPIO_DDC5_A); REG 222 drivers/gpu/drm/amd/display/dc/gpio/dcn21/hw_translate_dcn21.c info->offset = REG(DC_GPIO_DDCVGA_A); REG 234 drivers/gpu/drm/amd/display/dc/gpio/dcn21/hw_translate_dcn21.c info->offset = REG(DC_GPIO_DDC1_A); REG 237 drivers/gpu/drm/amd/display/dc/gpio/dcn21/hw_translate_dcn21.c info->offset = REG(DC_GPIO_DDC2_A); REG 240 drivers/gpu/drm/amd/display/dc/gpio/dcn21/hw_translate_dcn21.c info->offset = REG(DC_GPIO_DDC3_A); REG 243 drivers/gpu/drm/amd/display/dc/gpio/dcn21/hw_translate_dcn21.c info->offset = REG(DC_GPIO_DDC4_A); REG 246 drivers/gpu/drm/amd/display/dc/gpio/dcn21/hw_translate_dcn21.c info->offset = REG(DC_GPIO_DDC5_A); REG 249 drivers/gpu/drm/amd/display/dc/gpio/dcn21/hw_translate_dcn21.c info->offset = REG(DC_GPIO_DDCVGA_A); REG 258 drivers/gpu/drm/amd/display/dc/gpio/dcn21/hw_translate_dcn21.c info->offset = REG(DC_GPIO_GENERIC_A); REG 287 drivers/gpu/drm/amd/display/dc/gpio/dcn21/hw_translate_dcn21.c info->offset = REG(DC_GPIO_HPD_A); REG 35 drivers/gpu/drm/amd/display/dc/gpio/ddc_regs.h .type ## _reg = REG(DC_GPIO_DDC ## id ## _ ## type),\ REG 49 drivers/gpu/drm/amd/display/dc/gpio/ddc_regs.h .ddc_setup = REG(DC_I2C_DDC ## id ## _SETUP) REG 54 drivers/gpu/drm/amd/display/dc/gpio/ddc_regs.h .ddc_setup = REG(DC_I2C_DDC ## id ## _SETUP),\ REG 55 drivers/gpu/drm/amd/display/dc/gpio/ddc_regs.h .phy_aux_cntl = REG(PHY_AUX_CNTL), \ REG 56 drivers/gpu/drm/amd/display/dc/gpio/ddc_regs.h .dc_gpio_aux_ctrl_5 = REG(DC_GPIO_AUX_CTRL_5) REG 60 drivers/gpu/drm/amd/display/dc/gpio/ddc_regs.h .type ## _reg = REG(DC_GPIO_DDCVGA_ ## type),\ REG 77 drivers/gpu/drm/amd/display/dc/gpio/ddc_regs.h .type ## _reg = REG(DC_GPIO_I2CPAD_ ## type),\ REG 97 drivers/gpu/drm/amd/display/dc/gpio/ddc_regs.h .phy_aux_cntl = REG(PHY_AUX_CNTL), \ REG 98 drivers/gpu/drm/amd/display/dc/gpio/ddc_regs.h .dc_gpio_aux_ctrl_5 = REG(DC_GPIO_AUX_CTRL_5) REG 32 drivers/gpu/drm/amd/display/dc/gpio/generic_regs.h .type ## _reg = REG(DC_GPIO_GENERIC_## type),\ REG 46 drivers/gpu/drm/amd/display/dc/gpio/generic_regs.h .mux = REG(DC_GENERIC ## id),\ REG 40 drivers/gpu/drm/amd/display/dc/gpio/hpd_regs.h .type ## _reg = REG(DC_GPIO_HPD_## type),\ REG 40 drivers/gpu/drm/amd/display/dc/inc/reg_helper.h dm_read_reg(CTX, REG(reg_name)) REG 43 drivers/gpu/drm/amd/display/dc/inc/reg_helper.h dm_write_reg(CTX, REG(reg_name), value) REG 56 drivers/gpu/drm/amd/display/dc/inc/reg_helper.h REG(reg_name), \ REG 157 drivers/gpu/drm/amd/display/dc/inc/reg_helper.h generic_reg_get(CTX, REG(reg_name), \ REG 161 drivers/gpu/drm/amd/display/dc/inc/reg_helper.h generic_reg_get2(CTX, REG(reg_name), \ REG 166 drivers/gpu/drm/amd/display/dc/inc/reg_helper.h generic_reg_get3(CTX, REG(reg_name), \ REG 172 drivers/gpu/drm/amd/display/dc/inc/reg_helper.h generic_reg_get4(CTX, REG(reg_name), \ REG 179 drivers/gpu/drm/amd/display/dc/inc/reg_helper.h generic_reg_get5(CTX, REG(reg_name), \ REG 187 drivers/gpu/drm/amd/display/dc/inc/reg_helper.h generic_reg_get6(CTX, REG(reg_name), \ REG 196 drivers/gpu/drm/amd/display/dc/inc/reg_helper.h generic_reg_get7(CTX, REG(reg_name), \ REG 206 drivers/gpu/drm/amd/display/dc/inc/reg_helper.h generic_reg_get8(CTX, REG(reg_name), \ REG 220 drivers/gpu/drm/amd/display/dc/inc/reg_helper.h REG(reg_name), FN(reg_name, field), val,\ REG 227 drivers/gpu/drm/amd/display/dc/inc/reg_helper.h REG(reg_name), \ REG 448 drivers/gpu/drm/amd/display/dc/inc/reg_helper.h REG(index_reg_name), REG(data_reg_name), IND_REG(index), \ REG 459 drivers/gpu/drm/amd/display/dc/inc/reg_helper.h generic_read_indirect_reg(CTX, REG(index_reg_name), REG(data_reg_name), IND_REG(index)) REG 465 drivers/gpu/drm/amd/display/dc/inc/reg_helper.h REG(index_reg_name), REG(data_reg_name), IND_REG(index), \ REG 109 drivers/gpu/drm/i2c/tda998x_drv.c #define REG_VERSION_LSB REG(0x00, 0x00) /* read */ REG 110 drivers/gpu/drm/i2c/tda998x_drv.c #define REG_MAIN_CNTRL0 REG(0x00, 0x01) /* read/write */ REG 117 drivers/gpu/drm/i2c/tda998x_drv.c #define REG_VERSION_MSB REG(0x00, 0x02) /* read */ REG 118 drivers/gpu/drm/i2c/tda998x_drv.c #define REG_SOFTRESET REG(0x00, 0x0a) /* write */ REG 121 drivers/gpu/drm/i2c/tda998x_drv.c #define REG_DDC_DISABLE REG(0x00, 0x0b) /* read/write */ REG 122 drivers/gpu/drm/i2c/tda998x_drv.c #define REG_CCLK_ON REG(0x00, 0x0c) /* read/write */ REG 123 drivers/gpu/drm/i2c/tda998x_drv.c #define REG_I2C_MASTER REG(0x00, 0x0d) /* read/write */ REG 127 drivers/gpu/drm/i2c/tda998x_drv.c #define REG_FEAT_POWERDOWN REG(0x00, 0x0e) /* read/write */ REG 131 drivers/gpu/drm/i2c/tda998x_drv.c #define REG_INT_FLAGS_0 REG(0x00, 0x0f) /* read/write */ REG 132 drivers/gpu/drm/i2c/tda998x_drv.c #define REG_INT_FLAGS_1 REG(0x00, 0x10) /* read/write */ REG 133 drivers/gpu/drm/i2c/tda998x_drv.c #define REG_INT_FLAGS_2 REG(0x00, 0x11) /* read/write */ REG 135 drivers/gpu/drm/i2c/tda998x_drv.c #define REG_ENA_ACLK REG(0x00, 0x16) /* read/write */ REG 136 drivers/gpu/drm/i2c/tda998x_drv.c #define REG_ENA_VP_0 REG(0x00, 0x18) /* read/write */ REG 137 drivers/gpu/drm/i2c/tda998x_drv.c #define REG_ENA_VP_1 REG(0x00, 0x19) /* read/write */ REG 138 drivers/gpu/drm/i2c/tda998x_drv.c #define REG_ENA_VP_2 REG(0x00, 0x1a) /* read/write */ REG 139 drivers/gpu/drm/i2c/tda998x_drv.c #define REG_ENA_AP REG(0x00, 0x1e) /* read/write */ REG 140 drivers/gpu/drm/i2c/tda998x_drv.c #define REG_VIP_CNTRL_0 REG(0x00, 0x20) /* write */ REG 145 drivers/gpu/drm/i2c/tda998x_drv.c #define REG_VIP_CNTRL_1 REG(0x00, 0x21) /* write */ REG 150 drivers/gpu/drm/i2c/tda998x_drv.c #define REG_VIP_CNTRL_2 REG(0x00, 0x22) /* write */ REG 155 drivers/gpu/drm/i2c/tda998x_drv.c #define REG_VIP_CNTRL_3 REG(0x00, 0x23) /* write */ REG 164 drivers/gpu/drm/i2c/tda998x_drv.c #define REG_VIP_CNTRL_4 REG(0x00, 0x24) /* write */ REG 171 drivers/gpu/drm/i2c/tda998x_drv.c #define REG_VIP_CNTRL_5 REG(0x00, 0x25) /* write */ REG 174 drivers/gpu/drm/i2c/tda998x_drv.c #define REG_MUX_AP REG(0x00, 0x26) /* read/write */ REG 177 drivers/gpu/drm/i2c/tda998x_drv.c #define REG_MUX_VP_VIP_OUT REG(0x00, 0x27) /* read/write */ REG 178 drivers/gpu/drm/i2c/tda998x_drv.c #define REG_MAT_CONTRL REG(0x00, 0x80) /* write */ REG 181 drivers/gpu/drm/i2c/tda998x_drv.c #define REG_VIDFORMAT REG(0x00, 0xa0) /* write */ REG 182 drivers/gpu/drm/i2c/tda998x_drv.c #define REG_REFPIX_MSB REG(0x00, 0xa1) /* write */ REG 183 drivers/gpu/drm/i2c/tda998x_drv.c #define REG_REFPIX_LSB REG(0x00, 0xa2) /* write */ REG 184 drivers/gpu/drm/i2c/tda998x_drv.c #define REG_REFLINE_MSB REG(0x00, 0xa3) /* write */ REG 185 drivers/gpu/drm/i2c/tda998x_drv.c #define REG_REFLINE_LSB REG(0x00, 0xa4) /* write */ REG 186 drivers/gpu/drm/i2c/tda998x_drv.c #define REG_NPIX_MSB REG(0x00, 0xa5) /* write */ REG 187 drivers/gpu/drm/i2c/tda998x_drv.c #define REG_NPIX_LSB REG(0x00, 0xa6) /* write */ REG 188 drivers/gpu/drm/i2c/tda998x_drv.c #define REG_NLINE_MSB REG(0x00, 0xa7) /* write */ REG 189 drivers/gpu/drm/i2c/tda998x_drv.c #define REG_NLINE_LSB REG(0x00, 0xa8) /* write */ REG 190 drivers/gpu/drm/i2c/tda998x_drv.c #define REG_VS_LINE_STRT_1_MSB REG(0x00, 0xa9) /* write */ REG 191 drivers/gpu/drm/i2c/tda998x_drv.c #define REG_VS_LINE_STRT_1_LSB REG(0x00, 0xaa) /* write */ REG 192 drivers/gpu/drm/i2c/tda998x_drv.c #define REG_VS_PIX_STRT_1_MSB REG(0x00, 0xab) /* write */ REG 193 drivers/gpu/drm/i2c/tda998x_drv.c #define REG_VS_PIX_STRT_1_LSB REG(0x00, 0xac) /* write */ REG 194 drivers/gpu/drm/i2c/tda998x_drv.c #define REG_VS_LINE_END_1_MSB REG(0x00, 0xad) /* write */ REG 195 drivers/gpu/drm/i2c/tda998x_drv.c #define REG_VS_LINE_END_1_LSB REG(0x00, 0xae) /* write */ REG 196 drivers/gpu/drm/i2c/tda998x_drv.c #define REG_VS_PIX_END_1_MSB REG(0x00, 0xaf) /* write */ REG 197 drivers/gpu/drm/i2c/tda998x_drv.c #define REG_VS_PIX_END_1_LSB REG(0x00, 0xb0) /* write */ REG 198 drivers/gpu/drm/i2c/tda998x_drv.c #define REG_VS_LINE_STRT_2_MSB REG(0x00, 0xb1) /* write */ REG 199 drivers/gpu/drm/i2c/tda998x_drv.c #define REG_VS_LINE_STRT_2_LSB REG(0x00, 0xb2) /* write */ REG 200 drivers/gpu/drm/i2c/tda998x_drv.c #define REG_VS_PIX_STRT_2_MSB REG(0x00, 0xb3) /* write */ REG 201 drivers/gpu/drm/i2c/tda998x_drv.c #define REG_VS_PIX_STRT_2_LSB REG(0x00, 0xb4) /* write */ REG 202 drivers/gpu/drm/i2c/tda998x_drv.c #define REG_VS_LINE_END_2_MSB REG(0x00, 0xb5) /* write */ REG 203 drivers/gpu/drm/i2c/tda998x_drv.c #define REG_VS_LINE_END_2_LSB REG(0x00, 0xb6) /* write */ REG 204 drivers/gpu/drm/i2c/tda998x_drv.c #define REG_VS_PIX_END_2_MSB REG(0x00, 0xb7) /* write */ REG 205 drivers/gpu/drm/i2c/tda998x_drv.c #define REG_VS_PIX_END_2_LSB REG(0x00, 0xb8) /* write */ REG 206 drivers/gpu/drm/i2c/tda998x_drv.c #define REG_HS_PIX_START_MSB REG(0x00, 0xb9) /* write */ REG 207 drivers/gpu/drm/i2c/tda998x_drv.c #define REG_HS_PIX_START_LSB REG(0x00, 0xba) /* write */ REG 208 drivers/gpu/drm/i2c/tda998x_drv.c #define REG_HS_PIX_STOP_MSB REG(0x00, 0xbb) /* write */ REG 209 drivers/gpu/drm/i2c/tda998x_drv.c #define REG_HS_PIX_STOP_LSB REG(0x00, 0xbc) /* write */ REG 210 drivers/gpu/drm/i2c/tda998x_drv.c #define REG_VWIN_START_1_MSB REG(0x00, 0xbd) /* write */ REG 211 drivers/gpu/drm/i2c/tda998x_drv.c #define REG_VWIN_START_1_LSB REG(0x00, 0xbe) /* write */ REG 212 drivers/gpu/drm/i2c/tda998x_drv.c #define REG_VWIN_END_1_MSB REG(0x00, 0xbf) /* write */ REG 213 drivers/gpu/drm/i2c/tda998x_drv.c #define REG_VWIN_END_1_LSB REG(0x00, 0xc0) /* write */ REG 214 drivers/gpu/drm/i2c/tda998x_drv.c #define REG_VWIN_START_2_MSB REG(0x00, 0xc1) /* write */ REG 215 drivers/gpu/drm/i2c/tda998x_drv.c #define REG_VWIN_START_2_LSB REG(0x00, 0xc2) /* write */ REG 216 drivers/gpu/drm/i2c/tda998x_drv.c #define REG_VWIN_END_2_MSB REG(0x00, 0xc3) /* write */ REG 217 drivers/gpu/drm/i2c/tda998x_drv.c #define REG_VWIN_END_2_LSB REG(0x00, 0xc4) /* write */ REG 218 drivers/gpu/drm/i2c/tda998x_drv.c #define REG_DE_START_MSB REG(0x00, 0xc5) /* write */ REG 219 drivers/gpu/drm/i2c/tda998x_drv.c #define REG_DE_START_LSB REG(0x00, 0xc6) /* write */ REG 220 drivers/gpu/drm/i2c/tda998x_drv.c #define REG_DE_STOP_MSB REG(0x00, 0xc7) /* write */ REG 221 drivers/gpu/drm/i2c/tda998x_drv.c #define REG_DE_STOP_LSB REG(0x00, 0xc8) /* write */ REG 222 drivers/gpu/drm/i2c/tda998x_drv.c #define REG_TBG_CNTRL_0 REG(0x00, 0xca) /* write */ REG 230 drivers/gpu/drm/i2c/tda998x_drv.c #define REG_TBG_CNTRL_1 REG(0x00, 0xcb) /* write */ REG 238 drivers/gpu/drm/i2c/tda998x_drv.c #define REG_ENABLE_SPACE REG(0x00, 0xd6) /* write */ REG 239 drivers/gpu/drm/i2c/tda998x_drv.c #define REG_HVF_CNTRL_0 REG(0x00, 0xe4) /* write */ REG 244 drivers/gpu/drm/i2c/tda998x_drv.c #define REG_HVF_CNTRL_1 REG(0x00, 0xe5) /* write */ REG 250 drivers/gpu/drm/i2c/tda998x_drv.c #define REG_RPT_CNTRL REG(0x00, 0xf0) /* write */ REG 252 drivers/gpu/drm/i2c/tda998x_drv.c #define REG_I2S_FORMAT REG(0x00, 0xfc) /* read/write */ REG 256 drivers/gpu/drm/i2c/tda998x_drv.c #define REG_AIP_CLKSEL REG(0x00, 0xfd) /* write */ REG 264 drivers/gpu/drm/i2c/tda998x_drv.c #define REG_PLL_SERIAL_1 REG(0x02, 0x00) /* read/write */ REG 268 drivers/gpu/drm/i2c/tda998x_drv.c #define REG_PLL_SERIAL_2 REG(0x02, 0x01) /* read/write */ REG 271 drivers/gpu/drm/i2c/tda998x_drv.c #define REG_PLL_SERIAL_3 REG(0x02, 0x02) /* read/write */ REG 275 drivers/gpu/drm/i2c/tda998x_drv.c #define REG_SERIALIZER REG(0x02, 0x03) /* read/write */ REG 276 drivers/gpu/drm/i2c/tda998x_drv.c #define REG_BUFFER_OUT REG(0x02, 0x04) /* read/write */ REG 277 drivers/gpu/drm/i2c/tda998x_drv.c #define REG_PLL_SCG1 REG(0x02, 0x05) /* read/write */ REG 278 drivers/gpu/drm/i2c/tda998x_drv.c #define REG_PLL_SCG2 REG(0x02, 0x06) /* read/write */ REG 279 drivers/gpu/drm/i2c/tda998x_drv.c #define REG_PLL_SCGN1 REG(0x02, 0x07) /* read/write */ REG 280 drivers/gpu/drm/i2c/tda998x_drv.c #define REG_PLL_SCGN2 REG(0x02, 0x08) /* read/write */ REG 281 drivers/gpu/drm/i2c/tda998x_drv.c #define REG_PLL_SCGR1 REG(0x02, 0x09) /* read/write */ REG 282 drivers/gpu/drm/i2c/tda998x_drv.c #define REG_PLL_SCGR2 REG(0x02, 0x0a) /* read/write */ REG 283 drivers/gpu/drm/i2c/tda998x_drv.c #define REG_AUDIO_DIV REG(0x02, 0x0e) /* read/write */ REG 290 drivers/gpu/drm/i2c/tda998x_drv.c #define REG_SEL_CLK REG(0x02, 0x11) /* read/write */ REG 294 drivers/gpu/drm/i2c/tda998x_drv.c #define REG_ANA_GENERAL REG(0x02, 0x12) /* read/write */ REG 298 drivers/gpu/drm/i2c/tda998x_drv.c #define REG_EDID_DATA_0 REG(0x09, 0x00) /* read */ REG 300 drivers/gpu/drm/i2c/tda998x_drv.c #define REG_EDID_CTRL REG(0x09, 0xfa) /* read/write */ REG 301 drivers/gpu/drm/i2c/tda998x_drv.c #define REG_DDC_ADDR REG(0x09, 0xfb) /* read/write */ REG 302 drivers/gpu/drm/i2c/tda998x_drv.c #define REG_DDC_OFFS REG(0x09, 0xfc) /* read/write */ REG 303 drivers/gpu/drm/i2c/tda998x_drv.c #define REG_DDC_SEGM_ADDR REG(0x09, 0xfd) /* read/write */ REG 304 drivers/gpu/drm/i2c/tda998x_drv.c #define REG_DDC_SEGM REG(0x09, 0xfe) /* read/write */ REG 308 drivers/gpu/drm/i2c/tda998x_drv.c #define REG_IF1_HB0 REG(0x10, 0x20) /* read/write */ REG 309 drivers/gpu/drm/i2c/tda998x_drv.c #define REG_IF2_HB0 REG(0x10, 0x40) /* read/write */ REG 310 drivers/gpu/drm/i2c/tda998x_drv.c #define REG_IF3_HB0 REG(0x10, 0x60) /* read/write */ REG 311 drivers/gpu/drm/i2c/tda998x_drv.c #define REG_IF4_HB0 REG(0x10, 0x80) /* read/write */ REG 312 drivers/gpu/drm/i2c/tda998x_drv.c #define REG_IF5_HB0 REG(0x10, 0xa0) /* read/write */ REG 316 drivers/gpu/drm/i2c/tda998x_drv.c #define REG_AIP_CNTRL_0 REG(0x11, 0x00) /* read/write */ REG 322 drivers/gpu/drm/i2c/tda998x_drv.c #define REG_CA_I2S REG(0x11, 0x01) /* read/write */ REG 325 drivers/gpu/drm/i2c/tda998x_drv.c #define REG_LATENCY_RD REG(0x11, 0x04) /* read/write */ REG 326 drivers/gpu/drm/i2c/tda998x_drv.c #define REG_ACR_CTS_0 REG(0x11, 0x05) /* read/write */ REG 327 drivers/gpu/drm/i2c/tda998x_drv.c #define REG_ACR_CTS_1 REG(0x11, 0x06) /* read/write */ REG 328 drivers/gpu/drm/i2c/tda998x_drv.c #define REG_ACR_CTS_2 REG(0x11, 0x07) /* read/write */ REG 329 drivers/gpu/drm/i2c/tda998x_drv.c #define REG_ACR_N_0 REG(0x11, 0x08) /* read/write */ REG 330 drivers/gpu/drm/i2c/tda998x_drv.c #define REG_ACR_N_1 REG(0x11, 0x09) /* read/write */ REG 331 drivers/gpu/drm/i2c/tda998x_drv.c #define REG_ACR_N_2 REG(0x11, 0x0a) /* read/write */ REG 332 drivers/gpu/drm/i2c/tda998x_drv.c #define REG_CTS_N REG(0x11, 0x0c) /* read/write */ REG 335 drivers/gpu/drm/i2c/tda998x_drv.c #define REG_ENC_CNTRL REG(0x11, 0x0d) /* read/write */ REG 339 drivers/gpu/drm/i2c/tda998x_drv.c #define REG_DIP_FLAGS REG(0x11, 0x0e) /* read/write */ REG 342 drivers/gpu/drm/i2c/tda998x_drv.c #define REG_DIP_IF_FLAGS REG(0x11, 0x0f) /* read/write */ REG 348 drivers/gpu/drm/i2c/tda998x_drv.c #define REG_CH_STAT_B(x) REG(0x11, 0x14 + (x)) /* read/write */ REG 352 drivers/gpu/drm/i2c/tda998x_drv.c #define REG_TX3 REG(0x12, 0x9a) /* read/write */ REG 353 drivers/gpu/drm/i2c/tda998x_drv.c #define REG_TX4 REG(0x12, 0x9b) /* read/write */ REG 355 drivers/gpu/drm/i2c/tda998x_drv.c #define REG_TX33 REG(0x12, 0xb8) /* read/write */ REG 74 drivers/gpu/drm/panel/panel-novatek-nt39016.c #define RV(REG, VAL) { .reg = (REG), .def = (VAL), .delay_us = 2 } REG 428 drivers/gpu/drm/tilcdc/tilcdc_drv.c REG(1, false, LCDC_PID_REG), REG 429 drivers/gpu/drm/tilcdc/tilcdc_drv.c REG(1, true, LCDC_CTRL_REG), REG 430 drivers/gpu/drm/tilcdc/tilcdc_drv.c REG(1, false, LCDC_STAT_REG), REG 431 drivers/gpu/drm/tilcdc/tilcdc_drv.c REG(1, true, LCDC_RASTER_CTRL_REG), REG 432 drivers/gpu/drm/tilcdc/tilcdc_drv.c REG(1, true, LCDC_RASTER_TIMING_0_REG), REG 433 drivers/gpu/drm/tilcdc/tilcdc_drv.c REG(1, true, LCDC_RASTER_TIMING_1_REG), REG 434 drivers/gpu/drm/tilcdc/tilcdc_drv.c REG(1, true, LCDC_RASTER_TIMING_2_REG), REG 435 drivers/gpu/drm/tilcdc/tilcdc_drv.c REG(1, true, LCDC_DMA_CTRL_REG), REG 436 drivers/gpu/drm/tilcdc/tilcdc_drv.c REG(1, true, LCDC_DMA_FB_BASE_ADDR_0_REG), REG 437 drivers/gpu/drm/tilcdc/tilcdc_drv.c REG(1, true, LCDC_DMA_FB_CEILING_ADDR_0_REG), REG 438 drivers/gpu/drm/tilcdc/tilcdc_drv.c REG(1, true, LCDC_DMA_FB_BASE_ADDR_1_REG), REG 439 drivers/gpu/drm/tilcdc/tilcdc_drv.c REG(1, true, LCDC_DMA_FB_CEILING_ADDR_1_REG), REG 441 drivers/gpu/drm/tilcdc/tilcdc_drv.c REG(2, false, LCDC_RAW_STAT_REG), REG 442 drivers/gpu/drm/tilcdc/tilcdc_drv.c REG(2, false, LCDC_MASKED_STAT_REG), REG 443 drivers/gpu/drm/tilcdc/tilcdc_drv.c REG(2, true, LCDC_INT_ENABLE_SET_REG), REG 444 drivers/gpu/drm/tilcdc/tilcdc_drv.c REG(2, false, LCDC_INT_ENABLE_CLR_REG), REG 445 drivers/gpu/drm/tilcdc/tilcdc_drv.c REG(2, false, LCDC_END_OF_INT_IND_REG), REG 446 drivers/gpu/drm/tilcdc/tilcdc_drv.c REG(2, true, LCDC_CLK_ENABLE_REG), REG 248 drivers/hwmon/asb100.c #define set_in_reg(REG, reg) \ REG 261 drivers/hwmon/asb100.c asb100_write_value(client, ASB100_REG_IN_##REG(nr), \ REG 430 drivers/hwmon/asb100.c #define set_temp_reg(REG, reg) \ REG 450 drivers/hwmon/asb100.c asb100_write_value(client, ASB100_REG_TEMP_##REG(nr+1), \ REG 46 drivers/hwmon/smsc47b397.c outb(reg, REG); REG 52 drivers/hwmon/smsc47b397.c outb(reg, REG); REG 64 drivers/hwmon/smsc47b397.c if (!request_muxed_region(REG, 2, DRVNAME)) REG 67 drivers/hwmon/smsc47b397.c outb(0x55, REG); REG 73 drivers/hwmon/smsc47b397.c outb(0xAA, REG); REG 74 drivers/hwmon/smsc47b397.c release_region(REG, 2); REG 49 drivers/hwmon/smsc47m1.c outb(reg, REG); REG 56 drivers/hwmon/smsc47m1.c outb(reg, REG); REG 66 drivers/hwmon/smsc47m1.c if (!request_muxed_region(REG, 2, DRVNAME)) REG 69 drivers/hwmon/smsc47m1.c outb(0x55, REG); REG 76 drivers/hwmon/smsc47m1.c outb(0xAA, REG); REG 77 drivers/hwmon/smsc47m1.c release_region(REG, 2); REG 945 drivers/hwmon/w83627ehf.c #define store_in_reg(REG, reg) \ REG 961 drivers/hwmon/w83627ehf.c w83627ehf_write_value(data, W83627EHF_REG_IN_##REG(nr), \ REG 1611 drivers/hwmon/w83627ehf.c #define fan_functions(reg, REG) \ REG 1637 drivers/hwmon/w83627ehf.c w83627ehf_write_value(data, data->REG_##REG[nr], val); \ REG 1647 drivers/hwmon/w83627ehf.c #define fan_time_functions(reg, REG) \ REG 1676 drivers/hwmon/w83627ehf.c w83627ehf_write_value(data, data->REG_##REG[nr], val); \ REG 259 drivers/hwmon/w83781d.c #define store_in_reg(REG, reg) \ REG 272 drivers/hwmon/w83781d.c w83781d_write_value(data, W83781D_REG_IN_##REG(nr), \ REG 364 drivers/hwmon/w83781d.c #define store_temp_reg(REG, reg) \ REG 379 drivers/hwmon/w83781d.c w83781d_write_value(data, W83781D_REG_TEMP_##REG(nr), \ REG 383 drivers/hwmon/w83781d.c w83781d_write_value(data, W83781D_REG_TEMP_##REG(nr), \ REG 368 drivers/hwmon/w83791d.c #define store_in_reg(REG, reg) \ REG 384 drivers/hwmon/w83791d.c w83791d_write(client, W83791D_REG_IN_##REG[nr], data->in_##reg[nr]); \ REG 368 drivers/hwmon/w83792d.c #define store_in_reg(REG, reg) \ REG 384 drivers/hwmon/w83792d.c w83792d_write_value(client, W83792D_REG_IN_##REG[nr], \ REG 236 drivers/hwmon/w83l786ng.c #define store_in_reg(REG, reg) \ REG 250 drivers/hwmon/w83l786ng.c w83l786ng_write_value(client, W83L786NG_REG_IN_##REG(nr), \ REG 72 drivers/iio/magnetometer/mmc35240.c #define MMC35240_OTP_CONVERT_Y(REG) (((REG) >= 32 ? (32 - (REG)) : (REG)) * 6) REG 75 drivers/iio/magnetometer/mmc35240.c #define MMC35240_OTP_CONVERT_Z(REG) (((REG) >= 32 ? (32 - (REG)) : (REG)) * 81) REG 243 drivers/media/dvb-frontends/stb0899_priv.h #define STB0899_READ_S2REG(DEVICE, REG) (_stb0899_read_s2reg(state, DEVICE, STB0899_BASE_##REG, STB0899_OFF0_##REG)) REG 514 drivers/media/tuners/tda18250.c [REG] = { 0x22, 0x23, 0x24, 0x21, 0x0d, 0x0c, 0x0f, 0x14, REG 586 drivers/media/tuners/tda18250.c ret = regmap_write_bits(dev->regmap, delsys_params[REG][i], REG 1858 drivers/mmc/host/vub300.c u32 reg = REG(cmd); REG 12 drivers/net/ethernet/apple/mace.h REG(rcvfifo); /* receive FIFO */ REG 13 drivers/net/ethernet/apple/mace.h REG(xmtfifo); /* transmit FIFO */ REG 14 drivers/net/ethernet/apple/mace.h REG(xmtfc); /* transmit frame control */ REG 15 drivers/net/ethernet/apple/mace.h REG(xmtfs); /* transmit frame status */ REG 16 drivers/net/ethernet/apple/mace.h REG(xmtrc); /* transmit retry count */ REG 17 drivers/net/ethernet/apple/mace.h REG(rcvfc); /* receive frame control */ REG 18 drivers/net/ethernet/apple/mace.h REG(rcvfs); /* receive frame status (4 bytes) */ REG 19 drivers/net/ethernet/apple/mace.h REG(fifofc); /* FIFO frame count */ REG 20 drivers/net/ethernet/apple/mace.h REG(ir); /* interrupt register */ REG 21 drivers/net/ethernet/apple/mace.h REG(imr); /* interrupt mask register */ REG 22 drivers/net/ethernet/apple/mace.h REG(pr); /* poll register */ REG 23 drivers/net/ethernet/apple/mace.h REG(biucc); /* bus interface unit config control */ REG 24 drivers/net/ethernet/apple/mace.h REG(fifocc); /* FIFO configuration control */ REG 25 drivers/net/ethernet/apple/mace.h REG(maccc); /* medium access control config control */ REG 26 drivers/net/ethernet/apple/mace.h REG(plscc); /* phys layer signalling config control */ REG 27 drivers/net/ethernet/apple/mace.h REG(phycc); /* physical configuration control */ REG 28 drivers/net/ethernet/apple/mace.h REG(chipid_lo); /* chip ID, lsb */ REG 29 drivers/net/ethernet/apple/mace.h REG(chipid_hi); /* chip ID, msb */ REG 30 drivers/net/ethernet/apple/mace.h REG(iac); /* internal address config */ REG 31 drivers/net/ethernet/apple/mace.h REG(reg19); REG 32 drivers/net/ethernet/apple/mace.h REG(ladrf); /* logical address filter (8 bytes) */ REG 33 drivers/net/ethernet/apple/mace.h REG(padr); /* physical address (6 bytes) */ REG 34 drivers/net/ethernet/apple/mace.h REG(reg22); REG 35 drivers/net/ethernet/apple/mace.h REG(reg23); REG 36 drivers/net/ethernet/apple/mace.h REG(mpc); /* missed packet count (clears when read) */ REG 37 drivers/net/ethernet/apple/mace.h REG(reg25); REG 38 drivers/net/ethernet/apple/mace.h REG(rntpc); /* runt packet count (clears when read) */ REG 39 drivers/net/ethernet/apple/mace.h REG(rcvcc); /* recv collision count (clears when read) */ REG 40 drivers/net/ethernet/apple/mace.h REG(reg28); REG 41 drivers/net/ethernet/apple/mace.h REG(utr); /* user test reg */ REG 42 drivers/net/ethernet/apple/mace.h REG(reg30); REG 43 drivers/net/ethernet/apple/mace.h REG(reg31); REG 10894 drivers/net/ethernet/broadcom/tg3.c #define TG3_STAT_ADD32(PSTAT, REG) \ REG 10895 drivers/net/ethernet/broadcom/tg3.c do { u32 __val = tr32(REG); \ REG 73 drivers/net/ethernet/freescale/fs_enet/mac-fcc.c #define mk_mii_read(REG) (0x60020000 | ((REG & 0x1f) << 18)) REG 74 drivers/net/ethernet/freescale/fs_enet/mac-fcc.c #define mk_mii_write(REG, VAL) (0x50020000 | ((REG & 0x1f) << 18) | (VAL & 0xffff)) REG 46 drivers/net/ethernet/freescale/fs_enet/mii-fec.c #define mk_mii_read(REG) (0x60020000 | ((REG & 0x1f) << 18)) REG 47 drivers/net/ethernet/freescale/fs_enet/mii-fec.c #define mk_mii_write(REG, VAL) (0x50020000 | ((REG & 0x1f) << 18) | (VAL & 0xffff)) REG 11 drivers/net/ethernet/mscc/ocelot_regs.c REG(ANA_ADVLEARN, 0x009000), REG 12 drivers/net/ethernet/mscc/ocelot_regs.c REG(ANA_VLANMASK, 0x009004), REG 13 drivers/net/ethernet/mscc/ocelot_regs.c REG(ANA_PORT_B_DOMAIN, 0x009008), REG 14 drivers/net/ethernet/mscc/ocelot_regs.c REG(ANA_ANAGEFIL, 0x00900c), REG 15 drivers/net/ethernet/mscc/ocelot_regs.c REG(ANA_ANEVENTS, 0x009010), REG 16 drivers/net/ethernet/mscc/ocelot_regs.c REG(ANA_STORMLIMIT_BURST, 0x009014), REG 17 drivers/net/ethernet/mscc/ocelot_regs.c REG(ANA_STORMLIMIT_CFG, 0x009018), REG 18 drivers/net/ethernet/mscc/ocelot_regs.c REG(ANA_ISOLATED_PORTS, 0x009028), REG 19 drivers/net/ethernet/mscc/ocelot_regs.c REG(ANA_COMMUNITY_PORTS, 0x00902c), REG 20 drivers/net/ethernet/mscc/ocelot_regs.c REG(ANA_AUTOAGE, 0x009030), REG 21 drivers/net/ethernet/mscc/ocelot_regs.c REG(ANA_MACTOPTIONS, 0x009034), REG 22 drivers/net/ethernet/mscc/ocelot_regs.c REG(ANA_LEARNDISC, 0x009038), REG 23 drivers/net/ethernet/mscc/ocelot_regs.c REG(ANA_AGENCTRL, 0x00903c), REG 24 drivers/net/ethernet/mscc/ocelot_regs.c REG(ANA_MIRRORPORTS, 0x009040), REG 25 drivers/net/ethernet/mscc/ocelot_regs.c REG(ANA_EMIRRORPORTS, 0x009044), REG 26 drivers/net/ethernet/mscc/ocelot_regs.c REG(ANA_FLOODING, 0x009048), REG 27 drivers/net/ethernet/mscc/ocelot_regs.c REG(ANA_FLOODING_IPMC, 0x00904c), REG 28 drivers/net/ethernet/mscc/ocelot_regs.c REG(ANA_SFLOW_CFG, 0x009050), REG 29 drivers/net/ethernet/mscc/ocelot_regs.c REG(ANA_PORT_MODE, 0x009080), REG 30 drivers/net/ethernet/mscc/ocelot_regs.c REG(ANA_PGID_PGID, 0x008c00), REG 31 drivers/net/ethernet/mscc/ocelot_regs.c REG(ANA_TABLES_ANMOVED, 0x008b30), REG 32 drivers/net/ethernet/mscc/ocelot_regs.c REG(ANA_TABLES_MACHDATA, 0x008b34), REG 33 drivers/net/ethernet/mscc/ocelot_regs.c REG(ANA_TABLES_MACLDATA, 0x008b38), REG 34 drivers/net/ethernet/mscc/ocelot_regs.c REG(ANA_TABLES_MACACCESS, 0x008b3c), REG 35 drivers/net/ethernet/mscc/ocelot_regs.c REG(ANA_TABLES_MACTINDX, 0x008b40), REG 36 drivers/net/ethernet/mscc/ocelot_regs.c REG(ANA_TABLES_VLANACCESS, 0x008b44), REG 37 drivers/net/ethernet/mscc/ocelot_regs.c REG(ANA_TABLES_VLANTIDX, 0x008b48), REG 38 drivers/net/ethernet/mscc/ocelot_regs.c REG(ANA_TABLES_ISDXACCESS, 0x008b4c), REG 39 drivers/net/ethernet/mscc/ocelot_regs.c REG(ANA_TABLES_ISDXTIDX, 0x008b50), REG 40 drivers/net/ethernet/mscc/ocelot_regs.c REG(ANA_TABLES_ENTRYLIM, 0x008b00), REG 41 drivers/net/ethernet/mscc/ocelot_regs.c REG(ANA_TABLES_PTP_ID_HIGH, 0x008b54), REG 42 drivers/net/ethernet/mscc/ocelot_regs.c REG(ANA_TABLES_PTP_ID_LOW, 0x008b58), REG 43 drivers/net/ethernet/mscc/ocelot_regs.c REG(ANA_MSTI_STATE, 0x008e00), REG 44 drivers/net/ethernet/mscc/ocelot_regs.c REG(ANA_PORT_VLAN_CFG, 0x007000), REG 45 drivers/net/ethernet/mscc/ocelot_regs.c REG(ANA_PORT_DROP_CFG, 0x007004), REG 46 drivers/net/ethernet/mscc/ocelot_regs.c REG(ANA_PORT_QOS_CFG, 0x007008), REG 47 drivers/net/ethernet/mscc/ocelot_regs.c REG(ANA_PORT_VCAP_CFG, 0x00700c), REG 48 drivers/net/ethernet/mscc/ocelot_regs.c REG(ANA_PORT_VCAP_S1_KEY_CFG, 0x007010), REG 49 drivers/net/ethernet/mscc/ocelot_regs.c REG(ANA_PORT_VCAP_S2_CFG, 0x00701c), REG 50 drivers/net/ethernet/mscc/ocelot_regs.c REG(ANA_PORT_PCP_DEI_MAP, 0x007020), REG 51 drivers/net/ethernet/mscc/ocelot_regs.c REG(ANA_PORT_CPU_FWD_CFG, 0x007060), REG 52 drivers/net/ethernet/mscc/ocelot_regs.c REG(ANA_PORT_CPU_FWD_BPDU_CFG, 0x007064), REG 53 drivers/net/ethernet/mscc/ocelot_regs.c REG(ANA_PORT_CPU_FWD_GARP_CFG, 0x007068), REG 54 drivers/net/ethernet/mscc/ocelot_regs.c REG(ANA_PORT_CPU_FWD_CCM_CFG, 0x00706c), REG 55 drivers/net/ethernet/mscc/ocelot_regs.c REG(ANA_PORT_PORT_CFG, 0x007070), REG 56 drivers/net/ethernet/mscc/ocelot_regs.c REG(ANA_PORT_POL_CFG, 0x007074), REG 57 drivers/net/ethernet/mscc/ocelot_regs.c REG(ANA_PORT_PTP_CFG, 0x007078), REG 58 drivers/net/ethernet/mscc/ocelot_regs.c REG(ANA_PORT_PTP_DLY1_CFG, 0x00707c), REG 59 drivers/net/ethernet/mscc/ocelot_regs.c REG(ANA_OAM_UPM_LM_CNT, 0x007c00), REG 60 drivers/net/ethernet/mscc/ocelot_regs.c REG(ANA_PORT_PTP_DLY2_CFG, 0x007080), REG 61 drivers/net/ethernet/mscc/ocelot_regs.c REG(ANA_PFC_PFC_CFG, 0x008800), REG 62 drivers/net/ethernet/mscc/ocelot_regs.c REG(ANA_PFC_PFC_TIMER, 0x008804), REG 63 drivers/net/ethernet/mscc/ocelot_regs.c REG(ANA_IPT_OAM_MEP_CFG, 0x008000), REG 64 drivers/net/ethernet/mscc/ocelot_regs.c REG(ANA_IPT_IPT, 0x008004), REG 65 drivers/net/ethernet/mscc/ocelot_regs.c REG(ANA_PPT_PPT, 0x008ac0), REG 66 drivers/net/ethernet/mscc/ocelot_regs.c REG(ANA_FID_MAP_FID_MAP, 0x000000), REG 67 drivers/net/ethernet/mscc/ocelot_regs.c REG(ANA_AGGR_CFG, 0x0090b4), REG 68 drivers/net/ethernet/mscc/ocelot_regs.c REG(ANA_CPUQ_CFG, 0x0090b8), REG 69 drivers/net/ethernet/mscc/ocelot_regs.c REG(ANA_CPUQ_CFG2, 0x0090bc), REG 70 drivers/net/ethernet/mscc/ocelot_regs.c REG(ANA_CPUQ_8021_CFG, 0x0090c0), REG 71 drivers/net/ethernet/mscc/ocelot_regs.c REG(ANA_DSCP_CFG, 0x009100), REG 72 drivers/net/ethernet/mscc/ocelot_regs.c REG(ANA_DSCP_REWR_CFG, 0x009200), REG 73 drivers/net/ethernet/mscc/ocelot_regs.c REG(ANA_VCAP_RNG_TYPE_CFG, 0x009240), REG 74 drivers/net/ethernet/mscc/ocelot_regs.c REG(ANA_VCAP_RNG_VAL_CFG, 0x009260), REG 75 drivers/net/ethernet/mscc/ocelot_regs.c REG(ANA_VRAP_CFG, 0x009280), REG 76 drivers/net/ethernet/mscc/ocelot_regs.c REG(ANA_VRAP_HDR_DATA, 0x009284), REG 77 drivers/net/ethernet/mscc/ocelot_regs.c REG(ANA_VRAP_HDR_MASK, 0x009288), REG 78 drivers/net/ethernet/mscc/ocelot_regs.c REG(ANA_DISCARD_CFG, 0x00928c), REG 79 drivers/net/ethernet/mscc/ocelot_regs.c REG(ANA_FID_CFG, 0x009290), REG 80 drivers/net/ethernet/mscc/ocelot_regs.c REG(ANA_POL_PIR_CFG, 0x004000), REG 81 drivers/net/ethernet/mscc/ocelot_regs.c REG(ANA_POL_CIR_CFG, 0x004004), REG 82 drivers/net/ethernet/mscc/ocelot_regs.c REG(ANA_POL_MODE_CFG, 0x004008), REG 83 drivers/net/ethernet/mscc/ocelot_regs.c REG(ANA_POL_PIR_STATE, 0x00400c), REG 84 drivers/net/ethernet/mscc/ocelot_regs.c REG(ANA_POL_CIR_STATE, 0x004010), REG 85 drivers/net/ethernet/mscc/ocelot_regs.c REG(ANA_POL_STATE, 0x004014), REG 86 drivers/net/ethernet/mscc/ocelot_regs.c REG(ANA_POL_FLOWC, 0x008b80), REG 87 drivers/net/ethernet/mscc/ocelot_regs.c REG(ANA_POL_HYST, 0x008bec), REG 88 drivers/net/ethernet/mscc/ocelot_regs.c REG(ANA_POL_MISC_CFG, 0x008bf0), REG 92 drivers/net/ethernet/mscc/ocelot_regs.c REG(QS_XTR_GRP_CFG, 0x000000), REG 93 drivers/net/ethernet/mscc/ocelot_regs.c REG(QS_XTR_RD, 0x000008), REG 94 drivers/net/ethernet/mscc/ocelot_regs.c REG(QS_XTR_FRM_PRUNING, 0x000010), REG 95 drivers/net/ethernet/mscc/ocelot_regs.c REG(QS_XTR_FLUSH, 0x000018), REG 96 drivers/net/ethernet/mscc/ocelot_regs.c REG(QS_XTR_DATA_PRESENT, 0x00001c), REG 97 drivers/net/ethernet/mscc/ocelot_regs.c REG(QS_XTR_CFG, 0x000020), REG 98 drivers/net/ethernet/mscc/ocelot_regs.c REG(QS_INJ_GRP_CFG, 0x000024), REG 99 drivers/net/ethernet/mscc/ocelot_regs.c REG(QS_INJ_WR, 0x00002c), REG 100 drivers/net/ethernet/mscc/ocelot_regs.c REG(QS_INJ_CTRL, 0x000034), REG 101 drivers/net/ethernet/mscc/ocelot_regs.c REG(QS_INJ_STATUS, 0x00003c), REG 102 drivers/net/ethernet/mscc/ocelot_regs.c REG(QS_INJ_ERR, 0x000040), REG 103 drivers/net/ethernet/mscc/ocelot_regs.c REG(QS_INH_DBG, 0x000048), REG 107 drivers/net/ethernet/mscc/ocelot_regs.c REG(QSYS_PORT_MODE, 0x011200), REG 108 drivers/net/ethernet/mscc/ocelot_regs.c REG(QSYS_SWITCH_PORT_MODE, 0x011234), REG 109 drivers/net/ethernet/mscc/ocelot_regs.c REG(QSYS_STAT_CNT_CFG, 0x011264), REG 110 drivers/net/ethernet/mscc/ocelot_regs.c REG(QSYS_EEE_CFG, 0x011268), REG 111 drivers/net/ethernet/mscc/ocelot_regs.c REG(QSYS_EEE_THRES, 0x011294), REG 112 drivers/net/ethernet/mscc/ocelot_regs.c REG(QSYS_IGR_NO_SHARING, 0x011298), REG 113 drivers/net/ethernet/mscc/ocelot_regs.c REG(QSYS_EGR_NO_SHARING, 0x01129c), REG 114 drivers/net/ethernet/mscc/ocelot_regs.c REG(QSYS_SW_STATUS, 0x0112a0), REG 115 drivers/net/ethernet/mscc/ocelot_regs.c REG(QSYS_EXT_CPU_CFG, 0x0112d0), REG 116 drivers/net/ethernet/mscc/ocelot_regs.c REG(QSYS_PAD_CFG, 0x0112d4), REG 117 drivers/net/ethernet/mscc/ocelot_regs.c REG(QSYS_CPU_GROUP_MAP, 0x0112d8), REG 118 drivers/net/ethernet/mscc/ocelot_regs.c REG(QSYS_QMAP, 0x0112dc), REG 119 drivers/net/ethernet/mscc/ocelot_regs.c REG(QSYS_ISDX_SGRP, 0x011400), REG 120 drivers/net/ethernet/mscc/ocelot_regs.c REG(QSYS_TIMED_FRAME_ENTRY, 0x014000), REG 121 drivers/net/ethernet/mscc/ocelot_regs.c REG(QSYS_TFRM_MISC, 0x011310), REG 122 drivers/net/ethernet/mscc/ocelot_regs.c REG(QSYS_TFRM_PORT_DLY, 0x011314), REG 123 drivers/net/ethernet/mscc/ocelot_regs.c REG(QSYS_TFRM_TIMER_CFG_1, 0x011318), REG 124 drivers/net/ethernet/mscc/ocelot_regs.c REG(QSYS_TFRM_TIMER_CFG_2, 0x01131c), REG 125 drivers/net/ethernet/mscc/ocelot_regs.c REG(QSYS_TFRM_TIMER_CFG_3, 0x011320), REG 126 drivers/net/ethernet/mscc/ocelot_regs.c REG(QSYS_TFRM_TIMER_CFG_4, 0x011324), REG 127 drivers/net/ethernet/mscc/ocelot_regs.c REG(QSYS_TFRM_TIMER_CFG_5, 0x011328), REG 128 drivers/net/ethernet/mscc/ocelot_regs.c REG(QSYS_TFRM_TIMER_CFG_6, 0x01132c), REG 129 drivers/net/ethernet/mscc/ocelot_regs.c REG(QSYS_TFRM_TIMER_CFG_7, 0x011330), REG 130 drivers/net/ethernet/mscc/ocelot_regs.c REG(QSYS_TFRM_TIMER_CFG_8, 0x011334), REG 131 drivers/net/ethernet/mscc/ocelot_regs.c REG(QSYS_RED_PROFILE, 0x011338), REG 132 drivers/net/ethernet/mscc/ocelot_regs.c REG(QSYS_RES_QOS_MODE, 0x011378), REG 133 drivers/net/ethernet/mscc/ocelot_regs.c REG(QSYS_RES_CFG, 0x012000), REG 134 drivers/net/ethernet/mscc/ocelot_regs.c REG(QSYS_RES_STAT, 0x012004), REG 135 drivers/net/ethernet/mscc/ocelot_regs.c REG(QSYS_EGR_DROP_MODE, 0x01137c), REG 136 drivers/net/ethernet/mscc/ocelot_regs.c REG(QSYS_EQ_CTRL, 0x011380), REG 137 drivers/net/ethernet/mscc/ocelot_regs.c REG(QSYS_EVENTS_CORE, 0x011384), REG 138 drivers/net/ethernet/mscc/ocelot_regs.c REG(QSYS_CIR_CFG, 0x000000), REG 139 drivers/net/ethernet/mscc/ocelot_regs.c REG(QSYS_EIR_CFG, 0x000004), REG 140 drivers/net/ethernet/mscc/ocelot_regs.c REG(QSYS_SE_CFG, 0x000008), REG 141 drivers/net/ethernet/mscc/ocelot_regs.c REG(QSYS_SE_DWRR_CFG, 0x00000c), REG 142 drivers/net/ethernet/mscc/ocelot_regs.c REG(QSYS_SE_CONNECT, 0x00003c), REG 143 drivers/net/ethernet/mscc/ocelot_regs.c REG(QSYS_SE_DLB_SENSE, 0x000040), REG 144 drivers/net/ethernet/mscc/ocelot_regs.c REG(QSYS_CIR_STATE, 0x000044), REG 145 drivers/net/ethernet/mscc/ocelot_regs.c REG(QSYS_EIR_STATE, 0x000048), REG 146 drivers/net/ethernet/mscc/ocelot_regs.c REG(QSYS_SE_STATE, 0x00004c), REG 147 drivers/net/ethernet/mscc/ocelot_regs.c REG(QSYS_HSCH_MISC_CFG, 0x011388), REG 151 drivers/net/ethernet/mscc/ocelot_regs.c REG(REW_PORT_VLAN_CFG, 0x000000), REG 152 drivers/net/ethernet/mscc/ocelot_regs.c REG(REW_TAG_CFG, 0x000004), REG 153 drivers/net/ethernet/mscc/ocelot_regs.c REG(REW_PORT_CFG, 0x000008), REG 154 drivers/net/ethernet/mscc/ocelot_regs.c REG(REW_DSCP_CFG, 0x00000c), REG 155 drivers/net/ethernet/mscc/ocelot_regs.c REG(REW_PCP_DEI_QOS_MAP_CFG, 0x000010), REG 156 drivers/net/ethernet/mscc/ocelot_regs.c REG(REW_PTP_CFG, 0x000050), REG 157 drivers/net/ethernet/mscc/ocelot_regs.c REG(REW_PTP_DLY1_CFG, 0x000054), REG 158 drivers/net/ethernet/mscc/ocelot_regs.c REG(REW_DSCP_REMAP_DP1_CFG, 0x000690), REG 159 drivers/net/ethernet/mscc/ocelot_regs.c REG(REW_DSCP_REMAP_CFG, 0x000790), REG 160 drivers/net/ethernet/mscc/ocelot_regs.c REG(REW_STAT_CFG, 0x000890), REG 161 drivers/net/ethernet/mscc/ocelot_regs.c REG(REW_PPT, 0x000680), REG 165 drivers/net/ethernet/mscc/ocelot_regs.c REG(SYS_COUNT_RX_OCTETS, 0x000000), REG 166 drivers/net/ethernet/mscc/ocelot_regs.c REG(SYS_COUNT_RX_UNICAST, 0x000004), REG 167 drivers/net/ethernet/mscc/ocelot_regs.c REG(SYS_COUNT_RX_MULTICAST, 0x000008), REG 168 drivers/net/ethernet/mscc/ocelot_regs.c REG(SYS_COUNT_RX_BROADCAST, 0x00000c), REG 169 drivers/net/ethernet/mscc/ocelot_regs.c REG(SYS_COUNT_RX_SHORTS, 0x000010), REG 170 drivers/net/ethernet/mscc/ocelot_regs.c REG(SYS_COUNT_RX_FRAGMENTS, 0x000014), REG 171 drivers/net/ethernet/mscc/ocelot_regs.c REG(SYS_COUNT_RX_JABBERS, 0x000018), REG 172 drivers/net/ethernet/mscc/ocelot_regs.c REG(SYS_COUNT_RX_CRC_ALIGN_ERRS, 0x00001c), REG 173 drivers/net/ethernet/mscc/ocelot_regs.c REG(SYS_COUNT_RX_SYM_ERRS, 0x000020), REG 174 drivers/net/ethernet/mscc/ocelot_regs.c REG(SYS_COUNT_RX_64, 0x000024), REG 175 drivers/net/ethernet/mscc/ocelot_regs.c REG(SYS_COUNT_RX_65_127, 0x000028), REG 176 drivers/net/ethernet/mscc/ocelot_regs.c REG(SYS_COUNT_RX_128_255, 0x00002c), REG 177 drivers/net/ethernet/mscc/ocelot_regs.c REG(SYS_COUNT_RX_256_1023, 0x000030), REG 178 drivers/net/ethernet/mscc/ocelot_regs.c REG(SYS_COUNT_RX_1024_1526, 0x000034), REG 179 drivers/net/ethernet/mscc/ocelot_regs.c REG(SYS_COUNT_RX_1527_MAX, 0x000038), REG 180 drivers/net/ethernet/mscc/ocelot_regs.c REG(SYS_COUNT_RX_PAUSE, 0x00003c), REG 181 drivers/net/ethernet/mscc/ocelot_regs.c REG(SYS_COUNT_RX_CONTROL, 0x000040), REG 182 drivers/net/ethernet/mscc/ocelot_regs.c REG(SYS_COUNT_RX_LONGS, 0x000044), REG 183 drivers/net/ethernet/mscc/ocelot_regs.c REG(SYS_COUNT_RX_CLASSIFIED_DROPS, 0x000048), REG 184 drivers/net/ethernet/mscc/ocelot_regs.c REG(SYS_COUNT_TX_OCTETS, 0x000100), REG 185 drivers/net/ethernet/mscc/ocelot_regs.c REG(SYS_COUNT_TX_UNICAST, 0x000104), REG 186 drivers/net/ethernet/mscc/ocelot_regs.c REG(SYS_COUNT_TX_MULTICAST, 0x000108), REG 187 drivers/net/ethernet/mscc/ocelot_regs.c REG(SYS_COUNT_TX_BROADCAST, 0x00010c), REG 188 drivers/net/ethernet/mscc/ocelot_regs.c REG(SYS_COUNT_TX_COLLISION, 0x000110), REG 189 drivers/net/ethernet/mscc/ocelot_regs.c REG(SYS_COUNT_TX_DROPS, 0x000114), REG 190 drivers/net/ethernet/mscc/ocelot_regs.c REG(SYS_COUNT_TX_PAUSE, 0x000118), REG 191 drivers/net/ethernet/mscc/ocelot_regs.c REG(SYS_COUNT_TX_64, 0x00011c), REG 192 drivers/net/ethernet/mscc/ocelot_regs.c REG(SYS_COUNT_TX_65_127, 0x000120), REG 193 drivers/net/ethernet/mscc/ocelot_regs.c REG(SYS_COUNT_TX_128_511, 0x000124), REG 194 drivers/net/ethernet/mscc/ocelot_regs.c REG(SYS_COUNT_TX_512_1023, 0x000128), REG 195 drivers/net/ethernet/mscc/ocelot_regs.c REG(SYS_COUNT_TX_1024_1526, 0x00012c), REG 196 drivers/net/ethernet/mscc/ocelot_regs.c REG(SYS_COUNT_TX_1527_MAX, 0x000130), REG 197 drivers/net/ethernet/mscc/ocelot_regs.c REG(SYS_COUNT_TX_AGING, 0x000170), REG 198 drivers/net/ethernet/mscc/ocelot_regs.c REG(SYS_RESET_CFG, 0x000508), REG 199 drivers/net/ethernet/mscc/ocelot_regs.c REG(SYS_CMID, 0x00050c), REG 200 drivers/net/ethernet/mscc/ocelot_regs.c REG(SYS_VLAN_ETYPE_CFG, 0x000510), REG 201 drivers/net/ethernet/mscc/ocelot_regs.c REG(SYS_PORT_MODE, 0x000514), REG 202 drivers/net/ethernet/mscc/ocelot_regs.c REG(SYS_FRONT_PORT_MODE, 0x000548), REG 203 drivers/net/ethernet/mscc/ocelot_regs.c REG(SYS_FRM_AGING, 0x000574), REG 204 drivers/net/ethernet/mscc/ocelot_regs.c REG(SYS_STAT_CFG, 0x000578), REG 205 drivers/net/ethernet/mscc/ocelot_regs.c REG(SYS_SW_STATUS, 0x00057c), REG 206 drivers/net/ethernet/mscc/ocelot_regs.c REG(SYS_MISC_CFG, 0x0005ac), REG 207 drivers/net/ethernet/mscc/ocelot_regs.c REG(SYS_REW_MAC_HIGH_CFG, 0x0005b0), REG 208 drivers/net/ethernet/mscc/ocelot_regs.c REG(SYS_REW_MAC_LOW_CFG, 0x0005dc), REG 209 drivers/net/ethernet/mscc/ocelot_regs.c REG(SYS_CM_ADDR, 0x000500), REG 210 drivers/net/ethernet/mscc/ocelot_regs.c REG(SYS_CM_DATA, 0x000504), REG 211 drivers/net/ethernet/mscc/ocelot_regs.c REG(SYS_PAUSE_CFG, 0x000608), REG 212 drivers/net/ethernet/mscc/ocelot_regs.c REG(SYS_PAUSE_TOT_CFG, 0x000638), REG 213 drivers/net/ethernet/mscc/ocelot_regs.c REG(SYS_ATOP, 0x00063c), REG 214 drivers/net/ethernet/mscc/ocelot_regs.c REG(SYS_ATOP_TOT_CFG, 0x00066c), REG 215 drivers/net/ethernet/mscc/ocelot_regs.c REG(SYS_MAC_FC_CFG, 0x000670), REG 216 drivers/net/ethernet/mscc/ocelot_regs.c REG(SYS_MMGT, 0x00069c), REG 217 drivers/net/ethernet/mscc/ocelot_regs.c REG(SYS_MMGT_FAST, 0x0006a0), REG 218 drivers/net/ethernet/mscc/ocelot_regs.c REG(SYS_EVENTS_DIF, 0x0006a4), REG 219 drivers/net/ethernet/mscc/ocelot_regs.c REG(SYS_EVENTS_CORE, 0x0006b4), REG 220 drivers/net/ethernet/mscc/ocelot_regs.c REG(SYS_CNT, 0x000000), REG 221 drivers/net/ethernet/mscc/ocelot_regs.c REG(SYS_PTP_STATUS, 0x0006b8), REG 222 drivers/net/ethernet/mscc/ocelot_regs.c REG(SYS_PTP_TXSTAMP, 0x0006bc), REG 223 drivers/net/ethernet/mscc/ocelot_regs.c REG(SYS_PTP_NXT, 0x0006c0), REG 224 drivers/net/ethernet/mscc/ocelot_regs.c REG(SYS_PTP_CFG, 0x0006c4), REG 228 drivers/net/ethernet/mscc/ocelot_regs.c REG(S2_CORE_UPDATE_CTRL, 0x000000), REG 229 drivers/net/ethernet/mscc/ocelot_regs.c REG(S2_CORE_MV_CFG, 0x000004), REG 230 drivers/net/ethernet/mscc/ocelot_regs.c REG(S2_CACHE_ENTRY_DAT, 0x000008), REG 231 drivers/net/ethernet/mscc/ocelot_regs.c REG(S2_CACHE_MASK_DAT, 0x000108), REG 232 drivers/net/ethernet/mscc/ocelot_regs.c REG(S2_CACHE_ACTION_DAT, 0x000208), REG 233 drivers/net/ethernet/mscc/ocelot_regs.c REG(S2_CACHE_CNT_DAT, 0x000308), REG 234 drivers/net/ethernet/mscc/ocelot_regs.c REG(S2_CACHE_TG_DAT, 0x000388), REG 238 drivers/net/ethernet/mscc/ocelot_regs.c REG(PTP_PIN_CFG, 0x000000), REG 239 drivers/net/ethernet/mscc/ocelot_regs.c REG(PTP_PIN_TOD_SEC_MSB, 0x000004), REG 240 drivers/net/ethernet/mscc/ocelot_regs.c REG(PTP_PIN_TOD_SEC_LSB, 0x000008), REG 241 drivers/net/ethernet/mscc/ocelot_regs.c REG(PTP_PIN_TOD_NSEC, 0x00000c), REG 242 drivers/net/ethernet/mscc/ocelot_regs.c REG(PTP_CFG_MISC, 0x0000a0), REG 243 drivers/net/ethernet/mscc/ocelot_regs.c REG(PTP_CLK_CFG_ADJ_CFG, 0x0000a4), REG 244 drivers/net/ethernet/mscc/ocelot_regs.c REG(PTP_CLK_CFG_ADJ_FREQ, 0x0000a8), REG 131 drivers/net/ethernet/sun/niu.c #define niu_set_and_wait_clear_mac(NP, REG, BITS, LIMIT, DELAY, REG_NAME) \ REG 133 drivers/net/ethernet/sun/niu.c __niu_set_and_wait_clear_mac(NP, REG, BITS, LIMIT, DELAY, REG_NAME); \ REG 170 drivers/net/ethernet/sun/niu.c #define niu_set_and_wait_clear_ipp(NP, REG, BITS, LIMIT, DELAY, REG_NAME) \ REG 172 drivers/net/ethernet/sun/niu.c __niu_set_and_wait_clear_ipp(NP, REG, BITS, LIMIT, DELAY, REG_NAME); \ REG 190 drivers/net/ethernet/sun/niu.c #define niu_wait_bits_clear(NP, REG, BITS, LIMIT, DELAY) \ REG 192 drivers/net/ethernet/sun/niu.c __niu_wait_bits_clear(NP, REG, BITS, LIMIT, DELAY); \ REG 210 drivers/net/ethernet/sun/niu.c #define niu_set_and_wait_clear(NP, REG, BITS, LIMIT, DELAY, REG_NAME) \ REG 212 drivers/net/ethernet/sun/niu.c __niu_set_and_wait_clear(NP, REG, BITS, LIMIT, DELAY, REG_NAME); \ REG 181 drivers/pinctrl/bcm/pinctrl-nsp-gpio.c nsp_set_bit(chip, REG, NSP_GPIO_EVENT, gpio, val); REG 198 drivers/pinctrl/bcm/pinctrl-nsp-gpio.c nsp_set_bit(chip, REG, NSP_GPIO_EVENT_INT_MASK, gpio, unmask); REG 200 drivers/pinctrl/bcm/pinctrl-nsp-gpio.c nsp_set_bit(chip, REG, NSP_GPIO_INT_MASK, gpio, unmask); REG 232 drivers/pinctrl/bcm/pinctrl-nsp-gpio.c falling = nsp_get_bit(chip, REG, NSP_GPIO_EVENT_INT_POLARITY, gpio); REG 233 drivers/pinctrl/bcm/pinctrl-nsp-gpio.c level_low = nsp_get_bit(chip, REG, NSP_GPIO_INT_POLARITY, gpio); REG 259 drivers/pinctrl/bcm/pinctrl-nsp-gpio.c nsp_set_bit(chip, REG, NSP_GPIO_EVENT_INT_POLARITY, gpio, falling); REG 260 drivers/pinctrl/bcm/pinctrl-nsp-gpio.c nsp_set_bit(chip, REG, NSP_GPIO_INT_POLARITY, gpio, level_low); REG 284 drivers/pinctrl/bcm/pinctrl-nsp-gpio.c nsp_set_bit(chip, REG, NSP_GPIO_OUT_EN, gpio, false); REG 298 drivers/pinctrl/bcm/pinctrl-nsp-gpio.c nsp_set_bit(chip, REG, NSP_GPIO_OUT_EN, gpio, true); REG 299 drivers/pinctrl/bcm/pinctrl-nsp-gpio.c nsp_set_bit(chip, REG, NSP_GPIO_DATA_OUT, gpio, !!(val)); REG 312 drivers/pinctrl/bcm/pinctrl-nsp-gpio.c nsp_set_bit(chip, REG, NSP_GPIO_DATA_OUT, gpio, !!(val)); REG 50 drivers/pinctrl/cirrus/pinctrl-lochnagar.c #define LN_PIN_GPIO(REV, ID, NAME, REG, SHIFT, INVERT) \ REG 52 drivers/pinctrl/cirrus/pinctrl-lochnagar.c .name = NAME, .type = LN_PTYPE_GPIO, .reg = LOCHNAGAR##REV##_##REG, \ REG 66 drivers/pinctrl/cirrus/pinctrl-lochnagar.c #define LN1_PIN_GPIO(ID, NAME, REG, SHIFT, INVERT) \ REG 67 drivers/pinctrl/cirrus/pinctrl-lochnagar.c LN_PIN_GPIO(1, ID, NAME, REG, SHIFT, INVERT) REG 75 drivers/pinctrl/cirrus/pinctrl-lochnagar.c #define LN2_PIN_GPIO(ID, NAME, REG, SHIFT, INVERT) \ REG 76 drivers/pinctrl/cirrus/pinctrl-lochnagar.c LN_PIN_GPIO(2, ID, NAME, REG, SHIFT, INVERT) REG 437 drivers/pinctrl/pinctrl-ocelot.c regmap_update_bits(info->map, REG(OCELOT_GPIO_OE, info, pin), BIT(p), REG 581 drivers/pinctrl/pinctrl-ocelot.c regmap_read(info->map, REG(OCELOT_GPIO_IN, info, offset), &val); REG 592 drivers/pinctrl/pinctrl-ocelot.c regmap_write(info->map, REG(OCELOT_GPIO_OUT_SET, info, offset), REG 595 drivers/pinctrl/pinctrl-ocelot.c regmap_write(info->map, REG(OCELOT_GPIO_OUT_CLR, info, offset), REG 605 drivers/pinctrl/pinctrl-ocelot.c regmap_read(info->map, REG(OCELOT_GPIO_OE, info, offset), &val); REG 623 drivers/pinctrl/pinctrl-ocelot.c regmap_write(info->map, REG(OCELOT_GPIO_OUT_SET, info, offset), REG 626 drivers/pinctrl/pinctrl-ocelot.c regmap_write(info->map, REG(OCELOT_GPIO_OUT_CLR, info, offset), REG 649 drivers/pinctrl/pinctrl-ocelot.c regmap_update_bits(info->map, REG(OCELOT_GPIO_INTR_ENA, info, gpio), REG 659 drivers/pinctrl/pinctrl-ocelot.c regmap_update_bits(info->map, REG(OCELOT_GPIO_INTR_ENA, info, gpio), REG 669 drivers/pinctrl/pinctrl-ocelot.c regmap_write_bits(info->map, REG(OCELOT_GPIO_INTR, info, gpio), REG 244 drivers/regulator/mc13783-regulator.c MC13783_DEFINE(REG, _name, _node, _reg, _vsel_reg, _voltages) REG 246 drivers/regulator/mc13783-regulator.c MC13783_DEFINE(REG, _name, _node, _reg, _vsel_reg, _voltages) REG 255 drivers/regulator/mc13783-regulator.c MC13783_FIXED_DEFINE(REG, VAUDIO, vaudio, REGULATORMODE0, mc13783_vaudio_val), REG 256 drivers/regulator/mc13783-regulator.c MC13783_FIXED_DEFINE(REG, VIOHI, viohi, REGULATORMODE0, mc13783_viohi_val), REG 275 drivers/regulator/mc13783-regulator.c MC13783_FIXED_DEFINE(REG, VRFBG, vrfbg, REGULATORMODE1, mc13783_vrfbg_val), REG 286 drivers/regulator/mc13783-regulator.c MC13783_GPO_DEFINE(REG, GPO1, gpo1, POWERMISC, mc13783_gpo_val), REG 287 drivers/regulator/mc13783-regulator.c MC13783_GPO_DEFINE(REG, GPO2, gpo1, POWERMISC, mc13783_gpo_val), REG 288 drivers/regulator/mc13783-regulator.c MC13783_GPO_DEFINE(REG, GPO3, gpo1, POWERMISC, mc13783_gpo_val), REG 289 drivers/regulator/mc13783-regulator.c MC13783_GPO_DEFINE(REG, GPO4, gpo1, POWERMISC, mc13783_gpo_val), REG 290 drivers/regulator/mc13783-regulator.c MC13783_GPO_DEFINE(REG, PWGT1SPI, pwgt1spi, POWERMISC, mc13783_pwgtdrv_val), REG 291 drivers/regulator/mc13783-regulator.c MC13783_GPO_DEFINE(REG, PWGT2SPI, pwgt2spi, POWERMISC, mc13783_pwgtdrv_val), REG 45 drivers/regulator/rn5t618-regulator.c REG(DCDC1, DC1CTL, BIT(0), DC1DAC, 0xff, 600000, 3500000, 12500), REG 46 drivers/regulator/rn5t618-regulator.c REG(DCDC2, DC2CTL, BIT(0), DC2DAC, 0xff, 600000, 3500000, 12500), REG 47 drivers/regulator/rn5t618-regulator.c REG(DCDC3, DC3CTL, BIT(0), DC3DAC, 0xff, 600000, 3500000, 12500), REG 48 drivers/regulator/rn5t618-regulator.c REG(DCDC4, DC4CTL, BIT(0), DC4DAC, 0xff, 600000, 3500000, 12500), REG 50 drivers/regulator/rn5t618-regulator.c REG(LDO1, LDOEN1, BIT(0), LDO1DAC, 0x7f, 900000, 3500000, 25000), REG 51 drivers/regulator/rn5t618-regulator.c REG(LDO2, LDOEN1, BIT(1), LDO2DAC, 0x7f, 900000, 3500000, 25000), REG 52 drivers/regulator/rn5t618-regulator.c REG(LDO3, LDOEN1, BIT(2), LDO3DAC, 0x7f, 600000, 3500000, 25000), REG 53 drivers/regulator/rn5t618-regulator.c REG(LDO4, LDOEN1, BIT(3), LDO4DAC, 0x7f, 900000, 3500000, 25000), REG 54 drivers/regulator/rn5t618-regulator.c REG(LDO5, LDOEN1, BIT(4), LDO5DAC, 0x7f, 900000, 3500000, 25000), REG 56 drivers/regulator/rn5t618-regulator.c REG(LDORTC1, LDOEN2, BIT(4), LDORTCDAC, 0x7f, 1200000, 3500000, 25000), REG 57 drivers/regulator/rn5t618-regulator.c REG(LDORTC2, LDOEN2, BIT(5), LDORTC2DAC, 0x7f, 900000, 3500000, 25000), REG 62 drivers/regulator/rn5t618-regulator.c REG(DCDC1, DC1CTL, BIT(0), DC1DAC, 0xff, 600000, 3500000, 12500), REG 63 drivers/regulator/rn5t618-regulator.c REG(DCDC2, DC2CTL, BIT(0), DC2DAC, 0xff, 600000, 3500000, 12500), REG 64 drivers/regulator/rn5t618-regulator.c REG(DCDC3, DC3CTL, BIT(0), DC3DAC, 0xff, 600000, 3500000, 12500), REG 66 drivers/regulator/rn5t618-regulator.c REG(LDO1, LDOEN1, BIT(0), LDO1DAC, 0x7f, 900000, 3500000, 25000), REG 67 drivers/regulator/rn5t618-regulator.c REG(LDO2, LDOEN1, BIT(1), LDO2DAC, 0x7f, 900000, 3500000, 25000), REG 68 drivers/regulator/rn5t618-regulator.c REG(LDO3, LDOEN1, BIT(2), LDO3DAC, 0x7f, 600000, 3500000, 25000), REG 69 drivers/regulator/rn5t618-regulator.c REG(LDO4, LDOEN1, BIT(3), LDO4DAC, 0x7f, 900000, 3500000, 25000), REG 70 drivers/regulator/rn5t618-regulator.c REG(LDO5, LDOEN1, BIT(4), LDO5DAC, 0x7f, 900000, 3500000, 25000), REG 72 drivers/regulator/rn5t618-regulator.c REG(LDORTC1, LDOEN2, BIT(4), LDORTCDAC, 0x7f, 1700000, 3500000, 25000), REG 73 drivers/regulator/rn5t618-regulator.c REG(LDORTC2, LDOEN2, BIT(5), LDORTC2DAC, 0x7f, 900000, 3500000, 25000), REG 78 drivers/regulator/rn5t618-regulator.c REG(DCDC1, DC1CTL, BIT(0), DC1DAC, 0xff, 600000, 3500000, 12500), REG 79 drivers/regulator/rn5t618-regulator.c REG(DCDC2, DC2CTL, BIT(0), DC2DAC, 0xff, 600000, 3500000, 12500), REG 80 drivers/regulator/rn5t618-regulator.c REG(DCDC3, DC3CTL, BIT(0), DC3DAC, 0xff, 600000, 3500000, 12500), REG 81 drivers/regulator/rn5t618-regulator.c REG(DCDC4, DC4CTL, BIT(0), DC4DAC, 0xff, 600000, 3500000, 12500), REG 82 drivers/regulator/rn5t618-regulator.c REG(DCDC5, DC5CTL, BIT(0), DC5DAC, 0xff, 600000, 3500000, 12500), REG 84 drivers/regulator/rn5t618-regulator.c REG(LDO1, LDOEN1, BIT(0), LDO1DAC, 0x7f, 900000, 3500000, 25000), REG 85 drivers/regulator/rn5t618-regulator.c REG(LDO2, LDOEN1, BIT(1), LDO2DAC, 0x7f, 900000, 3500000, 25000), REG 86 drivers/regulator/rn5t618-regulator.c REG(LDO3, LDOEN1, BIT(2), LDO3DAC, 0x7f, 900000, 3500000, 25000), REG 87 drivers/regulator/rn5t618-regulator.c REG(LDO4, LDOEN1, BIT(3), LDO4DAC, 0x7f, 900000, 3500000, 25000), REG 88 drivers/regulator/rn5t618-regulator.c REG(LDO5, LDOEN1, BIT(4), LDO5DAC, 0x7f, 600000, 3500000, 25000), REG 89 drivers/regulator/rn5t618-regulator.c REG(LDO6, LDOEN1, BIT(5), LDO6DAC, 0x7f, 600000, 3500000, 25000), REG 90 drivers/regulator/rn5t618-regulator.c REG(LDO7, LDOEN1, BIT(6), LDO7DAC, 0x7f, 900000, 3500000, 25000), REG 91 drivers/regulator/rn5t618-regulator.c REG(LDO8, LDOEN1, BIT(7), LDO8DAC, 0x7f, 900000, 3500000, 25000), REG 92 drivers/regulator/rn5t618-regulator.c REG(LDO9, LDOEN2, BIT(0), LDO9DAC, 0x7f, 900000, 3500000, 25000), REG 93 drivers/regulator/rn5t618-regulator.c REG(LDO10, LDOEN2, BIT(0), LDO10DAC, 0x7f, 900000, 3500000, 25000), REG 95 drivers/regulator/rn5t618-regulator.c REG(LDORTC1, LDOEN2, BIT(4), LDORTCDAC, 0x7f, 1700000, 3500000, 25000), REG 96 drivers/regulator/rn5t618-regulator.c REG(LDORTC2, LDOEN2, BIT(5), LDORTC2DAC, 0x7f, 900000, 3500000, 25000), REG 116 drivers/scsi/esp_scsi.c #define esp_read8(REG) esp->ops->esp_read8(esp, REG) REG 117 drivers/scsi/esp_scsi.c #define esp_write8(VAL,REG) esp->ops->esp_write8(esp, VAL, REG) REG 49 drivers/scsi/mac_esp.c #define esp_read8(REG) mac_esp_read8(esp, REG) REG 50 drivers/scsi/mac_esp.c #define esp_write8(VAL, REG) mac_esp_write8(esp, VAL, REG) REG 1989 drivers/scsi/ncr53c8xx.c #define RADDR(label) (RELOC_REGISTER | REG(label)) REG 1990 drivers/scsi/ncr53c8xx.c #define FADDR(label,ofs)(RELOC_REGISTER | ((REG(label))+(ofs))) REG 1089 drivers/scsi/ncr53c8xx.h (0x68000000 | (SCR_REG_OFS(REG(reg))) | (op) | (((data)&0xff)<<8ul)) REG 1092 drivers/scsi/ncr53c8xx.h (0x70000000 | (SCR_REG_OFS(REG(reg))) | (op) | (((data)&0xff)<<8ul)) REG 1095 drivers/scsi/ncr53c8xx.h (0x78000000 | (SCR_REG_OFS(REG(reg))) | (op) | (((data)&0xff)<<8ul)) REG 1161 drivers/scsi/ncr53c8xx.h (0xe1000000 | how | (SCR_REG_OFS2(REG(reg))) | (n)) REG 1164 drivers/scsi/ncr53c8xx.h (0xe0000000 | how | (SCR_REG_OFS2(REG(reg))) | (n)) REG 43 drivers/scsi/sun3x_esp.c #define dma_read32(REG) \ REG 44 drivers/scsi/sun3x_esp.c readl(esp->dma_regs + (REG)) REG 45 drivers/scsi/sun3x_esp.c #define dma_write32(VAL, REG) \ REG 46 drivers/scsi/sun3x_esp.c writel((VAL), esp->dma_regs + (REG)) REG 48 drivers/scsi/sun3x_esp.c #define dma_read32(REG) \ REG 49 drivers/scsi/sun3x_esp.c *(volatile u32 *)(esp->dma_regs + (REG)) REG 50 drivers/scsi/sun3x_esp.c #define dma_write32(VAL, REG) \ REG 51 drivers/scsi/sun3x_esp.c do { *(volatile u32 *)(esp->dma_regs + (REG)) = (VAL); } while (0) REG 31 drivers/scsi/sun_esp.c #define dma_read32(REG) \ REG 32 drivers/scsi/sun_esp.c sbus_readl(esp->dma_regs + (REG)) REG 33 drivers/scsi/sun_esp.c #define dma_write32(VAL, REG) \ REG 34 drivers/scsi/sun_esp.c sbus_writel((VAL), esp->dma_regs + (REG)) REG 572 drivers/scsi/sym53c8xx_2/sym_defs.h (0x68000000 | (SCR_REG_OFS(REG(reg))) | (op) | (((data)&0xff)<<8ul)) REG 575 drivers/scsi/sym53c8xx_2/sym_defs.h (0x70000000 | (SCR_REG_OFS(REG(reg))) | (op) | (((data)&0xff)<<8ul)) REG 578 drivers/scsi/sym53c8xx_2/sym_defs.h (0x78000000 | (SCR_REG_OFS(REG(reg))) | (op) | (((data)&0xff)<<8ul)) REG 644 drivers/scsi/sym53c8xx_2/sym_defs.h (0xe1000000 | how | (SCR_REG_OFS2(REG(reg))) | (n)) REG 647 drivers/scsi/sym53c8xx_2/sym_defs.h (0xe0000000 | how | (SCR_REG_OFS2(REG(reg))) | (n)) REG 184 drivers/scsi/sym53c8xx_2/sym_fw.h #define RADDR_1(label) (RELOC_REGISTER | REG(label)) REG 185 drivers/scsi/sym53c8xx_2/sym_fw.h #define RADDR_2(label,ofs) (RELOC_REGISTER | ((REG(label))+(ofs))) REG 117 drivers/video/fbdev/controlfb.c #define CNTRL_REG(INFO,REG) (&(((INFO)->control_regs->REG).r)) REG 95 drivers/watchdog/it8712f_wdt.c outb(reg, REG); REG 101 drivers/watchdog/it8712f_wdt.c outb(reg, REG); REG 108 drivers/watchdog/it8712f_wdt.c outb(reg++, REG); REG 110 drivers/watchdog/it8712f_wdt.c outb(reg, REG); REG 117 drivers/watchdog/it8712f_wdt.c outb(LDN, REG); REG 126 drivers/watchdog/it8712f_wdt.c if (!request_muxed_region(REG, 2, NAME)) REG 129 drivers/watchdog/it8712f_wdt.c outb(0x87, REG); REG 130 drivers/watchdog/it8712f_wdt.c outb(0x01, REG); REG 131 drivers/watchdog/it8712f_wdt.c outb(0x55, REG); REG 132 drivers/watchdog/it8712f_wdt.c outb(0x55, REG); REG 138 drivers/watchdog/it8712f_wdt.c outb(0x02, REG); REG 140 drivers/watchdog/it8712f_wdt.c release_region(REG, 2); REG 107 drivers/watchdog/it87_wdt.c if (!request_muxed_region(REG, 2, WATCHDOG_NAME)) REG 110 drivers/watchdog/it87_wdt.c outb(0x87, REG); REG 111 drivers/watchdog/it87_wdt.c outb(0x01, REG); REG 112 drivers/watchdog/it87_wdt.c outb(0x55, REG); REG 113 drivers/watchdog/it87_wdt.c outb(0x55, REG); REG 119 drivers/watchdog/it87_wdt.c outb(0x02, REG); REG 121 drivers/watchdog/it87_wdt.c release_region(REG, 2); REG 126 drivers/watchdog/it87_wdt.c outb(LDNREG, REG); REG 132 drivers/watchdog/it87_wdt.c outb(reg, REG); REG 138 drivers/watchdog/it87_wdt.c outb(reg, REG); REG 145 drivers/watchdog/it87_wdt.c outb(reg++, REG); REG 147 drivers/watchdog/it87_wdt.c outb(reg, REG); REG 154 drivers/watchdog/it87_wdt.c outb(reg++, REG); REG 156 drivers/watchdog/it87_wdt.c outb(reg, REG); REG 3008 fs/proc/base.c REG("environ", S_IRUSR, proc_environ_operations), REG 3009 fs/proc/base.c REG("auxv", S_IRUSR, proc_auxv_operations), REG 3014 fs/proc/base.c REG("sched", S_IRUGO|S_IWUSR, proc_pid_sched_operations), REG 3017 fs/proc/base.c REG("autogroup", S_IRUGO|S_IWUSR, proc_pid_sched_autogroup_operations), REG 3019 fs/proc/base.c REG("comm", S_IRUGO|S_IWUSR, proc_pid_set_comm_operations), REG 3023 fs/proc/base.c REG("cmdline", S_IRUGO, proc_pid_cmdline_ops), REG 3026 fs/proc/base.c REG("maps", S_IRUGO, proc_pid_maps_operations), REG 3028 fs/proc/base.c REG("numa_maps", S_IRUGO, proc_pid_numa_maps_operations), REG 3030 fs/proc/base.c REG("mem", S_IRUSR|S_IWUSR, proc_mem_operations), REG 3034 fs/proc/base.c REG("mounts", S_IRUGO, proc_mounts_operations), REG 3035 fs/proc/base.c REG("mountinfo", S_IRUGO, proc_mountinfo_operations), REG 3036 fs/proc/base.c REG("mountstats", S_IRUSR, proc_mountstats_operations), REG 3038 fs/proc/base.c REG("clear_refs", S_IWUSR, proc_clear_refs_operations), REG 3039 fs/proc/base.c REG("smaps", S_IRUGO, proc_pid_smaps_operations), REG 3040 fs/proc/base.c REG("smaps_rollup", S_IRUGO, proc_pid_smaps_rollup_operations), REG 3041 fs/proc/base.c REG("pagemap", S_IRUSR, proc_pagemap_operations), REG 3056 fs/proc/base.c REG("latency", S_IRUGO, proc_lstats_operations), REG 3065 fs/proc/base.c REG("oom_adj", S_IRUGO|S_IWUSR, proc_oom_adj_operations), REG 3066 fs/proc/base.c REG("oom_score_adj", S_IRUGO|S_IWUSR, proc_oom_score_adj_operations), REG 3068 fs/proc/base.c REG("loginuid", S_IWUSR|S_IRUGO, proc_loginuid_operations), REG 3069 fs/proc/base.c REG("sessionid", S_IRUGO, proc_sessionid_operations), REG 3072 fs/proc/base.c REG("make-it-fail", S_IRUGO|S_IWUSR, proc_fault_inject_operations), REG 3073 fs/proc/base.c REG("fail-nth", 0644, proc_fail_nth_operations), REG 3076 fs/proc/base.c REG("coredump_filter", S_IRUGO|S_IWUSR, proc_coredump_filter_operations), REG 3082 fs/proc/base.c REG("uid_map", S_IRUGO|S_IWUSR, proc_uid_map_operations), REG 3083 fs/proc/base.c REG("gid_map", S_IRUGO|S_IWUSR, proc_gid_map_operations), REG 3084 fs/proc/base.c REG("projid_map", S_IRUGO|S_IWUSR, proc_projid_map_operations), REG 3085 fs/proc/base.c REG("setgroups", S_IRUGO|S_IWUSR, proc_setgroups_operations), REG 3088 fs/proc/base.c REG("timers", S_IRUGO, proc_timers_operations), REG 3090 fs/proc/base.c REG("timerslack_ns", S_IRUGO|S_IWUGO, proc_pid_set_timerslack_ns_operations), REG 3407 fs/proc/base.c REG("environ", S_IRUSR, proc_environ_operations), REG 3408 fs/proc/base.c REG("auxv", S_IRUSR, proc_auxv_operations), REG 3413 fs/proc/base.c REG("sched", S_IRUGO|S_IWUSR, proc_pid_sched_operations), REG 3421 fs/proc/base.c REG("cmdline", S_IRUGO, proc_pid_cmdline_ops), REG 3424 fs/proc/base.c REG("maps", S_IRUGO, proc_pid_maps_operations), REG 3426 fs/proc/base.c REG("children", S_IRUGO, proc_tid_children_operations), REG 3429 fs/proc/base.c REG("numa_maps", S_IRUGO, proc_pid_numa_maps_operations), REG 3431 fs/proc/base.c REG("mem", S_IRUSR|S_IWUSR, proc_mem_operations), REG 3435 fs/proc/base.c REG("mounts", S_IRUGO, proc_mounts_operations), REG 3436 fs/proc/base.c REG("mountinfo", S_IRUGO, proc_mountinfo_operations), REG 3438 fs/proc/base.c REG("clear_refs", S_IWUSR, proc_clear_refs_operations), REG 3439 fs/proc/base.c REG("smaps", S_IRUGO, proc_pid_smaps_operations), REG 3440 fs/proc/base.c REG("smaps_rollup", S_IRUGO, proc_pid_smaps_rollup_operations), REG 3441 fs/proc/base.c REG("pagemap", S_IRUSR, proc_pagemap_operations), REG 3456 fs/proc/base.c REG("latency", S_IRUGO, proc_lstats_operations), REG 3465 fs/proc/base.c REG("oom_adj", S_IRUGO|S_IWUSR, proc_oom_adj_operations), REG 3466 fs/proc/base.c REG("oom_score_adj", S_IRUGO|S_IWUSR, proc_oom_score_adj_operations), REG 3468 fs/proc/base.c REG("loginuid", S_IWUSR|S_IRUGO, proc_loginuid_operations), REG 3469 fs/proc/base.c REG("sessionid", S_IRUGO, proc_sessionid_operations), REG 3472 fs/proc/base.c REG("make-it-fail", S_IRUGO|S_IWUSR, proc_fault_inject_operations), REG 3473 fs/proc/base.c REG("fail-nth", 0644, proc_fail_nth_operations), REG 3479 fs/proc/base.c REG("uid_map", S_IRUGO|S_IWUSR, proc_uid_map_operations), REG 3480 fs/proc/base.c REG("gid_map", S_IRUGO|S_IWUSR, proc_gid_map_operations), REG 3481 fs/proc/base.c REG("projid_map", S_IRUGO|S_IWUSR, proc_projid_map_operations), REG 3482 fs/proc/base.c REG("setgroups", S_IRUGO|S_IWUSR, proc_setgroups_operations), REG 181 sound/isa/wss/wss_lib.c wss_outb(chip, CS4231P(REG), value); REG 194 sound/isa/wss/wss_lib.c wss_outb(chip, CS4231P(REG), value); REG 212 sound/isa/wss/wss_lib.c return wss_inb(chip, CS4231P(REG)); REG 220 sound/isa/wss/wss_lib.c wss_outb(chip, CS4231P(REG), REG 222 sound/isa/wss/wss_lib.c wss_outb(chip, CS4231P(REG), val); REG 233 sound/isa/wss/wss_lib.c wss_outb(chip, CS4231P(REG), REG 236 sound/isa/wss/wss_lib.c return wss_inb(chip, CS4231P(REG)); REG 240 sound/isa/wss/wss_lib.c res = wss_inb(chip, CS4231P(REG)); REG 302 sound/sparc/cs4231.c __cs4231_writeb(chip, value, CS4231U(chip, REG)); REG 334 sound/sparc/cs4231.c return __cs4231_readb(chip, CS4231U(chip, REG)); REG 19 tools/perf/arch/arm/util/unwind-libdw.c dwarf_regs[0] = REG(R0); REG 20 tools/perf/arch/arm/util/unwind-libdw.c dwarf_regs[1] = REG(R1); REG 21 tools/perf/arch/arm/util/unwind-libdw.c dwarf_regs[2] = REG(R2); REG 22 tools/perf/arch/arm/util/unwind-libdw.c dwarf_regs[3] = REG(R3); REG 23 tools/perf/arch/arm/util/unwind-libdw.c dwarf_regs[4] = REG(R4); REG 24 tools/perf/arch/arm/util/unwind-libdw.c dwarf_regs[5] = REG(R5); REG 25 tools/perf/arch/arm/util/unwind-libdw.c dwarf_regs[6] = REG(R6); REG 26 tools/perf/arch/arm/util/unwind-libdw.c dwarf_regs[7] = REG(R7); REG 27 tools/perf/arch/arm/util/unwind-libdw.c dwarf_regs[8] = REG(R8); REG 28 tools/perf/arch/arm/util/unwind-libdw.c dwarf_regs[9] = REG(R9); REG 29 tools/perf/arch/arm/util/unwind-libdw.c dwarf_regs[10] = REG(R10); REG 30 tools/perf/arch/arm/util/unwind-libdw.c dwarf_regs[11] = REG(FP); REG 31 tools/perf/arch/arm/util/unwind-libdw.c dwarf_regs[12] = REG(IP); REG 32 tools/perf/arch/arm/util/unwind-libdw.c dwarf_regs[13] = REG(SP); REG 33 tools/perf/arch/arm/util/unwind-libdw.c dwarf_regs[14] = REG(LR); REG 34 tools/perf/arch/arm/util/unwind-libdw.c dwarf_regs[15] = REG(PC); REG 19 tools/perf/arch/arm64/util/unwind-libdw.c dwarf_regs[0] = REG(X0); REG 20 tools/perf/arch/arm64/util/unwind-libdw.c dwarf_regs[1] = REG(X1); REG 21 tools/perf/arch/arm64/util/unwind-libdw.c dwarf_regs[2] = REG(X2); REG 22 tools/perf/arch/arm64/util/unwind-libdw.c dwarf_regs[3] = REG(X3); REG 23 tools/perf/arch/arm64/util/unwind-libdw.c dwarf_regs[4] = REG(X4); REG 24 tools/perf/arch/arm64/util/unwind-libdw.c dwarf_regs[5] = REG(X5); REG 25 tools/perf/arch/arm64/util/unwind-libdw.c dwarf_regs[6] = REG(X6); REG 26 tools/perf/arch/arm64/util/unwind-libdw.c dwarf_regs[7] = REG(X7); REG 27 tools/perf/arch/arm64/util/unwind-libdw.c dwarf_regs[8] = REG(X8); REG 28 tools/perf/arch/arm64/util/unwind-libdw.c dwarf_regs[9] = REG(X9); REG 29 tools/perf/arch/arm64/util/unwind-libdw.c dwarf_regs[10] = REG(X10); REG 30 tools/perf/arch/arm64/util/unwind-libdw.c dwarf_regs[11] = REG(X11); REG 31 tools/perf/arch/arm64/util/unwind-libdw.c dwarf_regs[12] = REG(X12); REG 32 tools/perf/arch/arm64/util/unwind-libdw.c dwarf_regs[13] = REG(X13); REG 33 tools/perf/arch/arm64/util/unwind-libdw.c dwarf_regs[14] = REG(X14); REG 34 tools/perf/arch/arm64/util/unwind-libdw.c dwarf_regs[15] = REG(X15); REG 35 tools/perf/arch/arm64/util/unwind-libdw.c dwarf_regs[16] = REG(X16); REG 36 tools/perf/arch/arm64/util/unwind-libdw.c dwarf_regs[17] = REG(X17); REG 37 tools/perf/arch/arm64/util/unwind-libdw.c dwarf_regs[18] = REG(X18); REG 38 tools/perf/arch/arm64/util/unwind-libdw.c dwarf_regs[19] = REG(X19); REG 39 tools/perf/arch/arm64/util/unwind-libdw.c dwarf_regs[20] = REG(X20); REG 40 tools/perf/arch/arm64/util/unwind-libdw.c dwarf_regs[21] = REG(X21); REG 41 tools/perf/arch/arm64/util/unwind-libdw.c dwarf_regs[22] = REG(X22); REG 42 tools/perf/arch/arm64/util/unwind-libdw.c dwarf_regs[23] = REG(X23); REG 43 tools/perf/arch/arm64/util/unwind-libdw.c dwarf_regs[24] = REG(X24); REG 44 tools/perf/arch/arm64/util/unwind-libdw.c dwarf_regs[25] = REG(X25); REG 45 tools/perf/arch/arm64/util/unwind-libdw.c dwarf_regs[26] = REG(X26); REG 46 tools/perf/arch/arm64/util/unwind-libdw.c dwarf_regs[27] = REG(X27); REG 47 tools/perf/arch/arm64/util/unwind-libdw.c dwarf_regs[28] = REG(X28); REG 48 tools/perf/arch/arm64/util/unwind-libdw.c dwarf_regs[29] = REG(X29); REG 49 tools/perf/arch/arm64/util/unwind-libdw.c dwarf_regs[30] = REG(LR); REG 50 tools/perf/arch/arm64/util/unwind-libdw.c dwarf_regs[31] = REG(SP); REG 56 tools/perf/arch/arm64/util/unwind-libdw.c dwarf_pc = REG(PC); REG 22 tools/perf/arch/csky/util/unwind-libdw.c dwarf_regs[0] = REG(A0); REG 23 tools/perf/arch/csky/util/unwind-libdw.c dwarf_regs[1] = REG(A1); REG 24 tools/perf/arch/csky/util/unwind-libdw.c dwarf_regs[2] = REG(A2); REG 25 tools/perf/arch/csky/util/unwind-libdw.c dwarf_regs[3] = REG(A3); REG 26 tools/perf/arch/csky/util/unwind-libdw.c dwarf_regs[4] = REG(REGS0); REG 27 tools/perf/arch/csky/util/unwind-libdw.c dwarf_regs[5] = REG(REGS1); REG 28 tools/perf/arch/csky/util/unwind-libdw.c dwarf_regs[6] = REG(REGS2); REG 29 tools/perf/arch/csky/util/unwind-libdw.c dwarf_regs[7] = REG(REGS3); REG 30 tools/perf/arch/csky/util/unwind-libdw.c dwarf_regs[8] = REG(REGS4); REG 31 tools/perf/arch/csky/util/unwind-libdw.c dwarf_regs[9] = REG(REGS5); REG 32 tools/perf/arch/csky/util/unwind-libdw.c dwarf_regs[10] = REG(REGS6); REG 33 tools/perf/arch/csky/util/unwind-libdw.c dwarf_regs[11] = REG(REGS7); REG 34 tools/perf/arch/csky/util/unwind-libdw.c dwarf_regs[12] = REG(REGS8); REG 35 tools/perf/arch/csky/util/unwind-libdw.c dwarf_regs[13] = REG(REGS9); REG 36 tools/perf/arch/csky/util/unwind-libdw.c dwarf_regs[14] = REG(SP); REG 37 tools/perf/arch/csky/util/unwind-libdw.c dwarf_regs[15] = REG(LR); REG 38 tools/perf/arch/csky/util/unwind-libdw.c dwarf_regs[16] = REG(EXREGS0); REG 39 tools/perf/arch/csky/util/unwind-libdw.c dwarf_regs[17] = REG(EXREGS1); REG 40 tools/perf/arch/csky/util/unwind-libdw.c dwarf_regs[18] = REG(EXREGS2); REG 41 tools/perf/arch/csky/util/unwind-libdw.c dwarf_regs[19] = REG(EXREGS3); REG 42 tools/perf/arch/csky/util/unwind-libdw.c dwarf_regs[20] = REG(EXREGS4); REG 43 tools/perf/arch/csky/util/unwind-libdw.c dwarf_regs[21] = REG(EXREGS5); REG 44 tools/perf/arch/csky/util/unwind-libdw.c dwarf_regs[22] = REG(EXREGS6); REG 45 tools/perf/arch/csky/util/unwind-libdw.c dwarf_regs[23] = REG(EXREGS7); REG 46 tools/perf/arch/csky/util/unwind-libdw.c dwarf_regs[24] = REG(EXREGS8); REG 47 tools/perf/arch/csky/util/unwind-libdw.c dwarf_regs[25] = REG(EXREGS9); REG 48 tools/perf/arch/csky/util/unwind-libdw.c dwarf_regs[26] = REG(EXREGS10); REG 49 tools/perf/arch/csky/util/unwind-libdw.c dwarf_regs[27] = REG(EXREGS11); REG 50 tools/perf/arch/csky/util/unwind-libdw.c dwarf_regs[28] = REG(EXREGS12); REG 51 tools/perf/arch/csky/util/unwind-libdw.c dwarf_regs[29] = REG(EXREGS13); REG 52 tools/perf/arch/csky/util/unwind-libdw.c dwarf_regs[30] = REG(EXREGS14); REG 53 tools/perf/arch/csky/util/unwind-libdw.c dwarf_regs[31] = REG(TLS); REG 54 tools/perf/arch/csky/util/unwind-libdw.c dwarf_regs[32] = REG(PC); REG 56 tools/perf/arch/csky/util/unwind-libdw.c dwarf_regs[0] = REG(SP); REG 57 tools/perf/arch/csky/util/unwind-libdw.c dwarf_regs[1] = REG(REGS9); REG 58 tools/perf/arch/csky/util/unwind-libdw.c dwarf_regs[2] = REG(A0); REG 59 tools/perf/arch/csky/util/unwind-libdw.c dwarf_regs[3] = REG(A1); REG 60 tools/perf/arch/csky/util/unwind-libdw.c dwarf_regs[4] = REG(A2); REG 61 tools/perf/arch/csky/util/unwind-libdw.c dwarf_regs[5] = REG(A3); REG 62 tools/perf/arch/csky/util/unwind-libdw.c dwarf_regs[6] = REG(REGS0); REG 63 tools/perf/arch/csky/util/unwind-libdw.c dwarf_regs[7] = REG(REGS1); REG 64 tools/perf/arch/csky/util/unwind-libdw.c dwarf_regs[8] = REG(REGS2); REG 65 tools/perf/arch/csky/util/unwind-libdw.c dwarf_regs[9] = REG(REGS3); REG 66 tools/perf/arch/csky/util/unwind-libdw.c dwarf_regs[10] = REG(REGS4); REG 67 tools/perf/arch/csky/util/unwind-libdw.c dwarf_regs[11] = REG(REGS5); REG 68 tools/perf/arch/csky/util/unwind-libdw.c dwarf_regs[12] = REG(REGS6); REG 69 tools/perf/arch/csky/util/unwind-libdw.c dwarf_regs[13] = REG(REGS7); REG 70 tools/perf/arch/csky/util/unwind-libdw.c dwarf_regs[14] = REG(REGS8); REG 71 tools/perf/arch/csky/util/unwind-libdw.c dwarf_regs[15] = REG(LR); REG 73 tools/perf/arch/csky/util/unwind-libdw.c dwfl_thread_state_register_pc(thread, REG(PC)); REG 28 tools/perf/arch/powerpc/util/unwind-libdw.c dwarf_regs[0] = REG(R0); REG 29 tools/perf/arch/powerpc/util/unwind-libdw.c dwarf_regs[1] = REG(R1); REG 30 tools/perf/arch/powerpc/util/unwind-libdw.c dwarf_regs[2] = REG(R2); REG 31 tools/perf/arch/powerpc/util/unwind-libdw.c dwarf_regs[3] = REG(R3); REG 32 tools/perf/arch/powerpc/util/unwind-libdw.c dwarf_regs[4] = REG(R4); REG 33 tools/perf/arch/powerpc/util/unwind-libdw.c dwarf_regs[5] = REG(R5); REG 34 tools/perf/arch/powerpc/util/unwind-libdw.c dwarf_regs[6] = REG(R6); REG 35 tools/perf/arch/powerpc/util/unwind-libdw.c dwarf_regs[7] = REG(R7); REG 36 tools/perf/arch/powerpc/util/unwind-libdw.c dwarf_regs[8] = REG(R8); REG 37 tools/perf/arch/powerpc/util/unwind-libdw.c dwarf_regs[9] = REG(R9); REG 38 tools/perf/arch/powerpc/util/unwind-libdw.c dwarf_regs[10] = REG(R10); REG 39 tools/perf/arch/powerpc/util/unwind-libdw.c dwarf_regs[11] = REG(R11); REG 40 tools/perf/arch/powerpc/util/unwind-libdw.c dwarf_regs[12] = REG(R12); REG 41 tools/perf/arch/powerpc/util/unwind-libdw.c dwarf_regs[13] = REG(R13); REG 42 tools/perf/arch/powerpc/util/unwind-libdw.c dwarf_regs[14] = REG(R14); REG 43 tools/perf/arch/powerpc/util/unwind-libdw.c dwarf_regs[15] = REG(R15); REG 44 tools/perf/arch/powerpc/util/unwind-libdw.c dwarf_regs[16] = REG(R16); REG 45 tools/perf/arch/powerpc/util/unwind-libdw.c dwarf_regs[17] = REG(R17); REG 46 tools/perf/arch/powerpc/util/unwind-libdw.c dwarf_regs[18] = REG(R18); REG 47 tools/perf/arch/powerpc/util/unwind-libdw.c dwarf_regs[19] = REG(R19); REG 48 tools/perf/arch/powerpc/util/unwind-libdw.c dwarf_regs[20] = REG(R20); REG 49 tools/perf/arch/powerpc/util/unwind-libdw.c dwarf_regs[21] = REG(R21); REG 50 tools/perf/arch/powerpc/util/unwind-libdw.c dwarf_regs[22] = REG(R22); REG 51 tools/perf/arch/powerpc/util/unwind-libdw.c dwarf_regs[23] = REG(R23); REG 52 tools/perf/arch/powerpc/util/unwind-libdw.c dwarf_regs[24] = REG(R24); REG 53 tools/perf/arch/powerpc/util/unwind-libdw.c dwarf_regs[25] = REG(R25); REG 54 tools/perf/arch/powerpc/util/unwind-libdw.c dwarf_regs[26] = REG(R26); REG 55 tools/perf/arch/powerpc/util/unwind-libdw.c dwarf_regs[27] = REG(R27); REG 56 tools/perf/arch/powerpc/util/unwind-libdw.c dwarf_regs[28] = REG(R28); REG 57 tools/perf/arch/powerpc/util/unwind-libdw.c dwarf_regs[29] = REG(R29); REG 58 tools/perf/arch/powerpc/util/unwind-libdw.c dwarf_regs[30] = REG(R30); REG 59 tools/perf/arch/powerpc/util/unwind-libdw.c dwarf_regs[31] = REG(R31); REG 63 tools/perf/arch/powerpc/util/unwind-libdw.c dwarf_nip = REG(NIP); REG 22 tools/perf/arch/riscv/util/unwind-libdw.c dwarf_regs[1] = REG(RA); REG 23 tools/perf/arch/riscv/util/unwind-libdw.c dwarf_regs[2] = REG(SP); REG 24 tools/perf/arch/riscv/util/unwind-libdw.c dwarf_regs[3] = REG(GP); REG 25 tools/perf/arch/riscv/util/unwind-libdw.c dwarf_regs[4] = REG(TP); REG 26 tools/perf/arch/riscv/util/unwind-libdw.c dwarf_regs[5] = REG(T0); REG 27 tools/perf/arch/riscv/util/unwind-libdw.c dwarf_regs[6] = REG(T1); REG 28 tools/perf/arch/riscv/util/unwind-libdw.c dwarf_regs[7] = REG(T2); REG 29 tools/perf/arch/riscv/util/unwind-libdw.c dwarf_regs[8] = REG(S0); REG 30 tools/perf/arch/riscv/util/unwind-libdw.c dwarf_regs[9] = REG(S1); REG 31 tools/perf/arch/riscv/util/unwind-libdw.c dwarf_regs[10] = REG(A0); REG 32 tools/perf/arch/riscv/util/unwind-libdw.c dwarf_regs[11] = REG(A1); REG 33 tools/perf/arch/riscv/util/unwind-libdw.c dwarf_regs[12] = REG(A2); REG 34 tools/perf/arch/riscv/util/unwind-libdw.c dwarf_regs[13] = REG(A3); REG 35 tools/perf/arch/riscv/util/unwind-libdw.c dwarf_regs[14] = REG(A4); REG 36 tools/perf/arch/riscv/util/unwind-libdw.c dwarf_regs[15] = REG(A5); REG 37 tools/perf/arch/riscv/util/unwind-libdw.c dwarf_regs[16] = REG(A6); REG 38 tools/perf/arch/riscv/util/unwind-libdw.c dwarf_regs[17] = REG(A7); REG 39 tools/perf/arch/riscv/util/unwind-libdw.c dwarf_regs[18] = REG(S2); REG 40 tools/perf/arch/riscv/util/unwind-libdw.c dwarf_regs[19] = REG(S3); REG 41 tools/perf/arch/riscv/util/unwind-libdw.c dwarf_regs[20] = REG(S4); REG 42 tools/perf/arch/riscv/util/unwind-libdw.c dwarf_regs[21] = REG(S5); REG 43 tools/perf/arch/riscv/util/unwind-libdw.c dwarf_regs[22] = REG(S6); REG 44 tools/perf/arch/riscv/util/unwind-libdw.c dwarf_regs[23] = REG(S7); REG 45 tools/perf/arch/riscv/util/unwind-libdw.c dwarf_regs[24] = REG(S8); REG 46 tools/perf/arch/riscv/util/unwind-libdw.c dwarf_regs[25] = REG(S9); REG 47 tools/perf/arch/riscv/util/unwind-libdw.c dwarf_regs[26] = REG(S10); REG 48 tools/perf/arch/riscv/util/unwind-libdw.c dwarf_regs[27] = REG(S11); REG 49 tools/perf/arch/riscv/util/unwind-libdw.c dwarf_regs[28] = REG(T3); REG 50 tools/perf/arch/riscv/util/unwind-libdw.c dwarf_regs[29] = REG(T4); REG 51 tools/perf/arch/riscv/util/unwind-libdw.c dwarf_regs[30] = REG(T5); REG 52 tools/perf/arch/riscv/util/unwind-libdw.c dwarf_regs[31] = REG(T6); REG 53 tools/perf/arch/riscv/util/unwind-libdw.c dwfl_thread_state_register_pc(thread, REG(PC)); REG 24 tools/perf/arch/s390/util/unwind-libdw.c dwarf_regs[0] = REG(R0); REG 25 tools/perf/arch/s390/util/unwind-libdw.c dwarf_regs[1] = REG(R1); REG 26 tools/perf/arch/s390/util/unwind-libdw.c dwarf_regs[2] = REG(R2); REG 27 tools/perf/arch/s390/util/unwind-libdw.c dwarf_regs[3] = REG(R3); REG 28 tools/perf/arch/s390/util/unwind-libdw.c dwarf_regs[4] = REG(R4); REG 29 tools/perf/arch/s390/util/unwind-libdw.c dwarf_regs[5] = REG(R5); REG 30 tools/perf/arch/s390/util/unwind-libdw.c dwarf_regs[6] = REG(R6); REG 31 tools/perf/arch/s390/util/unwind-libdw.c dwarf_regs[7] = REG(R7); REG 32 tools/perf/arch/s390/util/unwind-libdw.c dwarf_regs[8] = REG(R8); REG 33 tools/perf/arch/s390/util/unwind-libdw.c dwarf_regs[9] = REG(R9); REG 34 tools/perf/arch/s390/util/unwind-libdw.c dwarf_regs[10] = REG(R10); REG 35 tools/perf/arch/s390/util/unwind-libdw.c dwarf_regs[11] = REG(R11); REG 36 tools/perf/arch/s390/util/unwind-libdw.c dwarf_regs[12] = REG(R12); REG 37 tools/perf/arch/s390/util/unwind-libdw.c dwarf_regs[13] = REG(R13); REG 38 tools/perf/arch/s390/util/unwind-libdw.c dwarf_regs[14] = REG(R14); REG 39 tools/perf/arch/s390/util/unwind-libdw.c dwarf_regs[15] = REG(R15); REG 41 tools/perf/arch/s390/util/unwind-libdw.c dwarf_regs[16] = REG(FP0); REG 42 tools/perf/arch/s390/util/unwind-libdw.c dwarf_regs[17] = REG(FP2); REG 43 tools/perf/arch/s390/util/unwind-libdw.c dwarf_regs[18] = REG(FP4); REG 44 tools/perf/arch/s390/util/unwind-libdw.c dwarf_regs[19] = REG(FP6); REG 45 tools/perf/arch/s390/util/unwind-libdw.c dwarf_regs[20] = REG(FP1); REG 46 tools/perf/arch/s390/util/unwind-libdw.c dwarf_regs[21] = REG(FP3); REG 47 tools/perf/arch/s390/util/unwind-libdw.c dwarf_regs[22] = REG(FP5); REG 48 tools/perf/arch/s390/util/unwind-libdw.c dwarf_regs[23] = REG(FP7); REG 49 tools/perf/arch/s390/util/unwind-libdw.c dwarf_regs[24] = REG(FP8); REG 50 tools/perf/arch/s390/util/unwind-libdw.c dwarf_regs[25] = REG(FP10); REG 51 tools/perf/arch/s390/util/unwind-libdw.c dwarf_regs[26] = REG(FP12); REG 52 tools/perf/arch/s390/util/unwind-libdw.c dwarf_regs[27] = REG(FP14); REG 53 tools/perf/arch/s390/util/unwind-libdw.c dwarf_regs[28] = REG(FP9); REG 54 tools/perf/arch/s390/util/unwind-libdw.c dwarf_regs[29] = REG(FP11); REG 55 tools/perf/arch/s390/util/unwind-libdw.c dwarf_regs[30] = REG(FP13); REG 56 tools/perf/arch/s390/util/unwind-libdw.c dwarf_regs[31] = REG(FP15); REG 58 tools/perf/arch/s390/util/unwind-libdw.c dwarf_regs[64] = REG(MASK); REG 59 tools/perf/arch/s390/util/unwind-libdw.c dwarf_regs[65] = REG(PC); REG 21 tools/perf/arch/x86/util/unwind-libdw.c dwarf_regs[0] = REG(AX); REG 22 tools/perf/arch/x86/util/unwind-libdw.c dwarf_regs[1] = REG(CX); REG 23 tools/perf/arch/x86/util/unwind-libdw.c dwarf_regs[2] = REG(DX); REG 24 tools/perf/arch/x86/util/unwind-libdw.c dwarf_regs[3] = REG(BX); REG 25 tools/perf/arch/x86/util/unwind-libdw.c dwarf_regs[4] = REG(SP); REG 26 tools/perf/arch/x86/util/unwind-libdw.c dwarf_regs[5] = REG(BP); REG 27 tools/perf/arch/x86/util/unwind-libdw.c dwarf_regs[6] = REG(SI); REG 28 tools/perf/arch/x86/util/unwind-libdw.c dwarf_regs[7] = REG(DI); REG 29 tools/perf/arch/x86/util/unwind-libdw.c dwarf_regs[8] = REG(IP); REG 32 tools/perf/arch/x86/util/unwind-libdw.c dwarf_regs[0] = REG(AX); REG 33 tools/perf/arch/x86/util/unwind-libdw.c dwarf_regs[1] = REG(DX); REG 34 tools/perf/arch/x86/util/unwind-libdw.c dwarf_regs[2] = REG(CX); REG 35 tools/perf/arch/x86/util/unwind-libdw.c dwarf_regs[3] = REG(BX); REG 36 tools/perf/arch/x86/util/unwind-libdw.c dwarf_regs[4] = REG(SI); REG 37 tools/perf/arch/x86/util/unwind-libdw.c dwarf_regs[5] = REG(DI); REG 38 tools/perf/arch/x86/util/unwind-libdw.c dwarf_regs[6] = REG(BP); REG 39 tools/perf/arch/x86/util/unwind-libdw.c dwarf_regs[7] = REG(SP); REG 40 tools/perf/arch/x86/util/unwind-libdw.c dwarf_regs[8] = REG(R8); REG 41 tools/perf/arch/x86/util/unwind-libdw.c dwarf_regs[9] = REG(R9); REG 42 tools/perf/arch/x86/util/unwind-libdw.c dwarf_regs[10] = REG(R10); REG 43 tools/perf/arch/x86/util/unwind-libdw.c dwarf_regs[11] = REG(R11); REG 44 tools/perf/arch/x86/util/unwind-libdw.c dwarf_regs[12] = REG(R12); REG 45 tools/perf/arch/x86/util/unwind-libdw.c dwarf_regs[13] = REG(R13); REG 46 tools/perf/arch/x86/util/unwind-libdw.c dwarf_regs[14] = REG(R14); REG 47 tools/perf/arch/x86/util/unwind-libdw.c dwarf_regs[15] = REG(R15); REG 48 tools/perf/arch/x86/util/unwind-libdw.c dwarf_regs[16] = REG(IP);