READ_REG32        207 drivers/parisc/lba_pci.c     error_config = READ_REG32(d->hba.base_addr + LBA_ERROR_CONFIG);		\
READ_REG32        210 drivers/parisc/lba_pci.c     status_control = READ_REG32(d->hba.base_addr + LBA_STAT_CTL);		\
READ_REG32        216 drivers/parisc/lba_pci.c 	arb_mask = READ_REG32(d->hba.base_addr + LBA_ARB_MASK);		\
READ_REG32        242 drivers/parisc/lba_pci.c     lba_t32 = READ_REG32((d)->hba.base_addr + LBA_PCI_CFG_ADDR);	\
READ_REG32        252 drivers/parisc/lba_pci.c     lba_t32 = READ_REG32((d)->hba.base_addr + LBA_PCI_CFG_ADDR);	\
READ_REG32        290 drivers/parisc/lba_pci.c     error_status = READ_REG32(base + LBA_ERROR_STATUS);		\
READ_REG32        315 drivers/parisc/lba_pci.c     lba_t32 = READ_REG32((d)->hba.base_addr + LBA_PCI_CFG_ADDR);	\
READ_REG32        355 drivers/parisc/lba_pci.c 		case 4: data = READ_REG32(data_reg); break;
READ_REG32        397 drivers/parisc/lba_pci.c 	case 4: *data = READ_REG32(data_reg); break;
READ_REG32        464 drivers/parisc/lba_pci.c 	lba_t32 = READ_REG32(d->hba.base_addr + LBA_PCI_CFG_ADDR);
READ_REG32        499 drivers/parisc/lba_pci.c 		*data = READ_REG32(data_reg);             break;
READ_REG32       1083 drivers/parisc/lba_pci.c 				lba_len = ~READ_REG32(lba_dev->hba.base_addr
READ_REG32       1186 drivers/parisc/lba_pci.c 	lba_num = READ_REG32(lba_dev->hba.base_addr + LBA_FW_SCRATCH);
READ_REG32       1268 drivers/parisc/lba_pci.c 	r->start = READ_REG32(lba_dev->hba.base_addr + LBA_LMMIO_BASE);
READ_REG32       1276 drivers/parisc/lba_pci.c 		rsize = ~ READ_REG32(lba_dev->hba.base_addr + LBA_LMMIO_MASK);
READ_REG32       1314 drivers/parisc/lba_pci.c 	r->start = READ_REG32(lba_dev->hba.base_addr + LBA_ELMMIO_BASE);
READ_REG32       1322 drivers/parisc/lba_pci.c 		rsize = READ_REG32(lba_dev->hba.base_addr + LBA_ELMMIO_MASK);
READ_REG32       1332 drivers/parisc/lba_pci.c 	r->start = READ_REG32(lba_dev->hba.base_addr + LBA_IOS_BASE) & ~1L;
READ_REG32       1333 drivers/parisc/lba_pci.c 	r->end   = r->start + (READ_REG32(lba_dev->hba.base_addr + LBA_IOS_MASK) ^ (HBA_PORT_SPACE_SIZE - 1));
READ_REG32       1391 drivers/parisc/lba_pci.c 	bus_reset = READ_REG32(d->hba.base_addr + LBA_STAT_CTL + 4) & 1;
READ_REG32       1396 drivers/parisc/lba_pci.c 	stat = READ_REG32(d->hba.base_addr + LBA_ERROR_CONFIG);
READ_REG32       1418 drivers/parisc/lba_pci.c         stat = READ_REG32(d->hba.base_addr + LBA_STAT_CTL);
READ_REG32       1433 drivers/parisc/lba_pci.c 	if (0 == READ_REG32(d->hba.base_addr + LBA_ARB_MASK)) {
READ_REG32       1483 drivers/parisc/lba_pci.c 	func_class = READ_REG32(addr + LBA_FCLASS);
READ_REG32        137 drivers/parisc/sba_iommu.c #define READ_REG(addr)		READ_REG32(addr)
READ_REG32       1796 drivers/parisc/sba_iommu.c 		   READ_REG32(sba_dev->sba_hpa + LMMIO_DIST_BASE),
READ_REG32       1797 drivers/parisc/sba_iommu.c 		   READ_REG32(sba_dev->sba_hpa + LMMIO_DIST_MASK),
READ_REG32       1798 drivers/parisc/sba_iommu.c 		   READ_REG32(sba_dev->sba_hpa + LMMIO_DIST_ROUTE));
READ_REG32       1803 drivers/parisc/sba_iommu.c 			   READ_REG32(sba_dev->sba_hpa + LMMIO_DIRECT0_BASE  + i*0x18),
READ_REG32       1804 drivers/parisc/sba_iommu.c 			   READ_REG32(sba_dev->sba_hpa + LMMIO_DIRECT0_MASK  + i*0x18),
READ_REG32       1805 drivers/parisc/sba_iommu.c 			   READ_REG32(sba_dev->sba_hpa + LMMIO_DIRECT0_ROUTE + i*0x18));
READ_REG32       2029 drivers/parisc/sba_iommu.c 		base = READ_REG32(reg + LMMIO_DIRECT0_BASE);
READ_REG32       2033 drivers/parisc/sba_iommu.c 		size = READ_REG32(reg + LMMIO_DIRECT0_ROUTE);
READ_REG32       2039 drivers/parisc/sba_iommu.c 		size = ~ READ_REG32(reg + LMMIO_DIRECT0_MASK);
READ_REG32       2067 drivers/parisc/sba_iommu.c 	base = READ_REG32(sba->sba_hpa + LMMIO_DIST_BASE);
READ_REG32       2075 drivers/parisc/sba_iommu.c 	size = (~READ_REG32(sba->sba_hpa + LMMIO_DIST_MASK)) / ROPES_PER_IOC;