RCS0 1353 drivers/gpu/drm/i915/display/intel_overlay.c if (!HAS_ENGINE(dev_priv, RCS0)) RCS0 1361 drivers/gpu/drm/i915/display/intel_overlay.c overlay->context = dev_priv->engine[RCS0]->kernel_context; RCS0 1943 drivers/gpu/drm/i915/gem/i915_gem_execbuffer.c if (!IS_GEN(rq->i915, 7) || rq->engine->id != RCS0) { RCS0 2133 drivers/gpu/drm/i915/gem/i915_gem_execbuffer.c [I915_EXEC_DEFAULT] = RCS0, RCS0 2134 drivers/gpu/drm/i915/gem/i915_gem_execbuffer.c [I915_EXEC_RENDER] = RCS0, RCS0 199 drivers/gpu/drm/i915/gem/selftests/i915_gem_coherency.c rq = i915_request_create(i915->engine[RCS0]->kernel_context); RCS0 257 drivers/gpu/drm/i915/gem/selftests/i915_gem_coherency.c if (!HAS_ENGINE(i915, RCS0)) RCS0 260 drivers/gpu/drm/i915/gem/selftests/i915_gem_coherency.c return intel_engine_can_store_dword(i915->engine[RCS0]); RCS0 911 drivers/gpu/drm/i915/gem/selftests/i915_gem_context.c struct intel_engine_cs *engine = i915->engine[RCS0]; RCS0 963 drivers/gpu/drm/i915/gem/selftests/i915_gem_context.c ce = i915_gem_context_get_engine(ctx, RCS0); RCS0 1546 drivers/gpu/drm/i915/gem/selftests/i915_gem_context.c rq = igt_request_alloc(ctx, i915->engine[RCS0]); RCS0 1554 drivers/gpu/drm/i915/gem/selftests/i915_gem_context.c context_barrier_inject_fault = BIT(RCS0); RCS0 71 drivers/gpu/drm/i915/gt/intel_engine_cs.c [RCS0] = { RCS0 963 drivers/gpu/drm/i915/gt/intel_engine_cs.c if (engine->id != RCS0) RCS0 981 drivers/gpu/drm/i915/gt/intel_engine_cs.c if (engine->id != RCS0) RCS0 997 drivers/gpu/drm/i915/gt/intel_engine_cs.c if (engine->id == RCS0) RCS0 156 drivers/gpu/drm/i915/gt/intel_engine_user.c [RENDER_CLASS] = { RCS0, 1 }, RCS0 3065 drivers/gpu/drm/i915/gt/intel_lrc.c [RCS0] = GEN8_RCS_IRQ_SHIFT, RCS0 329 drivers/gpu/drm/i915/gt/intel_mocs.c case RCS0: RCS0 287 drivers/gpu/drm/i915/gt/intel_reset.c [RCS0] = GEN6_GRDOM_RENDER, RCS0 410 drivers/gpu/drm/i915/gt/intel_reset.c [RCS0] = GEN11_GRDOM_RENDER, RCS0 549 drivers/gpu/drm/i915/gt/intel_ringbuffer.c case RCS0: RCS0 1785 drivers/gpu/drm/i915/gt/intel_ringbuffer.c GEM_BUG_ON(engine->id != RCS0); RCS0 1050 drivers/gpu/drm/i915/gt/selftest_hangcheck.c struct intel_engine_cs *engine = gt->i915->engine[RCS0]; RCS0 1186 drivers/gpu/drm/i915/gt/selftest_hangcheck.c struct intel_engine_cs *engine = gt->i915->engine[RCS0]; RCS0 1542 drivers/gpu/drm/i915/gt/selftest_hangcheck.c struct intel_engine_cs *engine = gt->i915->engine[RCS0]; RCS0 732 drivers/gpu/drm/i915/gt/selftest_workarounds.c struct intel_engine_cs *engine = i915->engine[RCS0]; RCS0 410 drivers/gpu/drm/i915/gvt/cmd_parser.c #define R_RCS BIT(RCS0) RCS0 580 drivers/gpu/drm/i915/gvt/cmd_parser.c [RCS0] = { RCS0 980 drivers/gpu/drm/i915/gvt/cmd_parser.c if (IS_BROADWELL(gvt->dev_priv) && s->ring_id != RCS0) { RCS0 1081 drivers/gpu/drm/i915/gvt/cmd_parser.c [RCS0] = { RCS0 50 drivers/gpu/drm/i915/gvt/execlist.c [RCS0] = RCS_AS_CONTEXT_SWITCH, RCS0 326 drivers/gpu/drm/i915/gvt/handlers.c engine_mask |= BIT(RCS0); RCS0 1756 drivers/gpu/drm/i915/gvt/handlers.c id = RCS0; RCS0 45 drivers/gpu/drm/i915/gvt/mmio_context.c {RCS0, GFX_MODE_GEN7, 0xffff, false}, /* 0x229c */ RCS0 46 drivers/gpu/drm/i915/gvt/mmio_context.c {RCS0, GEN9_CTX_PREEMPT_REG, 0x0, false}, /* 0x2248 */ RCS0 47 drivers/gpu/drm/i915/gvt/mmio_context.c {RCS0, HWSTAM, 0x0, false}, /* 0x2098 */ RCS0 48 drivers/gpu/drm/i915/gvt/mmio_context.c {RCS0, INSTPM, 0xffff, true}, /* 0x20c0 */ RCS0 49 drivers/gpu/drm/i915/gvt/mmio_context.c {RCS0, RING_FORCE_TO_NONPRIV(RENDER_RING_BASE, 0), 0, false}, /* 0x24d0 */ RCS0 50 drivers/gpu/drm/i915/gvt/mmio_context.c {RCS0, RING_FORCE_TO_NONPRIV(RENDER_RING_BASE, 1), 0, false}, /* 0x24d4 */ RCS0 51 drivers/gpu/drm/i915/gvt/mmio_context.c {RCS0, RING_FORCE_TO_NONPRIV(RENDER_RING_BASE, 2), 0, false}, /* 0x24d8 */ RCS0 52 drivers/gpu/drm/i915/gvt/mmio_context.c {RCS0, RING_FORCE_TO_NONPRIV(RENDER_RING_BASE, 3), 0, false}, /* 0x24dc */ RCS0 53 drivers/gpu/drm/i915/gvt/mmio_context.c {RCS0, RING_FORCE_TO_NONPRIV(RENDER_RING_BASE, 4), 0, false}, /* 0x24e0 */ RCS0 54 drivers/gpu/drm/i915/gvt/mmio_context.c {RCS0, RING_FORCE_TO_NONPRIV(RENDER_RING_BASE, 5), 0, false}, /* 0x24e4 */ RCS0 55 drivers/gpu/drm/i915/gvt/mmio_context.c {RCS0, RING_FORCE_TO_NONPRIV(RENDER_RING_BASE, 6), 0, false}, /* 0x24e8 */ RCS0 56 drivers/gpu/drm/i915/gvt/mmio_context.c {RCS0, RING_FORCE_TO_NONPRIV(RENDER_RING_BASE, 7), 0, false}, /* 0x24ec */ RCS0 57 drivers/gpu/drm/i915/gvt/mmio_context.c {RCS0, RING_FORCE_TO_NONPRIV(RENDER_RING_BASE, 8), 0, false}, /* 0x24f0 */ RCS0 58 drivers/gpu/drm/i915/gvt/mmio_context.c {RCS0, RING_FORCE_TO_NONPRIV(RENDER_RING_BASE, 9), 0, false}, /* 0x24f4 */ RCS0 59 drivers/gpu/drm/i915/gvt/mmio_context.c {RCS0, RING_FORCE_TO_NONPRIV(RENDER_RING_BASE, 10), 0, false}, /* 0x24f8 */ RCS0 60 drivers/gpu/drm/i915/gvt/mmio_context.c {RCS0, RING_FORCE_TO_NONPRIV(RENDER_RING_BASE, 11), 0, false}, /* 0x24fc */ RCS0 61 drivers/gpu/drm/i915/gvt/mmio_context.c {RCS0, CACHE_MODE_1, 0xffff, true}, /* 0x7004 */ RCS0 62 drivers/gpu/drm/i915/gvt/mmio_context.c {RCS0, GEN7_GT_MODE, 0xffff, true}, /* 0x7008 */ RCS0 63 drivers/gpu/drm/i915/gvt/mmio_context.c {RCS0, CACHE_MODE_0_GEN7, 0xffff, true}, /* 0x7000 */ RCS0 64 drivers/gpu/drm/i915/gvt/mmio_context.c {RCS0, GEN7_COMMON_SLICE_CHICKEN1, 0xffff, true}, /* 0x7010 */ RCS0 65 drivers/gpu/drm/i915/gvt/mmio_context.c {RCS0, HDC_CHICKEN0, 0xffff, true}, /* 0x7300 */ RCS0 66 drivers/gpu/drm/i915/gvt/mmio_context.c {RCS0, VF_GUARDBAND, 0xffff, true}, /* 0x83a4 */ RCS0 73 drivers/gpu/drm/i915/gvt/mmio_context.c {RCS0, INVALID_MMIO_REG, 0, false } /* Terminated */ RCS0 77 drivers/gpu/drm/i915/gvt/mmio_context.c {RCS0, GFX_MODE_GEN7, 0xffff, false}, /* 0x229c */ RCS0 78 drivers/gpu/drm/i915/gvt/mmio_context.c {RCS0, GEN9_CTX_PREEMPT_REG, 0x0, false}, /* 0x2248 */ RCS0 79 drivers/gpu/drm/i915/gvt/mmio_context.c {RCS0, HWSTAM, 0x0, false}, /* 0x2098 */ RCS0 80 drivers/gpu/drm/i915/gvt/mmio_context.c {RCS0, INSTPM, 0xffff, true}, /* 0x20c0 */ RCS0 81 drivers/gpu/drm/i915/gvt/mmio_context.c {RCS0, RING_FORCE_TO_NONPRIV(RENDER_RING_BASE, 0), 0, false}, /* 0x24d0 */ RCS0 82 drivers/gpu/drm/i915/gvt/mmio_context.c {RCS0, RING_FORCE_TO_NONPRIV(RENDER_RING_BASE, 1), 0, false}, /* 0x24d4 */ RCS0 83 drivers/gpu/drm/i915/gvt/mmio_context.c {RCS0, RING_FORCE_TO_NONPRIV(RENDER_RING_BASE, 2), 0, false}, /* 0x24d8 */ RCS0 84 drivers/gpu/drm/i915/gvt/mmio_context.c {RCS0, RING_FORCE_TO_NONPRIV(RENDER_RING_BASE, 3), 0, false}, /* 0x24dc */ RCS0 85 drivers/gpu/drm/i915/gvt/mmio_context.c {RCS0, RING_FORCE_TO_NONPRIV(RENDER_RING_BASE, 4), 0, false}, /* 0x24e0 */ RCS0 86 drivers/gpu/drm/i915/gvt/mmio_context.c {RCS0, RING_FORCE_TO_NONPRIV(RENDER_RING_BASE, 5), 0, false}, /* 0x24e4 */ RCS0 87 drivers/gpu/drm/i915/gvt/mmio_context.c {RCS0, RING_FORCE_TO_NONPRIV(RENDER_RING_BASE, 6), 0, false}, /* 0x24e8 */ RCS0 88 drivers/gpu/drm/i915/gvt/mmio_context.c {RCS0, RING_FORCE_TO_NONPRIV(RENDER_RING_BASE, 7), 0, false}, /* 0x24ec */ RCS0 89 drivers/gpu/drm/i915/gvt/mmio_context.c {RCS0, RING_FORCE_TO_NONPRIV(RENDER_RING_BASE, 8), 0, false}, /* 0x24f0 */ RCS0 90 drivers/gpu/drm/i915/gvt/mmio_context.c {RCS0, RING_FORCE_TO_NONPRIV(RENDER_RING_BASE, 9), 0, false}, /* 0x24f4 */ RCS0 91 drivers/gpu/drm/i915/gvt/mmio_context.c {RCS0, RING_FORCE_TO_NONPRIV(RENDER_RING_BASE, 10), 0, false}, /* 0x24f8 */ RCS0 92 drivers/gpu/drm/i915/gvt/mmio_context.c {RCS0, RING_FORCE_TO_NONPRIV(RENDER_RING_BASE, 11), 0, false}, /* 0x24fc */ RCS0 93 drivers/gpu/drm/i915/gvt/mmio_context.c {RCS0, CACHE_MODE_1, 0xffff, true}, /* 0x7004 */ RCS0 94 drivers/gpu/drm/i915/gvt/mmio_context.c {RCS0, GEN7_GT_MODE, 0xffff, true}, /* 0x7008 */ RCS0 95 drivers/gpu/drm/i915/gvt/mmio_context.c {RCS0, CACHE_MODE_0_GEN7, 0xffff, true}, /* 0x7000 */ RCS0 96 drivers/gpu/drm/i915/gvt/mmio_context.c {RCS0, GEN7_COMMON_SLICE_CHICKEN1, 0xffff, true}, /* 0x7010 */ RCS0 97 drivers/gpu/drm/i915/gvt/mmio_context.c {RCS0, HDC_CHICKEN0, 0xffff, true}, /* 0x7300 */ RCS0 98 drivers/gpu/drm/i915/gvt/mmio_context.c {RCS0, VF_GUARDBAND, 0xffff, true}, /* 0x83a4 */ RCS0 100 drivers/gpu/drm/i915/gvt/mmio_context.c {RCS0, GEN8_PRIVATE_PAT_LO, 0, false}, /* 0x40e0 */ RCS0 101 drivers/gpu/drm/i915/gvt/mmio_context.c {RCS0, GEN8_PRIVATE_PAT_HI, 0, false}, /* 0x40e4 */ RCS0 102 drivers/gpu/drm/i915/gvt/mmio_context.c {RCS0, GEN8_CS_CHICKEN1, 0xffff, true}, /* 0x2580 */ RCS0 103 drivers/gpu/drm/i915/gvt/mmio_context.c {RCS0, COMMON_SLICE_CHICKEN2, 0xffff, true}, /* 0x7014 */ RCS0 104 drivers/gpu/drm/i915/gvt/mmio_context.c {RCS0, GEN9_CS_DEBUG_MODE1, 0xffff, false}, /* 0x20ec */ RCS0 105 drivers/gpu/drm/i915/gvt/mmio_context.c {RCS0, GEN8_L3SQCREG4, 0, false}, /* 0xb118 */ RCS0 106 drivers/gpu/drm/i915/gvt/mmio_context.c {RCS0, GEN7_HALF_SLICE_CHICKEN1, 0xffff, true}, /* 0xe100 */ RCS0 107 drivers/gpu/drm/i915/gvt/mmio_context.c {RCS0, HALF_SLICE_CHICKEN2, 0xffff, true}, /* 0xe180 */ RCS0 108 drivers/gpu/drm/i915/gvt/mmio_context.c {RCS0, HALF_SLICE_CHICKEN3, 0xffff, true}, /* 0xe184 */ RCS0 109 drivers/gpu/drm/i915/gvt/mmio_context.c {RCS0, GEN9_HALF_SLICE_CHICKEN5, 0xffff, true}, /* 0xe188 */ RCS0 110 drivers/gpu/drm/i915/gvt/mmio_context.c {RCS0, GEN9_HALF_SLICE_CHICKEN7, 0xffff, true}, /* 0xe194 */ RCS0 111 drivers/gpu/drm/i915/gvt/mmio_context.c {RCS0, GEN8_ROW_CHICKEN, 0xffff, true}, /* 0xe4f0 */ RCS0 112 drivers/gpu/drm/i915/gvt/mmio_context.c {RCS0, TRVATTL3PTRDW(0), 0, true}, /* 0x4de0 */ RCS0 113 drivers/gpu/drm/i915/gvt/mmio_context.c {RCS0, TRVATTL3PTRDW(1), 0, true}, /* 0x4de4 */ RCS0 114 drivers/gpu/drm/i915/gvt/mmio_context.c {RCS0, TRNULLDETCT, 0, true}, /* 0x4de8 */ RCS0 115 drivers/gpu/drm/i915/gvt/mmio_context.c {RCS0, TRINVTILEDETCT, 0, true}, /* 0x4dec */ RCS0 116 drivers/gpu/drm/i915/gvt/mmio_context.c {RCS0, TRVADR, 0, true}, /* 0x4df0 */ RCS0 117 drivers/gpu/drm/i915/gvt/mmio_context.c {RCS0, TRTTE, 0, true}, /* 0x4df4 */ RCS0 118 drivers/gpu/drm/i915/gvt/mmio_context.c {RCS0, _MMIO(0x4dfc), 0, true}, RCS0 130 drivers/gpu/drm/i915/gvt/mmio_context.c {RCS0, GEN8_HDC_CHICKEN1, 0xffff, true}, /* 0x7304 */ RCS0 131 drivers/gpu/drm/i915/gvt/mmio_context.c {RCS0, GEN9_CTX_PREEMPT_REG, 0x0, false}, /* 0x2248 */ RCS0 132 drivers/gpu/drm/i915/gvt/mmio_context.c {RCS0, GEN7_UCGCTL4, 0x0, false}, /* 0x940c */ RCS0 133 drivers/gpu/drm/i915/gvt/mmio_context.c {RCS0, GAMT_CHKN_BIT_REG, 0x0, false}, /* 0x4ab8 */ RCS0 135 drivers/gpu/drm/i915/gvt/mmio_context.c {RCS0, GEN9_GAMT_ECO_REG_RW_IA, 0x0, false}, /* 0x4ab0 */ RCS0 136 drivers/gpu/drm/i915/gvt/mmio_context.c {RCS0, GEN9_CSFE_CHICKEN1_RCS, 0xffff, false}, /* 0x20d4 */ RCS0 137 drivers/gpu/drm/i915/gvt/mmio_context.c {RCS0, _MMIO(0x20D8), 0xffff, true}, /* 0x20d8 */ RCS0 139 drivers/gpu/drm/i915/gvt/mmio_context.c {RCS0, GEN8_GARBCNTL, 0x0, false}, /* 0xb004 */ RCS0 140 drivers/gpu/drm/i915/gvt/mmio_context.c {RCS0, GEN7_FF_THREAD_MODE, 0x0, false}, /* 0x20a0 */ RCS0 141 drivers/gpu/drm/i915/gvt/mmio_context.c {RCS0, FF_SLICE_CS_CHICKEN2, 0xffff, false}, /* 0x20e4 */ RCS0 142 drivers/gpu/drm/i915/gvt/mmio_context.c {RCS0, INVALID_MMIO_REG, 0, false } /* Terminated */ RCS0 152 drivers/gpu/drm/i915/gvt/mmio_context.c [RCS0] = 0xc800, RCS0 315 drivers/gpu/drm/i915/gvt/mmio_context.c if (req->engine->id != RCS0) RCS0 339 drivers/gpu/drm/i915/gvt/mmio_context.c [RCS0] = 0x4260, RCS0 374 drivers/gpu/drm/i915/gvt/mmio_context.c if (ring_id == RCS0 && INTEL_GEN(dev_priv) >= 9) RCS0 399 drivers/gpu/drm/i915/gvt/mmio_context.c [RCS0] = 0xc800, RCS0 411 drivers/gpu/drm/i915/gvt/mmio_context.c if (ring_id == RCS0 && IS_GEN(dev_priv, 9)) RCS0 434 drivers/gpu/drm/i915/gvt/mmio_context.c if (ring_id == RCS0) { RCS0 100 drivers/gpu/drm/i915/gvt/scheduler.c if (workload->ring_id != RCS0) RCS0 156 drivers/gpu/drm/i915/gvt/scheduler.c if (ring_id == RCS0) { RCS0 184 drivers/gpu/drm/i915/gvt/scheduler.c if (IS_BROADWELL(gvt->dev_priv) && ring_id == RCS0) RCS0 438 drivers/gpu/drm/i915/gvt/scheduler.c if (workload->ring_id == RCS0 && workload->wa_ctx.indirect_ctx.size) { RCS0 837 drivers/gpu/drm/i915/gvt/scheduler.c if (IS_BROADWELL(gvt->dev_priv) && rq->engine->id == RCS0) RCS0 1552 drivers/gpu/drm/i915/gvt/scheduler.c if (ring_id == RCS0) { RCS0 1115 drivers/gpu/drm/i915/i915_gpu_error.c case RCS0: RCS0 4044 drivers/gpu/drm/i915/i915_irq.c intel_engine_breadcrumbs_irq(dev_priv->engine[RCS0]); RCS0 4149 drivers/gpu/drm/i915/i915_irq.c intel_engine_breadcrumbs_irq(dev_priv->engine[RCS0]); RCS0 4291 drivers/gpu/drm/i915/i915_irq.c intel_engine_breadcrumbs_irq(dev_priv->engine[RCS0]); RCS0 158 drivers/gpu/drm/i915/i915_pci.c .engine_mask = BIT(RCS0), \ RCS0 175 drivers/gpu/drm/i915/i915_pci.c .engine_mask = BIT(RCS0), \ RCS0 209 drivers/gpu/drm/i915/i915_pci.c .engine_mask = BIT(RCS0), \ RCS0 294 drivers/gpu/drm/i915/i915_pci.c .engine_mask = BIT(RCS0), \ RCS0 324 drivers/gpu/drm/i915/i915_pci.c .engine_mask = BIT(RCS0) | BIT(VCS0), RCS0 334 drivers/gpu/drm/i915/i915_pci.c .engine_mask = BIT(RCS0) | BIT(VCS0), RCS0 342 drivers/gpu/drm/i915/i915_pci.c .engine_mask = BIT(RCS0) | BIT(VCS0), \ RCS0 369 drivers/gpu/drm/i915/i915_pci.c .engine_mask = BIT(RCS0) | BIT(VCS0) | BIT(BCS0), \ RCS0 417 drivers/gpu/drm/i915/i915_pci.c .engine_mask = BIT(RCS0) | BIT(VCS0) | BIT(BCS0), \ RCS0 483 drivers/gpu/drm/i915/i915_pci.c .engine_mask = BIT(RCS0) | BIT(VCS0) | BIT(BCS0), RCS0 493 drivers/gpu/drm/i915/i915_pci.c .engine_mask = BIT(RCS0) | BIT(VCS0) | BIT(BCS0) | BIT(VECS0), \ RCS0 557 drivers/gpu/drm/i915/i915_pci.c BIT(RCS0) | BIT(VCS0) | BIT(BCS0) | BIT(VECS0) | BIT(VCS1), RCS0 566 drivers/gpu/drm/i915/i915_pci.c .engine_mask = BIT(RCS0) | BIT(VCS0) | BIT(BCS0) | BIT(VECS0), RCS0 616 drivers/gpu/drm/i915/i915_pci.c BIT(RCS0) | BIT(VCS0) | BIT(BCS0) | BIT(VECS0) | BIT(VCS1) RCS0 633 drivers/gpu/drm/i915/i915_pci.c .engine_mask = BIT(RCS0) | BIT(VCS0) | BIT(BCS0) | BIT(VECS0), \ RCS0 690 drivers/gpu/drm/i915/i915_pci.c BIT(RCS0) | BIT(VCS0) | BIT(BCS0) | BIT(VECS0) | BIT(VCS1), RCS0 711 drivers/gpu/drm/i915/i915_pci.c BIT(RCS0) | BIT(VCS0) | BIT(BCS0) | BIT(VECS0) | BIT(VCS1), RCS0 760 drivers/gpu/drm/i915/i915_pci.c BIT(RCS0) | BIT(BCS0) | BIT(VECS0) | BIT(VCS0) | BIT(VCS2), RCS0 767 drivers/gpu/drm/i915/i915_pci.c .engine_mask = BIT(RCS0) | BIT(BCS0) | BIT(VCS0) | BIT(VECS0), RCS0 799 drivers/gpu/drm/i915/i915_pci.c BIT(RCS0) | BIT(BCS0) | BIT(VECS0) | BIT(VCS0) | BIT(VCS2), RCS0 49 drivers/gpu/drm/i915/selftests/i915_request.c request = mock_request(i915->engine[RCS0]->kernel_context, HZ / 10); RCS0 71 drivers/gpu/drm/i915/selftests/i915_request.c request = mock_request(i915->engine[RCS0]->kernel_context, T); RCS0 144 drivers/gpu/drm/i915/selftests/i915_request.c request = mock_request(i915->engine[RCS0]->kernel_context, T); RCS0 202 drivers/gpu/drm/i915/selftests/i915_request.c ce = i915_gem_context_get_engine(ctx[0], RCS0); RCS0 215 drivers/gpu/drm/i915/selftests/i915_request.c ce = i915_gem_context_get_engine(ctx[1], RCS0); RCS0 433 drivers/gpu/drm/i915/selftests/i915_request.c .engine = i915->engine[RCS0], RCS0 205 drivers/gpu/drm/i915/selftests/mock_gem_device.c i915->engine[RCS0] = mock_engine(i915, "mock", RCS0); RCS0 206 drivers/gpu/drm/i915/selftests/mock_gem_device.c if (!i915->engine[RCS0]) RCS0 213 drivers/gpu/drm/i915/selftests/mock_gem_device.c if (mock_engine_init(i915->engine[RCS0])) RCS0 226 drivers/gpu/drm/i915/selftests/mock_gem_device.c mock_engine_free(i915->engine[RCS0]);