RB 994 arch/m68k/kernel/traps.c if (ssw & RB) RB 475 arch/nds32/mm/alignment.c shift = *idx_to_addr(regs, RB(inst)) << SV(inst); RB 546 arch/powerpc/xmon/ppc-opc.c #define RBS RB + 1 RB 3097 arch/powerpc/xmon/ppc-opc.c {"psq_lx", XW (4, 6,0), XW_MASK, PPCPS, 0, {FRT,RA,RB,PSWM,PSQM}}, RB 3099 arch/powerpc/xmon/ppc-opc.c {"psq_stx", XW (4, 7,0), XW_MASK, PPCPS, 0, {FRS,RA,RB,PSWM,PSQM}}, RB 3101 arch/powerpc/xmon/ppc-opc.c {"mulhhwu", XRC(4, 8,0), X_MASK, MULHW, 0, {RT, RA, RB}}, RB 3102 arch/powerpc/xmon/ppc-opc.c {"mulhhwu.", XRC(4, 8,1), X_MASK, MULHW, 0, {RT, RA, RB}}, RB 3108 arch/powerpc/xmon/ppc-opc.c {"machhwu", XO (4, 12,0,0), XO_MASK, MULHW, 0, {RT, RA, RB}}, RB 3110 arch/powerpc/xmon/ppc-opc.c {"machhwu.", XO (4, 12,0,1), XO_MASK, MULHW, 0, {RT, RA, RB}}, RB 3142 arch/powerpc/xmon/ppc-opc.c {"maddhd", VXA(4, 48), VXA_MASK, POWER9, 0, {RT, RA, RB, RC}}, RB 3144 arch/powerpc/xmon/ppc-opc.c {"maddhdu", VXA(4, 49), VXA_MASK, POWER9, 0, {RT, RA, RB, RC}}, RB 3147 arch/powerpc/xmon/ppc-opc.c {"maddld", VXA(4, 51), VXA_MASK, POWER9, 0, {RT, RA, RB, RC}}, RB 3172 arch/powerpc/xmon/ppc-opc.c {"psq_lux", XW (4, 38,0), XW_MASK, PPCPS, 0, {FRT,RA,RB,PSWM,PSQM}}, RB 3174 arch/powerpc/xmon/ppc-opc.c {"psq_stux", XW (4, 39,0), XW_MASK, PPCPS, 0, {FRS,RA,RB,PSWM,PSQM}}, RB 3177 arch/powerpc/xmon/ppc-opc.c {"mulhhw", XRC(4, 40,0), X_MASK, MULHW, 0, {RT, RA, RB}}, RB 3179 arch/powerpc/xmon/ppc-opc.c {"mulhhw.", XRC(4, 40,1), X_MASK, MULHW, 0, {RT, RA, RB}}, RB 3180 arch/powerpc/xmon/ppc-opc.c {"machhw", XO (4, 44,0,0), XO_MASK, MULHW, 0, {RT, RA, RB}}, RB 3181 arch/powerpc/xmon/ppc-opc.c {"machhw.", XO (4, 44,0,1), XO_MASK, MULHW, 0, {RT, RA, RB}}, RB 3182 arch/powerpc/xmon/ppc-opc.c {"nmachhw", XO (4, 46,0,0), XO_MASK, MULHW, 0, {RT, RA, RB}}, RB 3183 arch/powerpc/xmon/ppc-opc.c {"nmachhw.", XO (4, 46,0,1), XO_MASK, MULHW, 0, {RT, RA, RB}}, RB 3197 arch/powerpc/xmon/ppc-opc.c {"machhwsu", XO (4, 76,0,0), XO_MASK, MULHW, 0, {RT, RA, RB}}, RB 3198 arch/powerpc/xmon/ppc-opc.c {"machhwsu.", XO (4, 76,0,1), XO_MASK, MULHW, 0, {RT, RA, RB}}, RB 3207 arch/powerpc/xmon/ppc-opc.c {"machhws", XO (4, 108,0,0), XO_MASK, MULHW, 0, {RT, RA, RB}}, RB 3208 arch/powerpc/xmon/ppc-opc.c {"machhws.", XO (4, 108,0,1), XO_MASK, MULHW, 0, {RT, RA, RB}}, RB 3209 arch/powerpc/xmon/ppc-opc.c {"nmachhws", XO (4, 110,0,0), XO_MASK, MULHW, 0, {RT, RA, RB}}, RB 3210 arch/powerpc/xmon/ppc-opc.c {"nmachhws.", XO (4, 110,0,1), XO_MASK, MULHW, 0, {RT, RA, RB}}, RB 3220 arch/powerpc/xmon/ppc-opc.c {"mulchwu", XRC(4, 136,0), X_MASK, MULHW, 0, {RT, RA, RB}}, RB 3222 arch/powerpc/xmon/ppc-opc.c {"mulchwu.", XRC(4, 136,1), X_MASK, MULHW, 0, {RT, RA, RB}}, RB 3223 arch/powerpc/xmon/ppc-opc.c {"macchwu", XO (4, 140,0,0), XO_MASK, MULHW, 0, {RT, RA, RB}}, RB 3224 arch/powerpc/xmon/ppc-opc.c {"macchwu.", XO (4, 140,0,1), XO_MASK, MULHW, 0, {RT, RA, RB}}, RB 3233 arch/powerpc/xmon/ppc-opc.c {"mulchw", XRC(4, 168,0), X_MASK, MULHW, 0, {RT, RA, RB}}, RB 3234 arch/powerpc/xmon/ppc-opc.c {"mulchw.", XRC(4, 168,1), X_MASK, MULHW, 0, {RT, RA, RB}}, RB 3235 arch/powerpc/xmon/ppc-opc.c {"macchw", XO (4, 172,0,0), XO_MASK, MULHW, 0, {RT, RA, RB}}, RB 3236 arch/powerpc/xmon/ppc-opc.c {"macchw.", XO (4, 172,0,1), XO_MASK, MULHW, 0, {RT, RA, RB}}, RB 3237 arch/powerpc/xmon/ppc-opc.c {"nmacchw", XO (4, 174,0,0), XO_MASK, MULHW, 0, {RT, RA, RB}}, RB 3238 arch/powerpc/xmon/ppc-opc.c {"nmacchw.", XO (4, 174,0,1), XO_MASK, MULHW, 0, {RT, RA, RB}}, RB 3248 arch/powerpc/xmon/ppc-opc.c {"macchwsu", XO (4, 204,0,0), XO_MASK, MULHW, 0, {RT, RA, RB}}, RB 3249 arch/powerpc/xmon/ppc-opc.c {"macchwsu.", XO (4, 204,0,1), XO_MASK, MULHW, 0, {RT, RA, RB}}, RB 3256 arch/powerpc/xmon/ppc-opc.c {"macchws", XO (4, 236,0,0), XO_MASK, MULHW, 0, {RT, RA, RB}}, RB 3257 arch/powerpc/xmon/ppc-opc.c {"macchws.", XO (4, 236,0,1), XO_MASK, MULHW, 0, {RT, RA, RB}}, RB 3258 arch/powerpc/xmon/ppc-opc.c {"nmacchws", XO (4, 238,0,0), XO_MASK, MULHW, 0, {RT, RA, RB}}, RB 3259 arch/powerpc/xmon/ppc-opc.c {"nmacchws.", XO (4, 238,0,1), XO_MASK, MULHW, 0, {RT, RA, RB}}, RB 3260 arch/powerpc/xmon/ppc-opc.c {"evaddw", VX (4, 512), VX_MASK, PPCSPE, 0, {RS, RA, RB}}, RB 3263 arch/powerpc/xmon/ppc-opc.c {"evaddiw", VX (4, 514), VX_MASK, PPCSPE, 0, {RS, RB, UIMM}}, RB 3265 arch/powerpc/xmon/ppc-opc.c {"evsubfw", VX (4, 516), VX_MASK, PPCSPE, 0, {RS, RA, RB}}, RB 3266 arch/powerpc/xmon/ppc-opc.c {"evsubw", VX (4, 516), VX_MASK, PPCSPE, 0, {RS, RB, RA}}, RB 3268 arch/powerpc/xmon/ppc-opc.c {"evsubifw", VX (4, 518), VX_MASK, PPCSPE, 0, {RS, UIMM, RB}}, RB 3269 arch/powerpc/xmon/ppc-opc.c {"evsubiw", VX (4, 518), VX_MASK, PPCSPE, 0, {RS, RB, UIMM}}, RB 3283 arch/powerpc/xmon/ppc-opc.c {"brinc", VX (4, 527), VX_MASK, PPCSPE, 0, {RS, RA, RB}}, RB 3286 arch/powerpc/xmon/ppc-opc.c {"evand", VX (4, 529), VX_MASK, PPCSPE, 0, {RS, RA, RB}}, RB 3287 arch/powerpc/xmon/ppc-opc.c {"evandc", VX (4, 530), VX_MASK, PPCSPE, 0, {RS, RA, RB}}, RB 3288 arch/powerpc/xmon/ppc-opc.c {"evxor", VX (4, 534), VX_MASK, PPCSPE, 0, {RS, RA, RB}}, RB 3290 arch/powerpc/xmon/ppc-opc.c {"evor", VX (4, 535), VX_MASK, PPCSPE, 0, {RS, RA, RB}}, RB 3291 arch/powerpc/xmon/ppc-opc.c {"evnor", VX (4, 536), VX_MASK, PPCSPE, 0, {RS, RA, RB}}, RB 3294 arch/powerpc/xmon/ppc-opc.c {"eveqv", VX (4, 537), VX_MASK, PPCSPE, 0, {RS, RA, RB}}, RB 3295 arch/powerpc/xmon/ppc-opc.c {"evorc", VX (4, 539), VX_MASK, PPCSPE, 0, {RS, RA, RB}}, RB 3296 arch/powerpc/xmon/ppc-opc.c {"evnand", VX (4, 542), VX_MASK, PPCSPE, 0, {RS, RA, RB}}, RB 3297 arch/powerpc/xmon/ppc-opc.c {"evsrwu", VX (4, 544), VX_MASK, PPCSPE, 0, {RS, RA, RB}}, RB 3298 arch/powerpc/xmon/ppc-opc.c {"evsrws", VX (4, 545), VX_MASK, PPCSPE, 0, {RS, RA, RB}}, RB 3301 arch/powerpc/xmon/ppc-opc.c {"evslw", VX (4, 548), VX_MASK, PPCSPE, 0, {RS, RA, RB}}, RB 3303 arch/powerpc/xmon/ppc-opc.c {"evrlw", VX (4, 552), VX_MASK, PPCSPE, 0, {RS, RA, RB}}, RB 3307 arch/powerpc/xmon/ppc-opc.c {"evmergehi", VX (4, 556), VX_MASK, PPCSPE, 0, {RS, RA, RB}}, RB 3308 arch/powerpc/xmon/ppc-opc.c {"evmergelo", VX (4, 557), VX_MASK, PPCSPE, 0, {RS, RA, RB}}, RB 3309 arch/powerpc/xmon/ppc-opc.c {"evmergehilo", VX (4, 558), VX_MASK, PPCSPE, 0, {RS, RA, RB}}, RB 3310 arch/powerpc/xmon/ppc-opc.c {"evmergelohi", VX (4, 559), VX_MASK, PPCSPE, 0, {RS, RA, RB}}, RB 3311 arch/powerpc/xmon/ppc-opc.c {"evcmpgtu", VX (4, 560), VX_MASK, PPCSPE, 0, {CRFD, RA, RB}}, RB 3312 arch/powerpc/xmon/ppc-opc.c {"evcmpgts", VX (4, 561), VX_MASK, PPCSPE, 0, {CRFD, RA, RB}}, RB 3313 arch/powerpc/xmon/ppc-opc.c {"evcmpltu", VX (4, 562), VX_MASK, PPCSPE, 0, {CRFD, RA, RB}}, RB 3314 arch/powerpc/xmon/ppc-opc.c {"evcmplts", VX (4, 563), VX_MASK, PPCSPE, 0, {CRFD, RA, RB}}, RB 3315 arch/powerpc/xmon/ppc-opc.c {"evcmpeq", VX (4, 564), VX_MASK, PPCSPE, 0, {CRFD, RA, RB}}, RB 3328 arch/powerpc/xmon/ppc-opc.c {"evsel", EVSEL(4,79), EVSEL_MASK, PPCSPE, 0, {RS, RA, RB, CRFS}}, RB 3330 arch/powerpc/xmon/ppc-opc.c {"evfsadd", VX (4, 640), VX_MASK, PPCSPE, 0, {RS, RA, RB}}, RB 3332 arch/powerpc/xmon/ppc-opc.c {"evfssub", VX (4, 641), VX_MASK, PPCSPE, 0, {RS, RA, RB}}, RB 3340 arch/powerpc/xmon/ppc-opc.c {"evfsmul", VX (4, 648), VX_MASK, PPCSPE, 0, {RS, RA, RB}}, RB 3341 arch/powerpc/xmon/ppc-opc.c {"evfsdiv", VX (4, 649), VX_MASK, PPCSPE, 0, {RS, RA, RB}}, RB 3343 arch/powerpc/xmon/ppc-opc.c {"evfscmpgt", VX (4, 652), VX_MASK, PPCSPE, 0, {CRFD, RA, RB}}, RB 3346 arch/powerpc/xmon/ppc-opc.c {"evfscmplt", VX (4, 653), VX_MASK, PPCSPE, 0, {CRFD, RA, RB}}, RB 3347 arch/powerpc/xmon/ppc-opc.c {"evfscmpeq", VX (4, 654), VX_MASK, PPCSPE, 0, {CRFD, RA, RB}}, RB 3349 arch/powerpc/xmon/ppc-opc.c {"evfscfui", VX (4, 656), VX_MASK, PPCSPE, 0, {RS, RB}}, RB 3350 arch/powerpc/xmon/ppc-opc.c {"evfscfsi", VX (4, 657), VX_MASK, PPCSPE, 0, {RS, RB}}, RB 3351 arch/powerpc/xmon/ppc-opc.c {"evfscfuf", VX (4, 658), VX_MASK, PPCSPE, 0, {RS, RB}}, RB 3352 arch/powerpc/xmon/ppc-opc.c {"evfscfsf", VX (4, 659), VX_MASK, PPCSPE, 0, {RS, RB}}, RB 3353 arch/powerpc/xmon/ppc-opc.c {"evfsctui", VX (4, 660), VX_MASK, PPCSPE, 0, {RS, RB}}, RB 3354 arch/powerpc/xmon/ppc-opc.c {"evfsctsi", VX (4, 661), VX_MASK, PPCSPE, 0, {RS, RB}}, RB 3355 arch/powerpc/xmon/ppc-opc.c {"evfsctuf", VX (4, 662), VX_MASK, PPCSPE, 0, {RS, RB}}, RB 3356 arch/powerpc/xmon/ppc-opc.c {"evfsctsf", VX (4, 663), VX_MASK, PPCSPE, 0, {RS, RB}}, RB 3357 arch/powerpc/xmon/ppc-opc.c {"evfsctuiz", VX (4, 664), VX_MASK, PPCSPE, 0, {RS, RB}}, RB 3359 arch/powerpc/xmon/ppc-opc.c {"evfsctsiz", VX (4, 666), VX_MASK, PPCSPE, 0, {RS, RB}}, RB 3360 arch/powerpc/xmon/ppc-opc.c {"evfststgt", VX (4, 668), VX_MASK, PPCSPE, 0, {CRFD, RA, RB}}, RB 3361 arch/powerpc/xmon/ppc-opc.c {"evfststlt", VX (4, 669), VX_MASK, PPCSPE, 0, {CRFD, RA, RB}}, RB 3362 arch/powerpc/xmon/ppc-opc.c {"evfststeq", VX (4, 670), VX_MASK, PPCSPE, 0, {CRFD, RA, RB}}, RB 3364 arch/powerpc/xmon/ppc-opc.c {"efsadd", VX (4, 704), VX_MASK, PPCEFS, 0, {RS, RA, RB}}, RB 3365 arch/powerpc/xmon/ppc-opc.c {"efssub", VX (4, 705), VX_MASK, PPCEFS, 0, {RS, RA, RB}}, RB 3373 arch/powerpc/xmon/ppc-opc.c {"efsmul", VX (4, 712), VX_MASK, PPCEFS, 0, {RS, RA, RB}}, RB 3374 arch/powerpc/xmon/ppc-opc.c {"efsdiv", VX (4, 713), VX_MASK, PPCEFS, 0, {RS, RA, RB}}, RB 3376 arch/powerpc/xmon/ppc-opc.c {"efscmpgt", VX (4, 716), VX_MASK, PPCEFS, 0, {CRFD, RA, RB}}, RB 3378 arch/powerpc/xmon/ppc-opc.c {"efscmplt", VX (4, 717), VX_MASK, PPCEFS, 0, {CRFD, RA, RB}}, RB 3379 arch/powerpc/xmon/ppc-opc.c {"efscmpeq", VX (4, 718), VX_MASK, PPCEFS, 0, {CRFD, RA, RB}}, RB 3381 arch/powerpc/xmon/ppc-opc.c {"efscfd", VX (4, 719), VX_MASK, PPCEFS, 0, {RS, RB}}, RB 3382 arch/powerpc/xmon/ppc-opc.c {"efscfui", VX (4, 720), VX_MASK, PPCEFS, 0, {RS, RB}}, RB 3383 arch/powerpc/xmon/ppc-opc.c {"efscfsi", VX (4, 721), VX_MASK, PPCEFS, 0, {RS, RB}}, RB 3384 arch/powerpc/xmon/ppc-opc.c {"efscfuf", VX (4, 722), VX_MASK, PPCEFS, 0, {RS, RB}}, RB 3385 arch/powerpc/xmon/ppc-opc.c {"efscfsf", VX (4, 723), VX_MASK, PPCEFS, 0, {RS, RB}}, RB 3386 arch/powerpc/xmon/ppc-opc.c {"efsctui", VX (4, 724), VX_MASK, PPCEFS, 0, {RS, RB}}, RB 3387 arch/powerpc/xmon/ppc-opc.c {"efsctsi", VX (4, 725), VX_MASK, PPCEFS, 0, {RS, RB}}, RB 3388 arch/powerpc/xmon/ppc-opc.c {"efsctuf", VX (4, 726), VX_MASK, PPCEFS, 0, {RS, RB}}, RB 3389 arch/powerpc/xmon/ppc-opc.c {"efsctsf", VX (4, 727), VX_MASK, PPCEFS, 0, {RS, RB}}, RB 3390 arch/powerpc/xmon/ppc-opc.c {"efsctuiz", VX (4, 728), VX_MASK, PPCEFS, 0, {RS, RB}}, RB 3392 arch/powerpc/xmon/ppc-opc.c {"efsctsiz", VX (4, 730), VX_MASK, PPCEFS, 0, {RS, RB}}, RB 3393 arch/powerpc/xmon/ppc-opc.c {"efststgt", VX (4, 732), VX_MASK, PPCEFS, 0, {CRFD, RA, RB}}, RB 3394 arch/powerpc/xmon/ppc-opc.c {"efststlt", VX (4, 733), VX_MASK, PPCEFS, 0, {CRFD, RA, RB}}, RB 3395 arch/powerpc/xmon/ppc-opc.c {"efststeq", VX (4, 734), VX_MASK, PPCEFS, 0, {CRFD, RA, RB}}, RB 3396 arch/powerpc/xmon/ppc-opc.c {"efdadd", VX (4, 736), VX_MASK, PPCEFS, 0, {RS, RA, RB}}, RB 3397 arch/powerpc/xmon/ppc-opc.c {"efdsub", VX (4, 737), VX_MASK, PPCEFS, 0, {RS, RA, RB}}, RB 3398 arch/powerpc/xmon/ppc-opc.c {"efdcfuid", VX (4, 738), VX_MASK, PPCEFS, 0, {RS, RB}}, RB 3399 arch/powerpc/xmon/ppc-opc.c {"efdcfsid", VX (4, 739), VX_MASK, PPCEFS, 0, {RS, RB}}, RB 3403 arch/powerpc/xmon/ppc-opc.c {"efdmul", VX (4, 744), VX_MASK, PPCEFS, 0, {RS, RA, RB}}, RB 3404 arch/powerpc/xmon/ppc-opc.c {"efddiv", VX (4, 745), VX_MASK, PPCEFS, 0, {RS, RA, RB}}, RB 3405 arch/powerpc/xmon/ppc-opc.c {"efdctuidz", VX (4, 746), VX_MASK, PPCEFS, 0, {RS, RB}}, RB 3406 arch/powerpc/xmon/ppc-opc.c {"efdctsidz", VX (4, 747), VX_MASK, PPCEFS, 0, {RS, RB}}, RB 3407 arch/powerpc/xmon/ppc-opc.c {"efdcmpgt", VX (4, 748), VX_MASK, PPCEFS, 0, {CRFD, RA, RB}}, RB 3408 arch/powerpc/xmon/ppc-opc.c {"efdcmplt", VX (4, 749), VX_MASK, PPCEFS, 0, {CRFD, RA, RB}}, RB 3409 arch/powerpc/xmon/ppc-opc.c {"efdcmpeq", VX (4, 750), VX_MASK, PPCEFS, 0, {CRFD, RA, RB}}, RB 3410 arch/powerpc/xmon/ppc-opc.c {"efdcfs", VX (4, 751), VX_MASK, PPCEFS, 0, {RS, RB}}, RB 3411 arch/powerpc/xmon/ppc-opc.c {"efdcfui", VX (4, 752), VX_MASK, PPCEFS, 0, {RS, RB}}, RB 3412 arch/powerpc/xmon/ppc-opc.c {"efdcfsi", VX (4, 753), VX_MASK, PPCEFS, 0, {RS, RB}}, RB 3413 arch/powerpc/xmon/ppc-opc.c {"efdcfuf", VX (4, 754), VX_MASK, PPCEFS, 0, {RS, RB}}, RB 3414 arch/powerpc/xmon/ppc-opc.c {"efdcfsf", VX (4, 755), VX_MASK, PPCEFS, 0, {RS, RB}}, RB 3415 arch/powerpc/xmon/ppc-opc.c {"efdctui", VX (4, 756), VX_MASK, PPCEFS, 0, {RS, RB}}, RB 3416 arch/powerpc/xmon/ppc-opc.c {"efdctsi", VX (4, 757), VX_MASK, PPCEFS, 0, {RS, RB}}, RB 3417 arch/powerpc/xmon/ppc-opc.c {"efdctuf", VX (4, 758), VX_MASK, PPCEFS, 0, {RS, RB}}, RB 3418 arch/powerpc/xmon/ppc-opc.c {"efdctsf", VX (4, 759), VX_MASK, PPCEFS, 0, {RS, RB}}, RB 3419 arch/powerpc/xmon/ppc-opc.c {"efdctuiz", VX (4, 760), VX_MASK, PPCEFS, 0, {RS, RB}}, RB 3421 arch/powerpc/xmon/ppc-opc.c {"efdctsiz", VX (4, 762), VX_MASK, PPCEFS, 0, {RS, RB}}, RB 3422 arch/powerpc/xmon/ppc-opc.c {"efdtstgt", VX (4, 764), VX_MASK, PPCEFS, 0, {CRFD, RA, RB}}, RB 3423 arch/powerpc/xmon/ppc-opc.c {"efdtstlt", VX (4, 765), VX_MASK, PPCEFS, 0, {CRFD, RA, RB}}, RB 3424 arch/powerpc/xmon/ppc-opc.c {"efdtsteq", VX (4, 766), VX_MASK, PPCEFS, 0, {CRFD, RA, RB}}, RB 3425 arch/powerpc/xmon/ppc-opc.c {"evlddx", VX (4, 768), VX_MASK, PPCSPE, 0, {RS, RA, RB}}, RB 3428 arch/powerpc/xmon/ppc-opc.c {"evldwx", VX (4, 770), VX_MASK, PPCSPE, 0, {RS, RA, RB}}, RB 3431 arch/powerpc/xmon/ppc-opc.c {"evldhx", VX (4, 772), VX_MASK, PPCSPE, 0, {RS, RA, RB}}, RB 3435 arch/powerpc/xmon/ppc-opc.c {"evlhhesplatx",VX (4, 776), VX_MASK, PPCSPE, 0, {RS, RA, RB}}, RB 3440 arch/powerpc/xmon/ppc-opc.c {"evlhhousplatx",VX(4, 780), VX_MASK, PPCSPE, 0, {RS, RA, RB}}, RB 3444 arch/powerpc/xmon/ppc-opc.c {"evlhhossplatx",VX(4, 782), VX_MASK, PPCSPE, 0, {RS, RA, RB}}, RB 3447 arch/powerpc/xmon/ppc-opc.c {"mullhwu", XRC(4, 392,0), X_MASK, MULHW, 0, {RT, RA, RB}}, RB 3448 arch/powerpc/xmon/ppc-opc.c {"evlwhex", VX (4, 784), VX_MASK, PPCSPE, 0, {RS, RA, RB}}, RB 3449 arch/powerpc/xmon/ppc-opc.c {"mullhwu.", XRC(4, 392,1), X_MASK, MULHW, 0, {RT, RA, RB}}, RB 3451 arch/powerpc/xmon/ppc-opc.c {"evlwhoux", VX (4, 788), VX_MASK, PPCSPE, 0, {RS, RA, RB}}, RB 3453 arch/powerpc/xmon/ppc-opc.c {"evlwhosx", VX (4, 790), VX_MASK, PPCSPE, 0, {RS, RA, RB}}, RB 3455 arch/powerpc/xmon/ppc-opc.c {"maclhwu", XO (4, 396,0,0),XO_MASK, MULHW, 0, {RT, RA, RB}}, RB 3456 arch/powerpc/xmon/ppc-opc.c {"evlwwsplatx", VX (4, 792), VX_MASK, PPCSPE, 0, {RS, RA, RB}}, RB 3457 arch/powerpc/xmon/ppc-opc.c {"maclhwu.", XO (4, 396,0,1),XO_MASK, MULHW, 0, {RT, RA, RB}}, RB 3459 arch/powerpc/xmon/ppc-opc.c {"evlwhsplatx", VX (4, 796), VX_MASK, PPCSPE, 0, {RS, RA, RB}}, RB 3461 arch/powerpc/xmon/ppc-opc.c {"evstddx", VX (4, 800), VX_MASK, PPCSPE, 0, {RS, RA, RB}}, RB 3463 arch/powerpc/xmon/ppc-opc.c {"evstdwx", VX (4, 802), VX_MASK, PPCSPE, 0, {RS, RA, RB}}, RB 3465 arch/powerpc/xmon/ppc-opc.c {"evstdhx", VX (4, 804), VX_MASK, PPCSPE, 0, {RS, RA, RB}}, RB 3467 arch/powerpc/xmon/ppc-opc.c {"evstwhex", VX (4, 816), VX_MASK, PPCSPE, 0, {RS, RA, RB}}, RB 3469 arch/powerpc/xmon/ppc-opc.c {"evstwhox", VX (4, 820), VX_MASK, PPCSPE, 0, {RS, RA, RB}}, RB 3471 arch/powerpc/xmon/ppc-opc.c {"evstwwex", VX (4, 824), VX_MASK, PPCSPE, 0, {RS, RA, RB}}, RB 3473 arch/powerpc/xmon/ppc-opc.c {"evstwwox", VX (4, 828), VX_MASK, PPCSPE, 0, {RS, RA, RB}}, RB 3486 arch/powerpc/xmon/ppc-opc.c {"mullhw", XRC(4, 424,0), X_MASK, MULHW, 0, {RT, RA, RB}}, RB 3487 arch/powerpc/xmon/ppc-opc.c {"mullhw.", XRC(4, 424,1), X_MASK, MULHW, 0, {RT, RA, RB}}, RB 3488 arch/powerpc/xmon/ppc-opc.c {"maclhw", XO (4, 428,0,0),XO_MASK, MULHW, 0, {RT, RA, RB}}, RB 3489 arch/powerpc/xmon/ppc-opc.c {"maclhw.", XO (4, 428,0,1),XO_MASK, MULHW, 0, {RT, RA, RB}}, RB 3490 arch/powerpc/xmon/ppc-opc.c {"nmaclhw", XO (4, 430,0,0),XO_MASK, MULHW, 0, {RT, RA, RB}}, RB 3491 arch/powerpc/xmon/ppc-opc.c {"nmaclhw.", XO (4, 430,0,1),XO_MASK, MULHW, 0, {RT, RA, RB}}, RB 3501 arch/powerpc/xmon/ppc-opc.c {"maclhwsu", XO (4, 460,0,0), XO_MASK, MULHW, 0, {RT, RA, RB}}, RB 3502 arch/powerpc/xmon/ppc-opc.c {"maclhwsu.", XO (4, 460,0,1), XO_MASK, MULHW, 0, {RT, RA, RB}}, RB 3511 arch/powerpc/xmon/ppc-opc.c {"maclhws", XO (4, 492,0,0), XO_MASK, MULHW, 0, {RT, RA, RB}}, RB 3512 arch/powerpc/xmon/ppc-opc.c {"maclhws.", XO (4, 492,0,1), XO_MASK, MULHW, 0, {RT, RA, RB}}, RB 3513 arch/powerpc/xmon/ppc-opc.c {"nmaclhws", XO (4, 494,0,0), XO_MASK, MULHW, 0, {RT, RA, RB}}, RB 3514 arch/powerpc/xmon/ppc-opc.c {"nmaclhws.", XO (4, 494,0,1), XO_MASK, MULHW, 0, {RT, RA, RB}}, RB 3519 arch/powerpc/xmon/ppc-opc.c {"evmhessf", VX (4,1027), VX_MASK, PPCSPE, 0, {RS, RA, RB}}, RB 3525 arch/powerpc/xmon/ppc-opc.c {"evmhossf", VX (4,1031), VX_MASK, PPCSPE, 0, {RS, RA, RB}}, RB 3527 arch/powerpc/xmon/ppc-opc.c {"evmheumi", VX (4,1032), VX_MASK, PPCSPE, 0, {RS, RA, RB}}, RB 3528 arch/powerpc/xmon/ppc-opc.c {"evmhesmi", VX (4,1033), VX_MASK, PPCSPE, 0, {RS, RA, RB}}, RB 3530 arch/powerpc/xmon/ppc-opc.c {"evmhesmf", VX (4,1035), VX_MASK, PPCSPE, 0, {RS, RA, RB}}, RB 3531 arch/powerpc/xmon/ppc-opc.c {"evmhoumi", VX (4,1036), VX_MASK, PPCSPE, 0, {RS, RA, RB}}, RB 3533 arch/powerpc/xmon/ppc-opc.c {"evmhosmi", VX (4,1037), VX_MASK, PPCSPE, 0, {RS, RA, RB}}, RB 3534 arch/powerpc/xmon/ppc-opc.c {"evmhosmf", VX (4,1039), VX_MASK, PPCSPE, 0, {RS, RA, RB}}, RB 3535 arch/powerpc/xmon/ppc-opc.c {"machhwuo", XO (4, 12,1,0), XO_MASK, MULHW, 0, {RT, RA, RB}}, RB 3536 arch/powerpc/xmon/ppc-opc.c {"machhwuo.", XO (4, 12,1,1), XO_MASK, MULHW, 0, {RT, RA, RB}}, RB 3539 arch/powerpc/xmon/ppc-opc.c {"evmhessfa", VX (4,1059), VX_MASK, PPCSPE, 0, {RS, RA, RB}}, RB 3540 arch/powerpc/xmon/ppc-opc.c {"evmhossfa", VX (4,1063), VX_MASK, PPCSPE, 0, {RS, RA, RB}}, RB 3541 arch/powerpc/xmon/ppc-opc.c {"evmheumia", VX (4,1064), VX_MASK, PPCSPE, 0, {RS, RA, RB}}, RB 3542 arch/powerpc/xmon/ppc-opc.c {"evmhesmia", VX (4,1065), VX_MASK, PPCSPE, 0, {RS, RA, RB}}, RB 3543 arch/powerpc/xmon/ppc-opc.c {"evmhesmfa", VX (4,1067), VX_MASK, PPCSPE, 0, {RS, RA, RB}}, RB 3544 arch/powerpc/xmon/ppc-opc.c {"evmhoumia", VX (4,1068), VX_MASK, PPCSPE, 0, {RS, RA, RB}}, RB 3545 arch/powerpc/xmon/ppc-opc.c {"evmhosmia", VX (4,1069), VX_MASK, PPCSPE, 0, {RS, RA, RB}}, RB 3546 arch/powerpc/xmon/ppc-opc.c {"evmhosmfa", VX (4,1071), VX_MASK, PPCSPE, 0, {RS, RA, RB}}, RB 3556 arch/powerpc/xmon/ppc-opc.c {"evmwhssf", VX (4,1095), VX_MASK, PPCSPE, 0, {RS, RA, RB}}, RB 3558 arch/powerpc/xmon/ppc-opc.c {"evmwlumi", VX (4,1096), VX_MASK, PPCSPE, 0, {RS, RA, RB}}, RB 3560 arch/powerpc/xmon/ppc-opc.c {"evmwhumi", VX (4,1100), VX_MASK, PPCSPE, 0, {RS, RA, RB}}, RB 3562 arch/powerpc/xmon/ppc-opc.c {"evmwhsmi", VX (4,1101), VX_MASK, PPCSPE, 0, {RS, RA, RB}}, RB 3564 arch/powerpc/xmon/ppc-opc.c {"evmwhsmf", VX (4,1103), VX_MASK, PPCSPE, 0, {RS, RA, RB}}, RB 3565 arch/powerpc/xmon/ppc-opc.c {"evmwssf", VX (4,1107), VX_MASK, PPCSPE, 0, {RS, RA, RB}}, RB 3566 arch/powerpc/xmon/ppc-opc.c {"machhwo", XO (4, 44,1,0), XO_MASK, MULHW, 0, {RT, RA, RB}}, RB 3567 arch/powerpc/xmon/ppc-opc.c {"evmwumi", VX (4,1112), VX_MASK, PPCSPE, 0, {RS, RA, RB}}, RB 3568 arch/powerpc/xmon/ppc-opc.c {"machhwo.", XO (4, 44,1,1), XO_MASK, MULHW, 0, {RT, RA, RB}}, RB 3569 arch/powerpc/xmon/ppc-opc.c {"evmwsmi", VX (4,1113), VX_MASK, PPCSPE, 0, {RS, RA, RB}}, RB 3570 arch/powerpc/xmon/ppc-opc.c {"evmwsmf", VX (4,1115), VX_MASK, PPCSPE, 0, {RS, RA, RB}}, RB 3571 arch/powerpc/xmon/ppc-opc.c {"nmachhwo", XO (4, 46,1,0), XO_MASK, MULHW, 0, {RT, RA, RB}}, RB 3572 arch/powerpc/xmon/ppc-opc.c {"nmachhwo.", XO (4, 46,1,1), XO_MASK, MULHW, 0, {RT, RA, RB}}, RB 3575 arch/powerpc/xmon/ppc-opc.c {"evmwhssfa", VX (4,1127), VX_MASK, PPCSPE, 0, {RS, RA, RB}}, RB 3576 arch/powerpc/xmon/ppc-opc.c {"evmwlumia", VX (4,1128), VX_MASK, PPCSPE, 0, {RS, RA, RB}}, RB 3577 arch/powerpc/xmon/ppc-opc.c {"evmwhumia", VX (4,1132), VX_MASK, PPCSPE, 0, {RS, RA, RB}}, RB 3578 arch/powerpc/xmon/ppc-opc.c {"evmwhsmia", VX (4,1133), VX_MASK, PPCSPE, 0, {RS, RA, RB}}, RB 3579 arch/powerpc/xmon/ppc-opc.c {"evmwhsmfa", VX (4,1135), VX_MASK, PPCSPE, 0, {RS, RA, RB}}, RB 3580 arch/powerpc/xmon/ppc-opc.c {"evmwssfa", VX (4,1139), VX_MASK, PPCSPE, 0, {RS, RA, RB}}, RB 3581 arch/powerpc/xmon/ppc-opc.c {"evmwumia", VX (4,1144), VX_MASK, PPCSPE, 0, {RS, RA, RB}}, RB 3582 arch/powerpc/xmon/ppc-opc.c {"evmwsmia", VX (4,1145), VX_MASK, PPCSPE, 0, {RS, RA, RB}}, RB 3583 arch/powerpc/xmon/ppc-opc.c {"evmwsmfa", VX (4,1147), VX_MASK, PPCSPE, 0, {RS, RA, RB}}, RB 3595 arch/powerpc/xmon/ppc-opc.c {"machhwsuo", XO (4, 76,1,0), XO_MASK, MULHW, 0, {RT, RA, RB}}, RB 3596 arch/powerpc/xmon/ppc-opc.c {"machhwsuo.", XO (4, 76,1,1), XO_MASK, MULHW, 0, {RT, RA, RB}}, RB 3607 arch/powerpc/xmon/ppc-opc.c {"evdivws", VX (4,1222), VX_MASK, PPCSPE, 0, {RS, RA, RB}}, RB 3612 arch/powerpc/xmon/ppc-opc.c {"evdivwu", VX (4,1223), VX_MASK, PPCSPE, 0, {RS, RA, RB}}, RB 3619 arch/powerpc/xmon/ppc-opc.c {"machhwso", XO (4, 108,1,0), XO_MASK, MULHW, 0, {RT, RA, RB}}, RB 3620 arch/powerpc/xmon/ppc-opc.c {"machhwso.", XO (4, 108,1,1), XO_MASK, MULHW, 0, {RT, RA, RB}}, RB 3621 arch/powerpc/xmon/ppc-opc.c {"nmachhwso", XO (4, 110,1,0), XO_MASK, MULHW, 0, {RT, RA, RB}}, RB 3622 arch/powerpc/xmon/ppc-opc.c {"nmachhwso.", XO (4, 110,1,1), XO_MASK, MULHW, 0, {RT, RA, RB}}, RB 3626 arch/powerpc/xmon/ppc-opc.c {"evmheusiaaw", VX (4,1280), VX_MASK, PPCSPE, 0, {RS, RA, RB}}, RB 3628 arch/powerpc/xmon/ppc-opc.c {"evmhessiaaw", VX (4,1281), VX_MASK, PPCSPE, 0, {RS, RA, RB}}, RB 3630 arch/powerpc/xmon/ppc-opc.c {"evmhessfaaw", VX (4,1283), VX_MASK, PPCSPE, 0, {RS, RA, RB}}, RB 3631 arch/powerpc/xmon/ppc-opc.c {"evmhousiaaw", VX (4,1284), VX_MASK, PPCSPE, 0, {RS, RA, RB}}, RB 3634 arch/powerpc/xmon/ppc-opc.c {"evmhossiaaw", VX (4,1285), VX_MASK, PPCSPE, 0, {RS, RA, RB}}, RB 3638 arch/powerpc/xmon/ppc-opc.c {"evmhossfaaw", VX (4,1287), VX_MASK, PPCSPE, 0, {RS, RA, RB}}, RB 3639 arch/powerpc/xmon/ppc-opc.c {"evmheumiaaw", VX (4,1288), VX_MASK, PPCSPE, 0, {RS, RA, RB}}, RB 3642 arch/powerpc/xmon/ppc-opc.c {"evmhesmiaaw", VX (4,1289), VX_MASK, PPCSPE, 0, {RS, RA, RB}}, RB 3643 arch/powerpc/xmon/ppc-opc.c {"evmhesmfaaw", VX (4,1291), VX_MASK, PPCSPE, 0, {RS, RA, RB}}, RB 3645 arch/powerpc/xmon/ppc-opc.c {"evmhoumiaaw", VX (4,1292), VX_MASK, PPCSPE, 0, {RS, RA, RB}}, RB 3646 arch/powerpc/xmon/ppc-opc.c {"evmhosmiaaw", VX (4,1293), VX_MASK, PPCSPE, 0, {RS, RA, RB}}, RB 3647 arch/powerpc/xmon/ppc-opc.c {"evmhosmfaaw", VX (4,1295), VX_MASK, PPCSPE, 0, {RS, RA, RB}}, RB 3648 arch/powerpc/xmon/ppc-opc.c {"macchwuo", XO (4, 140,1,0), XO_MASK, MULHW, 0, {RT, RA, RB}}, RB 3649 arch/powerpc/xmon/ppc-opc.c {"macchwuo.", XO (4, 140,1,1), XO_MASK, MULHW, 0, {RT, RA, RB}}, RB 3650 arch/powerpc/xmon/ppc-opc.c {"evmhegumiaa", VX (4,1320), VX_MASK, PPCSPE, 0, {RS, RA, RB}}, RB 3651 arch/powerpc/xmon/ppc-opc.c {"evmhegsmiaa", VX (4,1321), VX_MASK, PPCSPE, 0, {RS, RA, RB}}, RB 3652 arch/powerpc/xmon/ppc-opc.c {"evmhegsmfaa", VX (4,1323), VX_MASK, PPCSPE, 0, {RS, RA, RB}}, RB 3653 arch/powerpc/xmon/ppc-opc.c {"evmhogumiaa", VX (4,1324), VX_MASK, PPCSPE, 0, {RS, RA, RB}}, RB 3654 arch/powerpc/xmon/ppc-opc.c {"evmhogsmiaa", VX (4,1325), VX_MASK, PPCSPE, 0, {RS, RA, RB}}, RB 3655 arch/powerpc/xmon/ppc-opc.c {"evmhogsmfaa", VX (4,1327), VX_MASK, PPCSPE, 0, {RS, RA, RB}}, RB 3657 arch/powerpc/xmon/ppc-opc.c {"evmwlusiaaw", VX (4,1344), VX_MASK, PPCSPE, 0, {RS, RA, RB}}, RB 3659 arch/powerpc/xmon/ppc-opc.c {"evmwlssiaaw", VX (4,1345), VX_MASK, PPCSPE, 0, {RS, RA, RB}}, RB 3666 arch/powerpc/xmon/ppc-opc.c {"evmwlumiaaw", VX (4,1352), VX_MASK, PPCSPE, 0, {RS, RA, RB}}, RB 3668 arch/powerpc/xmon/ppc-opc.c {"evmwlsmiaaw", VX (4,1353), VX_MASK, PPCSPE, 0, {RS, RA, RB}}, RB 3671 arch/powerpc/xmon/ppc-opc.c {"evmwssfaa", VX (4,1363), VX_MASK, PPCSPE, 0, {RS, RA, RB}}, RB 3672 arch/powerpc/xmon/ppc-opc.c {"macchwo", XO (4, 172,1,0), XO_MASK, MULHW, 0, {RT, RA, RB}}, RB 3673 arch/powerpc/xmon/ppc-opc.c {"evmwumiaa", VX (4,1368), VX_MASK, PPCSPE, 0, {RS, RA, RB}}, RB 3674 arch/powerpc/xmon/ppc-opc.c {"macchwo.", XO (4, 172,1,1), XO_MASK, MULHW, 0, {RT, RA, RB}}, RB 3675 arch/powerpc/xmon/ppc-opc.c {"evmwsmiaa", VX (4,1369), VX_MASK, PPCSPE, 0, {RS, RA, RB}}, RB 3676 arch/powerpc/xmon/ppc-opc.c {"evmwsmfaa", VX (4,1371), VX_MASK, PPCSPE, 0, {RS, RA, RB}}, RB 3677 arch/powerpc/xmon/ppc-opc.c {"nmacchwo", XO (4, 174,1,0), XO_MASK, MULHW, 0, {RT, RA, RB}}, RB 3678 arch/powerpc/xmon/ppc-opc.c {"nmacchwo.", XO (4, 174,1,1), XO_MASK, MULHW, 0, {RT, RA, RB}}, RB 3679 arch/powerpc/xmon/ppc-opc.c {"evmheusianw", VX (4,1408), VX_MASK, PPCSPE, 0, {RS, RA, RB}}, RB 3681 arch/powerpc/xmon/ppc-opc.c {"evmhessianw", VX (4,1409), VX_MASK, PPCSPE, 0, {RS, RA, RB}}, RB 3690 arch/powerpc/xmon/ppc-opc.c {"evmhessfanw", VX (4,1411), VX_MASK, PPCSPE, 0, {RS, RA, RB}}, RB 3692 arch/powerpc/xmon/ppc-opc.c {"evmhousianw", VX (4,1412), VX_MASK, PPCSPE, 0, {RS, RA, RB}}, RB 3693 arch/powerpc/xmon/ppc-opc.c {"evmhossianw", VX (4,1413), VX_MASK, PPCSPE, 0, {RS, RA, RB}}, RB 3697 arch/powerpc/xmon/ppc-opc.c {"evmhossfanw", VX (4,1415), VX_MASK, PPCSPE, 0, {RS, RA, RB}}, RB 3698 arch/powerpc/xmon/ppc-opc.c {"evmheumianw", VX (4,1416), VX_MASK, PPCSPE, 0, {RS, RA, RB}}, RB 3699 arch/powerpc/xmon/ppc-opc.c {"evmhesmianw", VX (4,1417), VX_MASK, PPCSPE, 0, {RS, RA, RB}}, RB 3700 arch/powerpc/xmon/ppc-opc.c {"evmhesmfanw", VX (4,1419), VX_MASK, PPCSPE, 0, {RS, RA, RB}}, RB 3701 arch/powerpc/xmon/ppc-opc.c {"evmhoumianw", VX (4,1420), VX_MASK, PPCSPE, 0, {RS, RA, RB}}, RB 3702 arch/powerpc/xmon/ppc-opc.c {"evmhosmianw", VX (4,1421), VX_MASK, PPCSPE, 0, {RS, RA, RB}}, RB 3703 arch/powerpc/xmon/ppc-opc.c {"evmhosmfanw", VX (4,1423), VX_MASK, PPCSPE, 0, {RS, RA, RB}}, RB 3704 arch/powerpc/xmon/ppc-opc.c {"macchwsuo", XO (4, 204,1,0), XO_MASK, MULHW, 0, {RT, RA, RB}}, RB 3705 arch/powerpc/xmon/ppc-opc.c {"macchwsuo.", XO (4, 204,1,1), XO_MASK, MULHW, 0, {RT, RA, RB}}, RB 3706 arch/powerpc/xmon/ppc-opc.c {"evmhegumian", VX (4,1448), VX_MASK, PPCSPE, 0, {RS, RA, RB}}, RB 3707 arch/powerpc/xmon/ppc-opc.c {"evmhegsmian", VX (4,1449), VX_MASK, PPCSPE, 0, {RS, RA, RB}}, RB 3708 arch/powerpc/xmon/ppc-opc.c {"evmhegsmfan", VX (4,1451), VX_MASK, PPCSPE, 0, {RS, RA, RB}}, RB 3709 arch/powerpc/xmon/ppc-opc.c {"evmhogumian", VX (4,1452), VX_MASK, PPCSPE, 0, {RS, RA, RB}}, RB 3710 arch/powerpc/xmon/ppc-opc.c {"evmhogsmian", VX (4,1453), VX_MASK, PPCSPE, 0, {RS, RA, RB}}, RB 3711 arch/powerpc/xmon/ppc-opc.c {"evmhogsmfan", VX (4,1455), VX_MASK, PPCSPE, 0, {RS, RA, RB}}, RB 3712 arch/powerpc/xmon/ppc-opc.c {"evmwlusianw", VX (4,1472), VX_MASK, PPCSPE, 0, {RS, RA, RB}}, RB 3714 arch/powerpc/xmon/ppc-opc.c {"evmwlssianw", VX (4,1473), VX_MASK, PPCSPE, 0, {RS, RA, RB}}, RB 3720 arch/powerpc/xmon/ppc-opc.c {"evmwlumianw", VX (4,1480), VX_MASK, PPCSPE, 0, {RS, RA, RB}}, RB 3721 arch/powerpc/xmon/ppc-opc.c {"evmwlsmianw", VX (4,1481), VX_MASK, PPCSPE, 0, {RS, RA, RB}}, RB 3724 arch/powerpc/xmon/ppc-opc.c {"evmwssfan", VX (4,1491), VX_MASK, PPCSPE, 0, {RS, RA, RB}}, RB 3725 arch/powerpc/xmon/ppc-opc.c {"macchwso", XO (4, 236,1,0), XO_MASK, MULHW, 0, {RT, RA, RB}}, RB 3726 arch/powerpc/xmon/ppc-opc.c {"evmwumian", VX (4,1496), VX_MASK, PPCSPE, 0, {RS, RA, RB}}, RB 3727 arch/powerpc/xmon/ppc-opc.c {"macchwso.", XO (4, 236,1,1), XO_MASK, MULHW, 0, {RT, RA, RB}}, RB 3728 arch/powerpc/xmon/ppc-opc.c {"evmwsmian", VX (4,1497), VX_MASK, PPCSPE, 0, {RS, RA, RB}}, RB 3729 arch/powerpc/xmon/ppc-opc.c {"evmwsmfan", VX (4,1499), VX_MASK, PPCSPE, 0, {RS, RA, RB}}, RB 3730 arch/powerpc/xmon/ppc-opc.c {"nmacchwso", XO (4, 238,1,0), XO_MASK, MULHW, 0, {RT, RA, RB}}, RB 3731 arch/powerpc/xmon/ppc-opc.c {"nmacchwso.", XO (4, 238,1,1), XO_MASK, MULHW, 0, {RT, RA, RB}}, RB 3788 arch/powerpc/xmon/ppc-opc.c {"maclhwuo", XO (4, 396,1,0), XO_MASK, MULHW, 0, {RT, RA, RB}}, RB 3789 arch/powerpc/xmon/ppc-opc.c {"maclhwuo.", XO (4, 396,1,1), XO_MASK, MULHW, 0, {RT, RA, RB}}, RB 3798 arch/powerpc/xmon/ppc-opc.c {"maclhwo", XO (4, 428,1,0), XO_MASK, MULHW, 0, {RT, RA, RB}}, RB 3799 arch/powerpc/xmon/ppc-opc.c {"maclhwo.", XO (4, 428,1,1), XO_MASK, MULHW, 0, {RT, RA, RB}}, RB 3800 arch/powerpc/xmon/ppc-opc.c {"nmaclhwo", XO (4, 430,1,0), XO_MASK, MULHW, 0, {RT, RA, RB}}, RB 3801 arch/powerpc/xmon/ppc-opc.c {"nmaclhwo.", XO (4, 430,1,1), XO_MASK, MULHW, 0, {RT, RA, RB}}, RB 3811 arch/powerpc/xmon/ppc-opc.c {"maclhwsuo", XO (4, 460,1,0), XO_MASK, MULHW, 0, {RT, RA, RB}}, RB 3812 arch/powerpc/xmon/ppc-opc.c {"maclhwsuo.", XO (4, 460,1,1), XO_MASK, MULHW, 0, {RT, RA, RB}}, RB 3819 arch/powerpc/xmon/ppc-opc.c {"maclhwso", XO (4, 492,1,0), XO_MASK, MULHW, 0, {RT, RA, RB}}, RB 3820 arch/powerpc/xmon/ppc-opc.c {"maclhwso.", XO (4, 492,1,1), XO_MASK, MULHW, 0, {RT, RA, RB}}, RB 3821 arch/powerpc/xmon/ppc-opc.c {"nmaclhwso", XO (4, 494,1,0), XO_MASK, MULHW, 0, {RT, RA, RB}}, RB 3822 arch/powerpc/xmon/ppc-opc.c {"nmaclhwso.", XO (4, 494,1,1), XO_MASK, MULHW, 0, {RT, RA, RB}}, RB 3823 arch/powerpc/xmon/ppc-opc.c {"dcbz_l", X (4,1014), XRT_MASK, PPCPS, 0, {RA, RB}}, RB 4602 arch/powerpc/xmon/ppc-opc.c {"rlmi", M(22,0), M_MASK, M601, PPCVLE, {RA, RS, RB, MBE, ME}}, RB 4603 arch/powerpc/xmon/ppc-opc.c {"rlmi.", M(22,1), M_MASK, M601, PPCVLE, {RA, RS, RB, MBE, ME}}, RB 4605 arch/powerpc/xmon/ppc-opc.c {"rotlw", MME(23,31,0), MMBME_MASK, PPCCOM, PPCVLE, {RA, RS, RB}}, RB 4606 arch/powerpc/xmon/ppc-opc.c {"rlwnm", M(23,0), M_MASK, PPCCOM, PPCVLE, {RA, RS, RB, MBE, ME}}, RB 4607 arch/powerpc/xmon/ppc-opc.c {"rlnm", M(23,0), M_MASK, PWRCOM, PPCVLE, {RA, RS, RB, MBE, ME}}, RB 4608 arch/powerpc/xmon/ppc-opc.c {"rotlw.", MME(23,31,1), MMBME_MASK, PPCCOM, PPCVLE, {RA, RS, RB}}, RB 4609 arch/powerpc/xmon/ppc-opc.c {"rlwnm.", M(23,1), M_MASK, PPCCOM, PPCVLE, {RA, RS, RB, MBE, ME}}, RB 4610 arch/powerpc/xmon/ppc-opc.c {"rlnm.", M(23,1), M_MASK, PWRCOM, PPCVLE, {RA, RS, RB, MBE, ME}}, RB 4648 arch/powerpc/xmon/ppc-opc.c {"rotld", MDS(30,8,0), MDSMB_MASK, PPC64, PPCVLE, {RA, RS, RB}}, RB 4649 arch/powerpc/xmon/ppc-opc.c {"rldcl", MDS(30,8,0), MDS_MASK, PPC64, PPCVLE, {RA, RS, RB, MB6}}, RB 4650 arch/powerpc/xmon/ppc-opc.c {"rotld.", MDS(30,8,1), MDSMB_MASK, PPC64, PPCVLE, {RA, RS, RB}}, RB 4651 arch/powerpc/xmon/ppc-opc.c {"rldcl.", MDS(30,8,1), MDS_MASK, PPC64, PPCVLE, {RA, RS, RB, MB6}}, RB 4653 arch/powerpc/xmon/ppc-opc.c {"rldcr", MDS(30,9,0), MDS_MASK, PPC64, PPCVLE, {RA, RS, RB, ME6}}, RB 4654 arch/powerpc/xmon/ppc-opc.c {"rldcr.", MDS(30,9,1), MDS_MASK, PPC64, PPCVLE, {RA, RS, RB, ME6}}, RB 4656 arch/powerpc/xmon/ppc-opc.c {"cmpw", XOPL(31,0,0), XCMPL_MASK, PPCCOM, 0, {OBF, RA, RB}}, RB 4657 arch/powerpc/xmon/ppc-opc.c {"cmpd", XOPL(31,0,1), XCMPL_MASK, PPC64, 0, {OBF, RA, RB}}, RB 4658 arch/powerpc/xmon/ppc-opc.c {"cmp", X(31,0), XCMP_MASK, PPC, 0, {BF, L32OPT, RA, RB}}, RB 4659 arch/powerpc/xmon/ppc-opc.c {"cmp", X(31,0), XCMPL_MASK, PWRCOM, PPC, {BF, RA, RB}}, RB 4661 arch/powerpc/xmon/ppc-opc.c {"twlgt", XTO(31,4,TOLGT), XTO_MASK, PPCCOM, 0, {RA, RB}}, RB 4662 arch/powerpc/xmon/ppc-opc.c {"tlgt", XTO(31,4,TOLGT), XTO_MASK, PWRCOM, 0, {RA, RB}}, RB 4663 arch/powerpc/xmon/ppc-opc.c {"twllt", XTO(31,4,TOLLT), XTO_MASK, PPCCOM, 0, {RA, RB}}, RB 4664 arch/powerpc/xmon/ppc-opc.c {"tllt", XTO(31,4,TOLLT), XTO_MASK, PWRCOM, 0, {RA, RB}}, RB 4665 arch/powerpc/xmon/ppc-opc.c {"tweq", XTO(31,4,TOEQ), XTO_MASK, PPCCOM, 0, {RA, RB}}, RB 4666 arch/powerpc/xmon/ppc-opc.c {"teq", XTO(31,4,TOEQ), XTO_MASK, PWRCOM, 0, {RA, RB}}, RB 4667 arch/powerpc/xmon/ppc-opc.c {"twlge", XTO(31,4,TOLGE), XTO_MASK, PPCCOM, 0, {RA, RB}}, RB 4668 arch/powerpc/xmon/ppc-opc.c {"tlge", XTO(31,4,TOLGE), XTO_MASK, PWRCOM, 0, {RA, RB}}, RB 4669 arch/powerpc/xmon/ppc-opc.c {"twlnl", XTO(31,4,TOLNL), XTO_MASK, PPCCOM, 0, {RA, RB}}, RB 4670 arch/powerpc/xmon/ppc-opc.c {"tlnl", XTO(31,4,TOLNL), XTO_MASK, PWRCOM, 0, {RA, RB}}, RB 4671 arch/powerpc/xmon/ppc-opc.c {"twlle", XTO(31,4,TOLLE), XTO_MASK, PPCCOM, 0, {RA, RB}}, RB 4672 arch/powerpc/xmon/ppc-opc.c {"tlle", XTO(31,4,TOLLE), XTO_MASK, PWRCOM, 0, {RA, RB}}, RB 4673 arch/powerpc/xmon/ppc-opc.c {"twlng", XTO(31,4,TOLNG), XTO_MASK, PPCCOM, 0, {RA, RB}}, RB 4674 arch/powerpc/xmon/ppc-opc.c {"tlng", XTO(31,4,TOLNG), XTO_MASK, PWRCOM, 0, {RA, RB}}, RB 4675 arch/powerpc/xmon/ppc-opc.c {"twgt", XTO(31,4,TOGT), XTO_MASK, PPCCOM, 0, {RA, RB}}, RB 4676 arch/powerpc/xmon/ppc-opc.c {"tgt", XTO(31,4,TOGT), XTO_MASK, PWRCOM, 0, {RA, RB}}, RB 4677 arch/powerpc/xmon/ppc-opc.c {"twge", XTO(31,4,TOGE), XTO_MASK, PPCCOM, 0, {RA, RB}}, RB 4678 arch/powerpc/xmon/ppc-opc.c {"tge", XTO(31,4,TOGE), XTO_MASK, PWRCOM, 0, {RA, RB}}, RB 4679 arch/powerpc/xmon/ppc-opc.c {"twnl", XTO(31,4,TONL), XTO_MASK, PPCCOM, 0, {RA, RB}}, RB 4680 arch/powerpc/xmon/ppc-opc.c {"tnl", XTO(31,4,TONL), XTO_MASK, PWRCOM, 0, {RA, RB}}, RB 4681 arch/powerpc/xmon/ppc-opc.c {"twlt", XTO(31,4,TOLT), XTO_MASK, PPCCOM, 0, {RA, RB}}, RB 4682 arch/powerpc/xmon/ppc-opc.c {"tlt", XTO(31,4,TOLT), XTO_MASK, PWRCOM, 0, {RA, RB}}, RB 4683 arch/powerpc/xmon/ppc-opc.c {"twle", XTO(31,4,TOLE), XTO_MASK, PPCCOM, 0, {RA, RB}}, RB 4684 arch/powerpc/xmon/ppc-opc.c {"tle", XTO(31,4,TOLE), XTO_MASK, PWRCOM, 0, {RA, RB}}, RB 4685 arch/powerpc/xmon/ppc-opc.c {"twng", XTO(31,4,TONG), XTO_MASK, PPCCOM, 0, {RA, RB}}, RB 4686 arch/powerpc/xmon/ppc-opc.c {"tng", XTO(31,4,TONG), XTO_MASK, PWRCOM, 0, {RA, RB}}, RB 4687 arch/powerpc/xmon/ppc-opc.c {"twne", XTO(31,4,TONE), XTO_MASK, PPCCOM, 0, {RA, RB}}, RB 4688 arch/powerpc/xmon/ppc-opc.c {"tne", XTO(31,4,TONE), XTO_MASK, PWRCOM, 0, {RA, RB}}, RB 4690 arch/powerpc/xmon/ppc-opc.c {"twu", XTO(31,4,TOU), XTO_MASK, PPCCOM, 0, {RA, RB}}, RB 4691 arch/powerpc/xmon/ppc-opc.c {"tu", XTO(31,4,TOU), XTO_MASK, PWRCOM, 0, {RA, RB}}, RB 4692 arch/powerpc/xmon/ppc-opc.c {"tw", X(31,4), X_MASK, PPCCOM, 0, {TO, RA, RB}}, RB 4693 arch/powerpc/xmon/ppc-opc.c {"t", X(31,4), X_MASK, PWRCOM, 0, {TO, RA, RB}}, RB 4695 arch/powerpc/xmon/ppc-opc.c {"lvsl", X(31,6), X_MASK, PPCVEC, 0, {VD, RA0, RB}}, RB 4696 arch/powerpc/xmon/ppc-opc.c {"lvebx", X(31,7), X_MASK, PPCVEC, 0, {VD, RA0, RB}}, RB 4697 arch/powerpc/xmon/ppc-opc.c {"lbfcmx", APU(31,7,0), APU_MASK, PPC405, 0, {FCRT, RA, RB}}, RB 4699 arch/powerpc/xmon/ppc-opc.c {"subfc", XO(31,8,0,0), XO_MASK, PPCCOM, 0, {RT, RA, RB}}, RB 4700 arch/powerpc/xmon/ppc-opc.c {"sf", XO(31,8,0,0), XO_MASK, PWRCOM, 0, {RT, RA, RB}}, RB 4701 arch/powerpc/xmon/ppc-opc.c {"subc", XO(31,8,0,0), XO_MASK, PPCCOM, 0, {RT, RB, RA}}, RB 4702 arch/powerpc/xmon/ppc-opc.c {"subfc.", XO(31,8,0,1), XO_MASK, PPCCOM, 0, {RT, RA, RB}}, RB 4703 arch/powerpc/xmon/ppc-opc.c {"sf.", XO(31,8,0,1), XO_MASK, PWRCOM, 0, {RT, RA, RB}}, RB 4704 arch/powerpc/xmon/ppc-opc.c {"subc.", XO(31,8,0,1), XO_MASK, PPCCOM, 0, {RT, RB, RA}}, RB 4706 arch/powerpc/xmon/ppc-opc.c {"mulhdu", XO(31,9,0,0), XO_MASK, PPC64, 0, {RT, RA, RB}}, RB 4707 arch/powerpc/xmon/ppc-opc.c {"mulhdu.", XO(31,9,0,1), XO_MASK, PPC64, 0, {RT, RA, RB}}, RB 4709 arch/powerpc/xmon/ppc-opc.c {"addc", XO(31,10,0,0), XO_MASK, PPCCOM, 0, {RT, RA, RB}}, RB 4710 arch/powerpc/xmon/ppc-opc.c {"a", XO(31,10,0,0), XO_MASK, PWRCOM, 0, {RT, RA, RB}}, RB 4711 arch/powerpc/xmon/ppc-opc.c {"addc.", XO(31,10,0,1), XO_MASK, PPCCOM, 0, {RT, RA, RB}}, RB 4712 arch/powerpc/xmon/ppc-opc.c {"a.", XO(31,10,0,1), XO_MASK, PWRCOM, 0, {RT, RA, RB}}, RB 4714 arch/powerpc/xmon/ppc-opc.c {"mulhwu", XO(31,11,0,0), XO_MASK, PPC, 0, {RT, RA, RB}}, RB 4715 arch/powerpc/xmon/ppc-opc.c {"mulhwu.", XO(31,11,0,1), XO_MASK, PPC, 0, {RT, RA, RB}}, RB 4717 arch/powerpc/xmon/ppc-opc.c {"lxsiwzx", X(31,12), XX1_MASK, PPCVSX2, 0, {XT6, RA0, RB}}, RB 4719 arch/powerpc/xmon/ppc-opc.c {"isellt", X(31,15), X_MASK, PPCISEL, 0, {RT, RA0, RB}}, RB 4723 arch/powerpc/xmon/ppc-opc.c {"tlbilxva", XTO(31,18,3), XTO_MASK, E500MC|PPCA2, 0, {RA0, RB}}, RB 4724 arch/powerpc/xmon/ppc-opc.c {"tlbilx", X(31,18), X_MASK, E500MC|PPCA2, 0, {T, RA0, RB}}, RB 4729 arch/powerpc/xmon/ppc-opc.c {"lwarx", X(31,20), XEH_MASK, PPC, 0, {RT, RA0, RB, EH}}, RB 4731 arch/powerpc/xmon/ppc-opc.c {"ldx", X(31,21), X_MASK, PPC64, 0, {RT, RA0, RB}}, RB 4733 arch/powerpc/xmon/ppc-opc.c {"icbt", X(31,22), X_MASK, BOOKE|PPCE300|PPCA2|PPC476, 0, {CT, RA0, RB}}, RB 4735 arch/powerpc/xmon/ppc-opc.c {"lwzx", X(31,23), X_MASK, PPCCOM, 0, {RT, RA0, RB}}, RB 4736 arch/powerpc/xmon/ppc-opc.c {"lx", X(31,23), X_MASK, PWRCOM, 0, {RT, RA, RB}}, RB 4738 arch/powerpc/xmon/ppc-opc.c {"slw", XRC(31,24,0), X_MASK, PPCCOM, 0, {RA, RS, RB}}, RB 4739 arch/powerpc/xmon/ppc-opc.c {"sl", XRC(31,24,0), X_MASK, PWRCOM, 0, {RA, RS, RB}}, RB 4740 arch/powerpc/xmon/ppc-opc.c {"slw.", XRC(31,24,1), X_MASK, PPCCOM, 0, {RA, RS, RB}}, RB 4741 arch/powerpc/xmon/ppc-opc.c {"sl.", XRC(31,24,1), X_MASK, PWRCOM, 0, {RA, RS, RB}}, RB 4748 arch/powerpc/xmon/ppc-opc.c {"sld", XRC(31,27,0), X_MASK, PPC64, 0, {RA, RS, RB}}, RB 4749 arch/powerpc/xmon/ppc-opc.c {"sld.", XRC(31,27,1), X_MASK, PPC64, 0, {RA, RS, RB}}, RB 4751 arch/powerpc/xmon/ppc-opc.c {"and", XRC(31,28,0), X_MASK, COM, 0, {RA, RS, RB}}, RB 4752 arch/powerpc/xmon/ppc-opc.c {"and.", XRC(31,28,1), X_MASK, COM, 0, {RA, RS, RB}}, RB 4754 arch/powerpc/xmon/ppc-opc.c {"maskg", XRC(31,29,0), X_MASK, M601, PPCA2, {RA, RS, RB}}, RB 4755 arch/powerpc/xmon/ppc-opc.c {"maskg.", XRC(31,29,1), X_MASK, M601, PPCA2, {RA, RS, RB}}, RB 4757 arch/powerpc/xmon/ppc-opc.c {"ldepx", X(31,29), X_MASK, E500MC|PPCA2, 0, {RT, RA0, RB}}, RB 4762 arch/powerpc/xmon/ppc-opc.c {"lwepx", X(31,31), X_MASK, E500MC|PPCA2, 0, {RT, RA0, RB}}, RB 4764 arch/powerpc/xmon/ppc-opc.c {"cmplw", XOPL(31,32,0), XCMPL_MASK, PPCCOM, 0, {OBF, RA, RB}}, RB 4765 arch/powerpc/xmon/ppc-opc.c {"cmpld", XOPL(31,32,1), XCMPL_MASK, PPC64, 0, {OBF, RA, RB}}, RB 4766 arch/powerpc/xmon/ppc-opc.c {"cmpl", X(31,32), XCMP_MASK, PPC, 0, {BF, L32OPT, RA, RB}}, RB 4767 arch/powerpc/xmon/ppc-opc.c {"cmpl", X(31,32), XCMPL_MASK, PWRCOM, PPC, {BF, RA, RB}}, RB 4769 arch/powerpc/xmon/ppc-opc.c {"lvsr", X(31,38), X_MASK, PPCVEC, 0, {VD, RA0, RB}}, RB 4770 arch/powerpc/xmon/ppc-opc.c {"lvehx", X(31,39), X_MASK, PPCVEC, 0, {VD, RA0, RB}}, RB 4771 arch/powerpc/xmon/ppc-opc.c {"lhfcmx", APU(31,39,0), APU_MASK, PPC405, 0, {FCRT, RA, RB}}, RB 4773 arch/powerpc/xmon/ppc-opc.c {"mviwsplt", X(31,46), X_MASK, PPCVEC2, 0, {VD, RA, RB}}, RB 4775 arch/powerpc/xmon/ppc-opc.c {"iselgt", X(31,47), X_MASK, PPCISEL, 0, {RT, RA0, RB}}, RB 4777 arch/powerpc/xmon/ppc-opc.c {"lvewx", X(31,71), X_MASK, PPCVEC, 0, {VD, RA0, RB}}, RB 4779 arch/powerpc/xmon/ppc-opc.c {"addg6s", XO(31,74,0,0), XO_MASK, POWER6, 0, {RT, RA, RB}}, RB 4781 arch/powerpc/xmon/ppc-opc.c {"lxsiwax", X(31,76), XX1_MASK, PPCVSX2, 0, {XT6, RA0, RB}}, RB 4783 arch/powerpc/xmon/ppc-opc.c {"iseleq", X(31,79), X_MASK, PPCISEL, 0, {RT, RA0, RB}}, RB 4785 arch/powerpc/xmon/ppc-opc.c {"isel", XISEL(31,15), XISEL_MASK, PPCISEL|TITAN, 0, {RT, RA0, RB, CRB}}, RB 4787 arch/powerpc/xmon/ppc-opc.c {"subf", XO(31,40,0,0), XO_MASK, PPC, 0, {RT, RA, RB}}, RB 4788 arch/powerpc/xmon/ppc-opc.c {"sub", XO(31,40,0,0), XO_MASK, PPC, 0, {RT, RB, RA}}, RB 4789 arch/powerpc/xmon/ppc-opc.c {"subf.", XO(31,40,0,1), XO_MASK, PPC, 0, {RT, RA, RB}}, RB 4790 arch/powerpc/xmon/ppc-opc.c {"sub.", XO(31,40,0,1), XO_MASK, PPC, 0, {RT, RB, RA}}, RB 4795 arch/powerpc/xmon/ppc-opc.c {"eratilx", X(31,51), X_MASK, PPCA2, 0, {ERAT_T, RA, RB}}, RB 4797 arch/powerpc/xmon/ppc-opc.c {"lbarx", X(31,52), XEH_MASK, POWER8|E6500, 0, {RT, RA0, RB, EH}}, RB 4799 arch/powerpc/xmon/ppc-opc.c {"ldux", X(31,53), X_MASK, PPC64, 0, {RT, RAL, RB}}, RB 4801 arch/powerpc/xmon/ppc-opc.c {"dcbst", X(31,54), XRT_MASK, PPC, 0, {RA0, RB}}, RB 4803 arch/powerpc/xmon/ppc-opc.c {"lwzux", X(31,55), X_MASK, PPCCOM, 0, {RT, RAL, RB}}, RB 4804 arch/powerpc/xmon/ppc-opc.c {"lux", X(31,55), X_MASK, PWRCOM, 0, {RT, RA, RB}}, RB 4809 arch/powerpc/xmon/ppc-opc.c {"andc", XRC(31,60,0), X_MASK, COM, 0, {RA, RS, RB}}, RB 4810 arch/powerpc/xmon/ppc-opc.c {"andc.", XRC(31,60,1), X_MASK, COM, 0, {RA, RS, RB}}, RB 4816 arch/powerpc/xmon/ppc-opc.c {"dcbstep", XRT(31,63,0), XRT_MASK, E500MC|PPCA2, 0, {RA0, RB}}, RB 4818 arch/powerpc/xmon/ppc-opc.c {"tdlgt", XTO(31,68,TOLGT), XTO_MASK, PPC64, 0, {RA, RB}}, RB 4819 arch/powerpc/xmon/ppc-opc.c {"tdllt", XTO(31,68,TOLLT), XTO_MASK, PPC64, 0, {RA, RB}}, RB 4820 arch/powerpc/xmon/ppc-opc.c {"tdeq", XTO(31,68,TOEQ), XTO_MASK, PPC64, 0, {RA, RB}}, RB 4821 arch/powerpc/xmon/ppc-opc.c {"tdlge", XTO(31,68,TOLGE), XTO_MASK, PPC64, 0, {RA, RB}}, RB 4822 arch/powerpc/xmon/ppc-opc.c {"tdlnl", XTO(31,68,TOLNL), XTO_MASK, PPC64, 0, {RA, RB}}, RB 4823 arch/powerpc/xmon/ppc-opc.c {"tdlle", XTO(31,68,TOLLE), XTO_MASK, PPC64, 0, {RA, RB}}, RB 4824 arch/powerpc/xmon/ppc-opc.c {"tdlng", XTO(31,68,TOLNG), XTO_MASK, PPC64, 0, {RA, RB}}, RB 4825 arch/powerpc/xmon/ppc-opc.c {"tdgt", XTO(31,68,TOGT), XTO_MASK, PPC64, 0, {RA, RB}}, RB 4826 arch/powerpc/xmon/ppc-opc.c {"tdge", XTO(31,68,TOGE), XTO_MASK, PPC64, 0, {RA, RB}}, RB 4827 arch/powerpc/xmon/ppc-opc.c {"tdnl", XTO(31,68,TONL), XTO_MASK, PPC64, 0, {RA, RB}}, RB 4828 arch/powerpc/xmon/ppc-opc.c {"tdlt", XTO(31,68,TOLT), XTO_MASK, PPC64, 0, {RA, RB}}, RB 4829 arch/powerpc/xmon/ppc-opc.c {"tdle", XTO(31,68,TOLE), XTO_MASK, PPC64, 0, {RA, RB}}, RB 4830 arch/powerpc/xmon/ppc-opc.c {"tdng", XTO(31,68,TONG), XTO_MASK, PPC64, 0, {RA, RB}}, RB 4831 arch/powerpc/xmon/ppc-opc.c {"tdne", XTO(31,68,TONE), XTO_MASK, PPC64, 0, {RA, RB}}, RB 4832 arch/powerpc/xmon/ppc-opc.c {"tdu", XTO(31,68,TOU), XTO_MASK, PPC64, 0, {RA, RB}}, RB 4833 arch/powerpc/xmon/ppc-opc.c {"td", X(31,68), X_MASK, PPC64, 0, {TO, RA, RB}}, RB 4835 arch/powerpc/xmon/ppc-opc.c {"lwfcmx", APU(31,71,0), APU_MASK, PPC405, 0, {FCRT, RA, RB}}, RB 4836 arch/powerpc/xmon/ppc-opc.c {"mulhd", XO(31,73,0,0), XO_MASK, PPC64, 0, {RT, RA, RB}}, RB 4837 arch/powerpc/xmon/ppc-opc.c {"mulhd.", XO(31,73,0,1), XO_MASK, PPC64, 0, {RT, RA, RB}}, RB 4839 arch/powerpc/xmon/ppc-opc.c {"mulhw", XO(31,75,0,0), XO_MASK, PPC, 0, {RT, RA, RB}}, RB 4840 arch/powerpc/xmon/ppc-opc.c {"mulhw.", XO(31,75,0,1), XO_MASK, PPC, 0, {RT, RA, RB}}, RB 4842 arch/powerpc/xmon/ppc-opc.c {"dlmzb", XRC(31,78,0), X_MASK, PPC403|PPC440|TITAN, 0, {RA, RS, RB}}, RB 4843 arch/powerpc/xmon/ppc-opc.c {"dlmzb.", XRC(31,78,1), X_MASK, PPC403|PPC440|TITAN, 0, {RA, RS, RB}}, RB 4849 arch/powerpc/xmon/ppc-opc.c {"ldarx", X(31,84), XEH_MASK, PPC64, 0, {RT, RA0, RB, EH}}, RB 4851 arch/powerpc/xmon/ppc-opc.c {"dcbfl", XOPL(31,86,1), XRT_MASK, POWER5, PPC476, {RA0, RB}}, RB 4852 arch/powerpc/xmon/ppc-opc.c {"dcbf", X(31,86), XLRT_MASK, PPC, 0, {RA0, RB, L2OPT}}, RB 4854 arch/powerpc/xmon/ppc-opc.c {"lbzx", X(31,87), X_MASK, COM, 0, {RT, RA0, RB}}, RB 4856 arch/powerpc/xmon/ppc-opc.c {"lbepx", X(31,95), X_MASK, E500MC|PPCA2, 0, {RT, RA0, RB}}, RB 4860 arch/powerpc/xmon/ppc-opc.c {"lvx", X(31,103), X_MASK, PPCVEC, 0, {VD, RA0, RB}}, RB 4861 arch/powerpc/xmon/ppc-opc.c {"lqfcmx", APU(31,103,0), APU_MASK, PPC405, 0, {FCRT, RA, RB}}, RB 4866 arch/powerpc/xmon/ppc-opc.c {"mul", XO(31,107,0,0), XO_MASK, M601, 0, {RT, RA, RB}}, RB 4867 arch/powerpc/xmon/ppc-opc.c {"mul.", XO(31,107,0,1), XO_MASK, M601, 0, {RT, RA, RB}}, RB 4869 arch/powerpc/xmon/ppc-opc.c {"mvidsplt", X(31,110), X_MASK, PPCVEC2, 0, {VD, RA, RB}}, RB 4871 arch/powerpc/xmon/ppc-opc.c {"mtsrdin", X(31,114), XRA_MASK, PPC64, 0, {RS, RB}}, RB 4877 arch/powerpc/xmon/ppc-opc.c {"lharx", X(31,116), XEH_MASK, POWER8|E6500, 0, {RT, RA0, RB, EH}}, RB 4879 arch/powerpc/xmon/ppc-opc.c {"clf", X(31,118), XTO_MASK, POWER, 0, {RA, RB}}, RB 4881 arch/powerpc/xmon/ppc-opc.c {"lbzux", X(31,119), X_MASK, COM, 0, {RT, RAL, RB}}, RB 4886 arch/powerpc/xmon/ppc-opc.c {"nor", XRC(31,124,0), X_MASK, COM, 0, {RA, RS, RB}}, RB 4888 arch/powerpc/xmon/ppc-opc.c {"nor.", XRC(31,124,1), X_MASK, COM, 0, {RA, RS, RB}}, RB 4890 arch/powerpc/xmon/ppc-opc.c {"dcbfep", XRT(31,127,0), XRT_MASK, E500MC|PPCA2, 0, {RA0, RB}}, RB 4896 arch/powerpc/xmon/ppc-opc.c {"dcbtstls", X(31,134), X_MASK, PPCCHLK|PPC476|TITAN, 0, {CT, RA0, RB}}, RB 4898 arch/powerpc/xmon/ppc-opc.c {"stvebx", X(31,135), X_MASK, PPCVEC, 0, {VS, RA0, RB}}, RB 4899 arch/powerpc/xmon/ppc-opc.c {"stbfcmx", APU(31,135,0), APU_MASK, PPC405, 0, {FCRT, RA, RB}}, RB 4901 arch/powerpc/xmon/ppc-opc.c {"subfe", XO(31,136,0,0), XO_MASK, PPCCOM, 0, {RT, RA, RB}}, RB 4902 arch/powerpc/xmon/ppc-opc.c {"sfe", XO(31,136,0,0), XO_MASK, PWRCOM, 0, {RT, RA, RB}}, RB 4903 arch/powerpc/xmon/ppc-opc.c {"subfe.", XO(31,136,0,1), XO_MASK, PPCCOM, 0, {RT, RA, RB}}, RB 4904 arch/powerpc/xmon/ppc-opc.c {"sfe.", XO(31,136,0,1), XO_MASK, PWRCOM, 0, {RT, RA, RB}}, RB 4906 arch/powerpc/xmon/ppc-opc.c {"adde", XO(31,138,0,0), XO_MASK, PPCCOM, 0, {RT, RA, RB}}, RB 4907 arch/powerpc/xmon/ppc-opc.c {"ae", XO(31,138,0,0), XO_MASK, PWRCOM, 0, {RT, RA, RB}}, RB 4908 arch/powerpc/xmon/ppc-opc.c {"adde.", XO(31,138,0,1), XO_MASK, PPCCOM, 0, {RT, RA, RB}}, RB 4909 arch/powerpc/xmon/ppc-opc.c {"ae.", XO(31,138,0,1), XO_MASK, PWRCOM, 0, {RT, RA, RB}}, RB 4911 arch/powerpc/xmon/ppc-opc.c {"stxsiwx", X(31,140), XX1_MASK, PPCVSX2, 0, {XS6, RA0, RB}}, RB 4913 arch/powerpc/xmon/ppc-opc.c {"msgsndp", XRTRA(31,142,0,0), XRTRA_MASK, POWER8, 0, {RB}}, RB 4914 arch/powerpc/xmon/ppc-opc.c {"dcbtstlse", X(31,142), X_MASK, PPCCHLK, E500MC, {CT, RA0, RB}}, RB 4924 arch/powerpc/xmon/ppc-opc.c {"eratsx", XRC(31,147,0), X_MASK, PPCA2, 0, {RT, RA0, RB}}, RB 4925 arch/powerpc/xmon/ppc-opc.c {"eratsx.", XRC(31,147,1), X_MASK, PPCA2, 0, {RT, RA0, RB}}, RB 4927 arch/powerpc/xmon/ppc-opc.c {"stdx", X(31,149), X_MASK, PPC64, 0, {RS, RA0, RB}}, RB 4929 arch/powerpc/xmon/ppc-opc.c {"stwcx.", XRC(31,150,1), X_MASK, PPC, 0, {RS, RA0, RB}}, RB 4931 arch/powerpc/xmon/ppc-opc.c {"stwx", X(31,151), X_MASK, PPCCOM, 0, {RS, RA0, RB}}, RB 4932 arch/powerpc/xmon/ppc-opc.c {"stx", X(31,151), X_MASK, PWRCOM, 0, {RS, RA, RB}}, RB 4934 arch/powerpc/xmon/ppc-opc.c {"slq", XRC(31,152,0), X_MASK, M601, 0, {RA, RS, RB}}, RB 4935 arch/powerpc/xmon/ppc-opc.c {"slq.", XRC(31,152,1), X_MASK, M601, 0, {RA, RS, RB}}, RB 4937 arch/powerpc/xmon/ppc-opc.c {"sle", XRC(31,153,0), X_MASK, M601, 0, {RA, RS, RB}}, RB 4938 arch/powerpc/xmon/ppc-opc.c {"sle.", XRC(31,153,1), X_MASK, M601, 0, {RA, RS, RB}}, RB 4942 arch/powerpc/xmon/ppc-opc.c {"stdepx", X(31,157), X_MASK, E500MC|PPCA2, 0, {RS, RA0, RB}}, RB 4944 arch/powerpc/xmon/ppc-opc.c {"stwepx", X(31,159), X_MASK, E500MC|PPCA2, 0, {RS, RA0, RB}}, RB 4948 arch/powerpc/xmon/ppc-opc.c {"dcbtls", X(31,166), X_MASK, PPCCHLK|PPC476|TITAN, 0, {CT, RA0, RB}}, RB 4950 arch/powerpc/xmon/ppc-opc.c {"stvehx", X(31,167), X_MASK, PPCVEC, 0, {VS, RA0, RB}}, RB 4951 arch/powerpc/xmon/ppc-opc.c {"sthfcmx", APU(31,167,0), APU_MASK, PPC405, 0, {FCRT, RA, RB}}, RB 4953 arch/powerpc/xmon/ppc-opc.c {"addex", ZRC(31,170,0), Z2_MASK, POWER9, 0, {RT, RA, RB, CY}}, RB 4955 arch/powerpc/xmon/ppc-opc.c {"msgclrp", XRTRA(31,174,0,0), XRTRA_MASK, POWER8, 0, {RB}}, RB 4956 arch/powerpc/xmon/ppc-opc.c {"dcbtlse", X(31,174), X_MASK, PPCCHLK, E500MC, {CT, RA0, RB}}, RB 4965 arch/powerpc/xmon/ppc-opc.c {"stdux", X(31,181), X_MASK, PPC64, 0, {RS, RAS, RB}}, RB 4967 arch/powerpc/xmon/ppc-opc.c {"stqcx.", XRC(31,182,1), X_MASK, POWER8, 0, {RSQ, RA0, RB}}, RB 4970 arch/powerpc/xmon/ppc-opc.c {"stwux", X(31,183), X_MASK, PPCCOM, 0, {RS, RAS, RB}}, RB 4971 arch/powerpc/xmon/ppc-opc.c {"stux", X(31,183), X_MASK, PWRCOM, 0, {RS, RA0, RB}}, RB 4978 arch/powerpc/xmon/ppc-opc.c {"cmprb", X(31,192), XCMP_MASK, POWER9, 0, {BF, L, RA, RB}}, RB 4980 arch/powerpc/xmon/ppc-opc.c {"icblq.", XRC(31,198,1), X_MASK, E6500, 0, {CT, RA0, RB}}, RB 4982 arch/powerpc/xmon/ppc-opc.c {"stvewx", X(31,199), X_MASK, PPCVEC, 0, {VS, RA0, RB}}, RB 4983 arch/powerpc/xmon/ppc-opc.c {"stwfcmx", APU(31,199,0), APU_MASK, PPC405, 0, {FCRT, RA, RB}}, RB 4995 arch/powerpc/xmon/ppc-opc.c {"msgsnd", XRTRA(31,206,0,0), XRTRA_MASK, E500MC|PPCA2|POWER8, 0, {RB}}, RB 5004 arch/powerpc/xmon/ppc-opc.c {"ldawx.", XRC(31,212,1), X_MASK, PPCA2, 0, {RT, RA0, RB}}, RB 5006 arch/powerpc/xmon/ppc-opc.c {"stdcx.", XRC(31,214,1), X_MASK, PPC64, 0, {RS, RA0, RB}}, RB 5008 arch/powerpc/xmon/ppc-opc.c {"stbx", X(31,215), X_MASK, COM, 0, {RS, RA0, RB}}, RB 5010 arch/powerpc/xmon/ppc-opc.c {"sllq", XRC(31,216,0), X_MASK, M601, 0, {RA, RS, RB}}, RB 5011 arch/powerpc/xmon/ppc-opc.c {"sllq.", XRC(31,216,1), X_MASK, M601, 0, {RA, RS, RB}}, RB 5013 arch/powerpc/xmon/ppc-opc.c {"sleq", XRC(31,217,0), X_MASK, M601, 0, {RA, RS, RB}}, RB 5014 arch/powerpc/xmon/ppc-opc.c {"sleq.", XRC(31,217,1), X_MASK, M601, 0, {RA, RS, RB}}, RB 5016 arch/powerpc/xmon/ppc-opc.c {"stbepx", X(31,223), X_MASK, E500MC|PPCA2, 0, {RS, RA0, RB}}, RB 5018 arch/powerpc/xmon/ppc-opc.c {"cmpeqb", X(31,224), XCMPL_MASK, POWER9, 0, {BF, RA, RB}}, RB 5020 arch/powerpc/xmon/ppc-opc.c {"icblc", X(31,230), X_MASK, PPCCHLK|PPC476|TITAN, 0, {CT, RA0, RB}}, RB 5022 arch/powerpc/xmon/ppc-opc.c {"stvx", X(31,231), X_MASK, PPCVEC, 0, {VS, RA0, RB}}, RB 5023 arch/powerpc/xmon/ppc-opc.c {"stqfcmx", APU(31,231,0), APU_MASK, PPC405, 0, {FCRT, RA, RB}}, RB 5030 arch/powerpc/xmon/ppc-opc.c {"mulld", XO(31,233,0,0), XO_MASK, PPC64, 0, {RT, RA, RB}}, RB 5031 arch/powerpc/xmon/ppc-opc.c {"mulld.", XO(31,233,0,1), XO_MASK, PPC64, 0, {RT, RA, RB}}, RB 5038 arch/powerpc/xmon/ppc-opc.c {"mullw", XO(31,235,0,0), XO_MASK, PPCCOM, 0, {RT, RA, RB}}, RB 5039 arch/powerpc/xmon/ppc-opc.c {"muls", XO(31,235,0,0), XO_MASK, PWRCOM, 0, {RT, RA, RB}}, RB 5040 arch/powerpc/xmon/ppc-opc.c {"mullw.", XO(31,235,0,1), XO_MASK, PPCCOM, 0, {RT, RA, RB}}, RB 5041 arch/powerpc/xmon/ppc-opc.c {"muls.", XO(31,235,0,1), XO_MASK, PWRCOM, 0, {RT, RA, RB}}, RB 5043 arch/powerpc/xmon/ppc-opc.c {"icblce", X(31,238), X_MASK, PPCCHLK, E500MC|PPCA2, {CT, RA, RB}}, RB 5044 arch/powerpc/xmon/ppc-opc.c {"msgclr", XRTRA(31,238,0,0), XRTRA_MASK, E500MC|PPCA2|POWER8, 0, {RB}}, RB 5045 arch/powerpc/xmon/ppc-opc.c {"mtsrin", X(31,242), XRA_MASK, PPC, NON32, {RS, RB}}, RB 5046 arch/powerpc/xmon/ppc-opc.c {"mtsri", X(31,242), XRA_MASK, POWER, NON32, {RS, RB}}, RB 5052 arch/powerpc/xmon/ppc-opc.c {"dcbtstt", XRT(31,246,0x10), XRT_MASK, POWER7, 0, {RA0, RB}}, RB 5053 arch/powerpc/xmon/ppc-opc.c {"dcbtst", X(31,246), X_MASK, POWER4, DCBT_EO, {RA0, RB, CT}}, RB 5054 arch/powerpc/xmon/ppc-opc.c {"dcbtst", X(31,246), X_MASK, DCBT_EO, 0, {CT, RA0, RB}}, RB 5055 arch/powerpc/xmon/ppc-opc.c {"dcbtst", X(31,246), X_MASK, PPC, POWER4|DCBT_EO, {RA0, RB}}, RB 5057 arch/powerpc/xmon/ppc-opc.c {"stbux", X(31,247), X_MASK, COM, 0, {RS, RAS, RB}}, RB 5062 arch/powerpc/xmon/ppc-opc.c {"bpermd", X(31,252), X_MASK, POWER7|PPCA2, 0, {RA, RS, RB}}, RB 5064 arch/powerpc/xmon/ppc-opc.c {"dcbtstep", XRT(31,255,0), X_MASK, E500MC|PPCA2, 0, {RT, RA0, RB}}, RB 5069 arch/powerpc/xmon/ppc-opc.c {"lvexbx", X(31,261), X_MASK, PPCVEC2, 0, {VD, RA0, RB}}, RB 5071 arch/powerpc/xmon/ppc-opc.c {"icbt", X(31,262), XRT_MASK, PPC403, 0, {RA, RB}}, RB 5073 arch/powerpc/xmon/ppc-opc.c {"lvepxl", X(31,263), X_MASK, PPCVEC2, 0, {VD, RA0, RB}}, RB 5075 arch/powerpc/xmon/ppc-opc.c {"ldfcmx", APU(31,263,0), APU_MASK, PPC405, 0, {FCRT, RA, RB}}, RB 5076 arch/powerpc/xmon/ppc-opc.c {"doz", XO(31,264,0,0), XO_MASK, M601, 0, {RT, RA, RB}}, RB 5077 arch/powerpc/xmon/ppc-opc.c {"doz.", XO(31,264,0,1), XO_MASK, M601, 0, {RT, RA, RB}}, RB 5079 arch/powerpc/xmon/ppc-opc.c {"modud", X(31,265), X_MASK, POWER9, 0, {RT, RA, RB}}, RB 5081 arch/powerpc/xmon/ppc-opc.c {"add", XO(31,266,0,0), XO_MASK, PPCCOM, 0, {RT, RA, RB}}, RB 5082 arch/powerpc/xmon/ppc-opc.c {"cax", XO(31,266,0,0), XO_MASK, PWRCOM, 0, {RT, RA, RB}}, RB 5083 arch/powerpc/xmon/ppc-opc.c {"add.", XO(31,266,0,1), XO_MASK, PPCCOM, 0, {RT, RA, RB}}, RB 5084 arch/powerpc/xmon/ppc-opc.c {"cax.", XO(31,266,0,1), XO_MASK, PWRCOM, 0, {RT, RA, RB}}, RB 5086 arch/powerpc/xmon/ppc-opc.c {"moduw", X(31,267), X_MASK, POWER9, 0, {RT, RA, RB}}, RB 5088 arch/powerpc/xmon/ppc-opc.c {"lxvx", X(31,268), XX1_MASK|1<<6, PPCVSX3, 0, {XT6, RA0, RB}}, RB 5089 arch/powerpc/xmon/ppc-opc.c {"lxvl", X(31,269), XX1_MASK, PPCVSX3, 0, {XT6, RA0, RB}}, RB 5093 arch/powerpc/xmon/ppc-opc.c {"tlbiel", X(31,274), X_MASK|1<<20,POWER9, PPC476, {RB, RSO, RIC, PRS, X_R}}, RB 5094 arch/powerpc/xmon/ppc-opc.c {"tlbiel", X(31,274), XRTLRA_MASK, POWER4, POWER9|PPC476, {RB, LOPT}}, RB 5100 arch/powerpc/xmon/ppc-opc.c {"lscbx", XRC(31,277,0), X_MASK, M601, 0, {RT, RA, RB}}, RB 5101 arch/powerpc/xmon/ppc-opc.c {"lscbx.", XRC(31,277,1), X_MASK, M601, 0, {RT, RA, RB}}, RB 5103 arch/powerpc/xmon/ppc-opc.c {"dcbtt", XRT(31,278,0x10), XRT_MASK, POWER7, 0, {RA0, RB}}, RB 5104 arch/powerpc/xmon/ppc-opc.c {"dcbt", X(31,278), X_MASK, POWER4, DCBT_EO, {RA0, RB, CT}}, RB 5105 arch/powerpc/xmon/ppc-opc.c {"dcbt", X(31,278), X_MASK, DCBT_EO, 0, {CT, RA0, RB}}, RB 5106 arch/powerpc/xmon/ppc-opc.c {"dcbt", X(31,278), X_MASK, PPC, POWER4|DCBT_EO, {RA0, RB}}, RB 5108 arch/powerpc/xmon/ppc-opc.c {"lhzx", X(31,279), X_MASK, COM, 0, {RT, RA0, RB}}, RB 5112 arch/powerpc/xmon/ppc-opc.c {"eqv", XRC(31,284,0), X_MASK, COM, 0, {RA, RS, RB}}, RB 5113 arch/powerpc/xmon/ppc-opc.c {"eqv.", XRC(31,284,1), X_MASK, COM, 0, {RA, RS, RB}}, RB 5115 arch/powerpc/xmon/ppc-opc.c {"lhepx", X(31,287), X_MASK, E500MC|PPCA2, 0, {RT, RA0, RB}}, RB 5119 arch/powerpc/xmon/ppc-opc.c {"lvexhx", X(31,293), X_MASK, PPCVEC2, 0, {VD, RA0, RB}}, RB 5120 arch/powerpc/xmon/ppc-opc.c {"lvepx", X(31,295), X_MASK, PPCVEC2, 0, {VD, RA0, RB}}, RB 5122 arch/powerpc/xmon/ppc-opc.c {"lxvll", X(31,301), XX1_MASK, PPCVSX3, 0, {XT6, RA0, RB}}, RB 5126 arch/powerpc/xmon/ppc-opc.c {"tlbie", X(31,306), X_MASK|1<<20,POWER9, TITAN, {RB, RS, RIC, PRS, X_R}}, RB 5127 arch/powerpc/xmon/ppc-opc.c {"tlbie", X(31,306), XRA_MASK, POWER7, POWER9|TITAN, {RB, RS}}, RB 5128 arch/powerpc/xmon/ppc-opc.c {"tlbie", X(31,306), XRTLRA_MASK, PPC, E500|POWER7|TITAN, {RB, LOPT}}, RB 5129 arch/powerpc/xmon/ppc-opc.c {"tlbi", X(31,306), XRT_MASK, POWER, 0, {RA0, RB}}, RB 5133 arch/powerpc/xmon/ppc-opc.c {"ldmx", X(31,309), X_MASK, POWER9, 0, {RT, RA0, RB}}, RB 5135 arch/powerpc/xmon/ppc-opc.c {"eciwx", X(31,310), X_MASK, PPC, E500|TITAN, {RT, RA0, RB}}, RB 5137 arch/powerpc/xmon/ppc-opc.c {"lhzux", X(31,311), X_MASK, COM, 0, {RT, RAL, RB}}, RB 5141 arch/powerpc/xmon/ppc-opc.c {"xor", XRC(31,316,0), X_MASK, COM, 0, {RA, RS, RB}}, RB 5142 arch/powerpc/xmon/ppc-opc.c {"xor.", XRC(31,316,1), X_MASK, COM, 0, {RA, RS, RB}}, RB 5144 arch/powerpc/xmon/ppc-opc.c {"dcbtep", XRT(31,319,0), X_MASK, E500MC|PPCA2, 0, {RT, RA0, RB}}, RB 5183 arch/powerpc/xmon/ppc-opc.c {"lvexwx", X(31,325), X_MASK, PPCVEC2, 0, {VD, RA0, RB}}, RB 5185 arch/powerpc/xmon/ppc-opc.c {"dcread", X(31,326), X_MASK, PPC476|TITAN, 0, {RT, RA0, RB}}, RB 5187 arch/powerpc/xmon/ppc-opc.c {"div", XO(31,331,0,0), XO_MASK, M601, 0, {RT, RA, RB}}, RB 5188 arch/powerpc/xmon/ppc-opc.c {"div.", XO(31,331,0,1), XO_MASK, M601, 0, {RT, RA, RB}}, RB 5190 arch/powerpc/xmon/ppc-opc.c {"lxvdsx", X(31,332), XX1_MASK, PPCVSX, 0, {XT6, RA0, RB}}, RB 5399 arch/powerpc/xmon/ppc-opc.c {"lwax", X(31,341), X_MASK, PPC64, 0, {RT, RA0, RB}}, RB 5401 arch/powerpc/xmon/ppc-opc.c {"dst", XDSS(31,342,0), XDSS_MASK, PPCVEC, 0, {RA, RB, STRM}}, RB 5403 arch/powerpc/xmon/ppc-opc.c {"lhax", X(31,343), X_MASK, COM, 0, {RT, RA0, RB}}, RB 5405 arch/powerpc/xmon/ppc-opc.c {"lvxl", X(31,359), X_MASK, PPCVEC, 0, {VD, RA0, RB}}, RB 5410 arch/powerpc/xmon/ppc-opc.c {"divs", XO(31,363,0,0), XO_MASK, M601, 0, {RT, RA, RB}}, RB 5411 arch/powerpc/xmon/ppc-opc.c {"divs.", XO(31,363,0,1), XO_MASK, M601, 0, {RT, RA, RB}}, RB 5413 arch/powerpc/xmon/ppc-opc.c {"lxvwsx", X(31,364), XX1_MASK, PPCVSX3, 0, {XT6, RA0, RB}}, RB 5421 arch/powerpc/xmon/ppc-opc.c {"lwaux", X(31,373), X_MASK, PPC64, 0, {RT, RAL, RB}}, RB 5423 arch/powerpc/xmon/ppc-opc.c {"dstst", XDSS(31,374,0), XDSS_MASK, PPCVEC, 0, {RA, RB, STRM}}, RB 5425 arch/powerpc/xmon/ppc-opc.c {"lhaux", X(31,375), X_MASK, COM, 0, {RT, RAL, RB}}, RB 5432 arch/powerpc/xmon/ppc-opc.c {"stvexbx", X(31,389), X_MASK, PPCVEC2, 0, {VS, RA0, RB}}, RB 5434 arch/powerpc/xmon/ppc-opc.c {"dcblc", X(31,390), X_MASK, PPCCHLK|PPC476|TITAN, 0, {CT, RA0, RB}}, RB 5435 arch/powerpc/xmon/ppc-opc.c {"stdfcmx", APU(31,391,0), APU_MASK, PPC405, 0, {FCRT, RA, RB}}, RB 5437 arch/powerpc/xmon/ppc-opc.c {"divdeu", XO(31,393,0,0), XO_MASK, POWER7|PPCA2, 0, {RT, RA, RB}}, RB 5438 arch/powerpc/xmon/ppc-opc.c {"divdeu.", XO(31,393,0,1), XO_MASK, POWER7|PPCA2, 0, {RT, RA, RB}}, RB 5439 arch/powerpc/xmon/ppc-opc.c {"divweu", XO(31,395,0,0), XO_MASK, POWER7|PPCA2, 0, {RT, RA, RB}}, RB 5440 arch/powerpc/xmon/ppc-opc.c {"divweu.", XO(31,395,0,1), XO_MASK, POWER7|PPCA2, 0, {RT, RA, RB}}, RB 5442 arch/powerpc/xmon/ppc-opc.c {"stxvx", X(31,396), XX1_MASK, PPCVSX3, 0, {XS6, RA0, RB}}, RB 5443 arch/powerpc/xmon/ppc-opc.c {"stxvl", X(31,397), XX1_MASK, PPCVSX3, 0, {XS6, RA0, RB}}, RB 5445 arch/powerpc/xmon/ppc-opc.c {"dcblce", X(31,398), X_MASK, PPCCHLK, E500MC, {CT, RA, RB}}, RB 5447 arch/powerpc/xmon/ppc-opc.c {"slbmte", X(31,402), XRA_MASK, PPC64, 0, {RS, RB}}, RB 5451 arch/powerpc/xmon/ppc-opc.c {"pbt.", XRC(31,404,1), X_MASK, POWER8, 0, {RS, RA0, RB}}, RB 5453 arch/powerpc/xmon/ppc-opc.c {"icswx", XRC(31,406,0), X_MASK, POWER7|PPCA2, 0, {RS, RA, RB}}, RB 5454 arch/powerpc/xmon/ppc-opc.c {"icswx.", XRC(31,406,1), X_MASK, POWER7|PPCA2, 0, {RS, RA, RB}}, RB 5456 arch/powerpc/xmon/ppc-opc.c {"sthx", X(31,407), X_MASK, COM, 0, {RS, RA0, RB}}, RB 5458 arch/powerpc/xmon/ppc-opc.c {"orc", XRC(31,412,0), X_MASK, COM, 0, {RA, RS, RB}}, RB 5459 arch/powerpc/xmon/ppc-opc.c {"orc.", XRC(31,412,1), X_MASK, COM, 0, {RA, RS, RB}}, RB 5461 arch/powerpc/xmon/ppc-opc.c {"sthepx", X(31,415), X_MASK, E500MC|PPCA2, 0, {RS, RA0, RB}}, RB 5465 arch/powerpc/xmon/ppc-opc.c {"stvexhx", X(31,421), X_MASK, PPCVEC2, 0, {VS, RA0, RB}}, RB 5467 arch/powerpc/xmon/ppc-opc.c {"dcblq.", XRC(31,422,1), X_MASK, E6500, 0, {CT, RA0, RB}}, RB 5469 arch/powerpc/xmon/ppc-opc.c {"divde", XO(31,425,0,0), XO_MASK, POWER7|PPCA2, 0, {RT, RA, RB}}, RB 5470 arch/powerpc/xmon/ppc-opc.c {"divde.", XO(31,425,0,1), XO_MASK, POWER7|PPCA2, 0, {RT, RA, RB}}, RB 5471 arch/powerpc/xmon/ppc-opc.c {"divwe", XO(31,427,0,0), XO_MASK, POWER7|PPCA2, 0, {RT, RA, RB}}, RB 5472 arch/powerpc/xmon/ppc-opc.c {"divwe.", XO(31,427,0,1), XO_MASK, POWER7|PPCA2, 0, {RT, RA, RB}}, RB 5474 arch/powerpc/xmon/ppc-opc.c {"stxvll", X(31,429), XX1_MASK, PPCVSX3, 0, {XS6, RA0, RB}}, RB 5478 arch/powerpc/xmon/ppc-opc.c {"slbie", X(31,434), XRTRA_MASK, PPC64, 0, {RB}}, RB 5480 arch/powerpc/xmon/ppc-opc.c {"mtvsrdd", X(31,435), XX1_MASK, PPCVSX3, 0, {XT6, RA0, RB}}, RB 5482 arch/powerpc/xmon/ppc-opc.c {"ecowx", X(31,438), X_MASK, PPC, E500|TITAN, {RT, RA0, RB}}, RB 5484 arch/powerpc/xmon/ppc-opc.c {"sthux", X(31,439), X_MASK, COM, 0, {RS, RAS, RB}}, RB 5496 arch/powerpc/xmon/ppc-opc.c {"or", XRC(31,444,0), X_MASK, COM, 0, {RA, RS, RB}}, RB 5498 arch/powerpc/xmon/ppc-opc.c {"or.", XRC(31,444,1), X_MASK, COM, 0, {RA, RS, RB}}, RB 5537 arch/powerpc/xmon/ppc-opc.c {"stvexwx", X(31,453), X_MASK, PPCVEC2, 0, {VS, RA0, RB}}, RB 5542 arch/powerpc/xmon/ppc-opc.c {"divdu", XO(31,457,0,0), XO_MASK, PPC64, 0, {RT, RA, RB}}, RB 5543 arch/powerpc/xmon/ppc-opc.c {"divdu.", XO(31,457,0,1), XO_MASK, PPC64, 0, {RT, RA, RB}}, RB 5545 arch/powerpc/xmon/ppc-opc.c {"divwu", XO(31,459,0,0), XO_MASK, PPC, 0, {RT, RA, RB}}, RB 5546 arch/powerpc/xmon/ppc-opc.c {"divwu.", XO(31,459,0,1), XO_MASK, PPC, 0, {RT, RA, RB}}, RB 5551 arch/powerpc/xmon/ppc-opc.c {"slbieg", X(31,466), XRA_MASK, POWER9, 0, {RS, RB}}, RB 5719 arch/powerpc/xmon/ppc-opc.c {"dcbi", X(31,470), XRT_MASK, PPC, 0, {RA0, RB}}, RB 5721 arch/powerpc/xmon/ppc-opc.c {"nand", XRC(31,476,0), X_MASK, COM, 0, {RA, RS, RB}}, RB 5722 arch/powerpc/xmon/ppc-opc.c {"nand.", XRC(31,476,1), X_MASK, COM, 0, {RA, RS, RB}}, RB 5724 arch/powerpc/xmon/ppc-opc.c {"dsn", X(31,483), XRT_MASK, E500MC, 0, {RA, RB}}, RB 5726 arch/powerpc/xmon/ppc-opc.c {"dcread", X(31,486), X_MASK, PPC403|PPC440, PPCA2|PPC476, {RT, RA0, RB}}, RB 5728 arch/powerpc/xmon/ppc-opc.c {"icbtls", X(31,486), X_MASK, PPCCHLK|PPC476|TITAN, 0, {CT, RA0, RB}}, RB 5730 arch/powerpc/xmon/ppc-opc.c {"stvxl", X(31,487), X_MASK, PPCVEC, 0, {VS, RA0, RB}}, RB 5735 arch/powerpc/xmon/ppc-opc.c {"divd", XO(31,489,0,0), XO_MASK, PPC64, 0, {RT, RA, RB}}, RB 5736 arch/powerpc/xmon/ppc-opc.c {"divd.", XO(31,489,0,1), XO_MASK, PPC64, 0, {RT, RA, RB}}, RB 5738 arch/powerpc/xmon/ppc-opc.c {"divw", XO(31,491,0,0), XO_MASK, PPC, 0, {RT, RA, RB}}, RB 5739 arch/powerpc/xmon/ppc-opc.c {"divw.", XO(31,491,0,1), XO_MASK, PPC, 0, {RT, RA, RB}}, RB 5741 arch/powerpc/xmon/ppc-opc.c {"icbtlse", X(31,494), X_MASK, PPCCHLK, E500MC, {CT, RA, RB}}, RB 5750 arch/powerpc/xmon/ppc-opc.c {"cmpb", X(31,508), X_MASK, POWER6|PPCA2|PPC476, 0, {RA, RS, RB}}, RB 5754 arch/powerpc/xmon/ppc-opc.c {"lbdcbx", X(31,514), X_MASK, E200Z4, 0, {RT, RA, RB}}, RB 5755 arch/powerpc/xmon/ppc-opc.c {"lbdx", X(31,515), X_MASK, E500MC, 0, {RT, RA, RB}}, RB 5759 arch/powerpc/xmon/ppc-opc.c {"lvlx", X(31,519), X_MASK, CELL, 0, {VD, RA0, RB}}, RB 5760 arch/powerpc/xmon/ppc-opc.c {"lbfcmux", APU(31,519,0), APU_MASK, PPC405, 0, {FCRT, RA, RB}}, RB 5762 arch/powerpc/xmon/ppc-opc.c {"subfco", XO(31,8,1,0), XO_MASK, PPCCOM, 0, {RT, RA, RB}}, RB 5763 arch/powerpc/xmon/ppc-opc.c {"sfo", XO(31,8,1,0), XO_MASK, PWRCOM, 0, {RT, RA, RB}}, RB 5764 arch/powerpc/xmon/ppc-opc.c {"subco", XO(31,8,1,0), XO_MASK, PPCCOM, 0, {RT, RB, RA}}, RB 5765 arch/powerpc/xmon/ppc-opc.c {"subfco.", XO(31,8,1,1), XO_MASK, PPCCOM, 0, {RT, RA, RB}}, RB 5766 arch/powerpc/xmon/ppc-opc.c {"sfo.", XO(31,8,1,1), XO_MASK, PWRCOM, 0, {RT, RA, RB}}, RB 5767 arch/powerpc/xmon/ppc-opc.c {"subco.", XO(31,8,1,1), XO_MASK, PPCCOM, 0, {RT, RB, RA}}, RB 5769 arch/powerpc/xmon/ppc-opc.c {"addco", XO(31,10,1,0), XO_MASK, PPCCOM, 0, {RT, RA, RB}}, RB 5770 arch/powerpc/xmon/ppc-opc.c {"ao", XO(31,10,1,0), XO_MASK, PWRCOM, 0, {RT, RA, RB}}, RB 5771 arch/powerpc/xmon/ppc-opc.c {"addco.", XO(31,10,1,1), XO_MASK, PPCCOM, 0, {RT, RA, RB}}, RB 5772 arch/powerpc/xmon/ppc-opc.c {"ao.", XO(31,10,1,1), XO_MASK, PWRCOM, 0, {RT, RA, RB}}, RB 5774 arch/powerpc/xmon/ppc-opc.c {"lxsspx", X(31,524), XX1_MASK, PPCVSX2, 0, {XT6, RA0, RB}}, RB 5778 arch/powerpc/xmon/ppc-opc.c {"ldbrx", X(31,532), X_MASK, CELL|POWER7|PPCA2, 0, {RT, RA0, RB}}, RB 5781 arch/powerpc/xmon/ppc-opc.c {"lsx", X(31,533), X_MASK, PWRCOM, 0, {RT, RA, RB}}, RB 5783 arch/powerpc/xmon/ppc-opc.c {"lwbrx", X(31,534), X_MASK, PPCCOM, 0, {RT, RA0, RB}}, RB 5784 arch/powerpc/xmon/ppc-opc.c {"lbrx", X(31,534), X_MASK, PWRCOM, 0, {RT, RA, RB}}, RB 5786 arch/powerpc/xmon/ppc-opc.c {"lfsx", X(31,535), X_MASK, COM, PPCEFS, {FRT, RA0, RB}}, RB 5788 arch/powerpc/xmon/ppc-opc.c {"srw", XRC(31,536,0), X_MASK, PPCCOM, 0, {RA, RS, RB}}, RB 5789 arch/powerpc/xmon/ppc-opc.c {"sr", XRC(31,536,0), X_MASK, PWRCOM, 0, {RA, RS, RB}}, RB 5790 arch/powerpc/xmon/ppc-opc.c {"srw.", XRC(31,536,1), X_MASK, PPCCOM, 0, {RA, RS, RB}}, RB 5791 arch/powerpc/xmon/ppc-opc.c {"sr.", XRC(31,536,1), X_MASK, PWRCOM, 0, {RA, RS, RB}}, RB 5793 arch/powerpc/xmon/ppc-opc.c {"rrib", XRC(31,537,0), X_MASK, M601, 0, {RA, RS, RB}}, RB 5794 arch/powerpc/xmon/ppc-opc.c {"rrib.", XRC(31,537,1), X_MASK, M601, 0, {RA, RS, RB}}, RB 5799 arch/powerpc/xmon/ppc-opc.c {"srd", XRC(31,539,0), X_MASK, PPC64, 0, {RA, RS, RB}}, RB 5800 arch/powerpc/xmon/ppc-opc.c {"srd.", XRC(31,539,1), X_MASK, PPC64, 0, {RA, RS, RB}}, RB 5802 arch/powerpc/xmon/ppc-opc.c {"maskir", XRC(31,541,0), X_MASK, M601, 0, {RA, RS, RB}}, RB 5803 arch/powerpc/xmon/ppc-opc.c {"maskir.", XRC(31,541,1), X_MASK, M601, 0, {RA, RS, RB}}, RB 5805 arch/powerpc/xmon/ppc-opc.c {"lhdcbx", X(31,546), X_MASK, E200Z4, 0, {RT, RA, RB}}, RB 5806 arch/powerpc/xmon/ppc-opc.c {"lhdx", X(31,547), X_MASK, E500MC, 0, {RT, RA, RB}}, RB 5808 arch/powerpc/xmon/ppc-opc.c {"lvtrx", X(31,549), X_MASK, PPCVEC2, 0, {VD, RA0, RB}}, RB 5812 arch/powerpc/xmon/ppc-opc.c {"lvrx", X(31,551), X_MASK, CELL, 0, {VD, RA0, RB}}, RB 5813 arch/powerpc/xmon/ppc-opc.c {"lhfcmux", APU(31,551,0), APU_MASK, PPC405, 0, {FCRT, RA, RB}}, RB 5815 arch/powerpc/xmon/ppc-opc.c {"subfo", XO(31,40,1,0), XO_MASK, PPC, 0, {RT, RA, RB}}, RB 5816 arch/powerpc/xmon/ppc-opc.c {"subo", XO(31,40,1,0), XO_MASK, PPC, 0, {RT, RB, RA}}, RB 5817 arch/powerpc/xmon/ppc-opc.c {"subfo.", XO(31,40,1,1), XO_MASK, PPC, 0, {RT, RA, RB}}, RB 5818 arch/powerpc/xmon/ppc-opc.c {"subo.", XO(31,40,1,1), XO_MASK, PPC, 0, {RT, RB, RA}}, RB 5822 arch/powerpc/xmon/ppc-opc.c {"lfsux", X(31,567), X_MASK, COM, PPCEFS, {FRT, RAS, RB}}, RB 5829 arch/powerpc/xmon/ppc-opc.c {"lwdcbx", X(31,578), X_MASK, E200Z4, 0, {RT, RA, RB}}, RB 5830 arch/powerpc/xmon/ppc-opc.c {"lwdx", X(31,579), X_MASK, E500MC, 0, {RT, RA, RB}}, RB 5832 arch/powerpc/xmon/ppc-opc.c {"lvtlx", X(31,581), X_MASK, PPCVEC2, 0, {VD, RA0, RB}}, RB 5836 arch/powerpc/xmon/ppc-opc.c {"lwfcmux", APU(31,583,0), APU_MASK, PPC405, 0, {FCRT, RA, RB}}, RB 5838 arch/powerpc/xmon/ppc-opc.c {"lxsdx", X(31,588), XX1_MASK, PPCVSX, 0, {XT6, RA0, RB}}, RB 5855 arch/powerpc/xmon/ppc-opc.c {"lfdx", X(31,599), X_MASK, COM, PPCEFS, {FRT, RA0, RB}}, RB 5857 arch/powerpc/xmon/ppc-opc.c {"mffgpr", XRC(31,607,0), XRA_MASK, POWER6, POWER7, {FRT, RB}}, RB 5858 arch/powerpc/xmon/ppc-opc.c {"lfdepx", X(31,607), X_MASK, E500MC|PPCA2, 0, {FRT, RA0, RB}}, RB 5860 arch/powerpc/xmon/ppc-opc.c {"lddx", X(31,611), X_MASK, E500MC, 0, {RT, RA, RB}}, RB 5862 arch/powerpc/xmon/ppc-opc.c {"lvswx", X(31,613), X_MASK, PPCVEC2, 0, {VD, RA0, RB}}, RB 5866 arch/powerpc/xmon/ppc-opc.c {"lqfcmux", APU(31,615,0), APU_MASK, PPC405, 0, {FCRT, RA, RB}}, RB 5871 arch/powerpc/xmon/ppc-opc.c {"mulo", XO(31,107,1,0), XO_MASK, M601, 0, {RT, RA, RB}}, RB 5872 arch/powerpc/xmon/ppc-opc.c {"mulo.", XO(31,107,1,1), XO_MASK, M601, 0, {RT, RA, RB}}, RB 5874 arch/powerpc/xmon/ppc-opc.c {"mfsri", X(31,627), X_MASK, M601, 0, {RT, RA, RB}}, RB 5878 arch/powerpc/xmon/ppc-opc.c {"lfdux", X(31,631), X_MASK, COM, PPCEFS, {FRT, RAS, RB}}, RB 5880 arch/powerpc/xmon/ppc-opc.c {"stbdcbx", X(31,642), X_MASK, E200Z4, 0, {RS, RA, RB}}, RB 5881 arch/powerpc/xmon/ppc-opc.c {"stbdx", X(31,643), X_MASK, E500MC, 0, {RS, RA, RB}}, RB 5883 arch/powerpc/xmon/ppc-opc.c {"stvlx", X(31,647), X_MASK, CELL, 0, {VS, RA0, RB}}, RB 5884 arch/powerpc/xmon/ppc-opc.c {"stbfcmux", APU(31,647,0), APU_MASK, PPC405, 0, {FCRT, RA, RB}}, RB 5886 arch/powerpc/xmon/ppc-opc.c {"stxsspx", X(31,652), XX1_MASK, PPCVSX2, 0, {XS6, RA0, RB}}, RB 5890 arch/powerpc/xmon/ppc-opc.c {"subfeo", XO(31,136,1,0), XO_MASK, PPCCOM, 0, {RT, RA, RB}}, RB 5891 arch/powerpc/xmon/ppc-opc.c {"sfeo", XO(31,136,1,0), XO_MASK, PWRCOM, 0, {RT, RA, RB}}, RB 5892 arch/powerpc/xmon/ppc-opc.c {"subfeo.", XO(31,136,1,1), XO_MASK, PPCCOM, 0, {RT, RA, RB}}, RB 5893 arch/powerpc/xmon/ppc-opc.c {"sfeo.", XO(31,136,1,1), XO_MASK, PWRCOM, 0, {RT, RA, RB}}, RB 5895 arch/powerpc/xmon/ppc-opc.c {"addeo", XO(31,138,1,0), XO_MASK, PPCCOM, 0, {RT, RA, RB}}, RB 5896 arch/powerpc/xmon/ppc-opc.c {"aeo", XO(31,138,1,0), XO_MASK, PWRCOM, 0, {RT, RA, RB}}, RB 5897 arch/powerpc/xmon/ppc-opc.c {"addeo.", XO(31,138,1,1), XO_MASK, PPCCOM, 0, {RT, RA, RB}}, RB 5898 arch/powerpc/xmon/ppc-opc.c {"aeo.", XO(31,138,1,1), XO_MASK, PWRCOM, 0, {RT, RA, RB}}, RB 5900 arch/powerpc/xmon/ppc-opc.c {"mfsrin", X(31,659), XRA_MASK, PPC, NON32, {RT, RB}}, RB 5902 arch/powerpc/xmon/ppc-opc.c {"stdbrx", X(31,660), X_MASK, CELL|POWER7|PPCA2, 0, {RS, RA0, RB}}, RB 5904 arch/powerpc/xmon/ppc-opc.c {"stswx", X(31,661), X_MASK, PPCCOM, E500|E500MC, {RS, RA0, RB}}, RB 5905 arch/powerpc/xmon/ppc-opc.c {"stsx", X(31,661), X_MASK, PWRCOM, 0, {RS, RA0, RB}}, RB 5907 arch/powerpc/xmon/ppc-opc.c {"stwbrx", X(31,662), X_MASK, PPCCOM, 0, {RS, RA0, RB}}, RB 5908 arch/powerpc/xmon/ppc-opc.c {"stbrx", X(31,662), X_MASK, PWRCOM, 0, {RS, RA0, RB}}, RB 5910 arch/powerpc/xmon/ppc-opc.c {"stfsx", X(31,663), X_MASK, COM, PPCEFS, {FRS, RA0, RB}}, RB 5912 arch/powerpc/xmon/ppc-opc.c {"srq", XRC(31,664,0), X_MASK, M601, 0, {RA, RS, RB}}, RB 5913 arch/powerpc/xmon/ppc-opc.c {"srq.", XRC(31,664,1), X_MASK, M601, 0, {RA, RS, RB}}, RB 5915 arch/powerpc/xmon/ppc-opc.c {"sre", XRC(31,665,0), X_MASK, M601, 0, {RA, RS, RB}}, RB 5916 arch/powerpc/xmon/ppc-opc.c {"sre.", XRC(31,665,1), X_MASK, M601, 0, {RA, RS, RB}}, RB 5918 arch/powerpc/xmon/ppc-opc.c {"sthdcbx", X(31,674), X_MASK, E200Z4, 0, {RS, RA, RB}}, RB 5919 arch/powerpc/xmon/ppc-opc.c {"sthdx", X(31,675), X_MASK, E500MC, 0, {RS, RA, RB}}, RB 5921 arch/powerpc/xmon/ppc-opc.c {"stvfrx", X(31,677), X_MASK, PPCVEC2, 0, {VS, RA0, RB}}, RB 5923 arch/powerpc/xmon/ppc-opc.c {"stvrx", X(31,679), X_MASK, CELL, 0, {VS, RA0, RB}}, RB 5924 arch/powerpc/xmon/ppc-opc.c {"sthfcmux", APU(31,679,0), APU_MASK, PPC405, 0, {FCRT, RA, RB}}, RB 5929 arch/powerpc/xmon/ppc-opc.c {"stbcx.", XRC(31,694,1), X_MASK, POWER8|E6500, 0, {RS, RA0, RB}}, RB 5931 arch/powerpc/xmon/ppc-opc.c {"stfsux", X(31,695), X_MASK, COM, PPCEFS, {FRS, RAS, RB}}, RB 5936 arch/powerpc/xmon/ppc-opc.c {"stwdcbx", X(31,706), X_MASK, E200Z4, 0, {RS, RA, RB}}, RB 5937 arch/powerpc/xmon/ppc-opc.c {"stwdx", X(31,707), X_MASK, E500MC, 0, {RS, RA, RB}}, RB 5939 arch/powerpc/xmon/ppc-opc.c {"stvflx", X(31,709), X_MASK, PPCVEC2, 0, {VS, RA0, RB}}, RB 5943 arch/powerpc/xmon/ppc-opc.c {"stwfcmux", APU(31,711,0), APU_MASK, PPC405, 0, {FCRT, RA, RB}}, RB 5945 arch/powerpc/xmon/ppc-opc.c {"stxsdx", X(31,716), XX1_MASK, PPCVSX, 0, {XS6, RA0, RB}}, RB 5962 arch/powerpc/xmon/ppc-opc.c {"sthcx.", XRC(31,726,1), X_MASK, POWER8|E6500, 0, {RS, RA0, RB}}, RB 5964 arch/powerpc/xmon/ppc-opc.c {"stfdx", X(31,727), X_MASK, COM, PPCEFS, {FRS, RA0, RB}}, RB 5966 arch/powerpc/xmon/ppc-opc.c {"srlq", XRC(31,728,0), X_MASK, M601, 0, {RA, RS, RB}}, RB 5967 arch/powerpc/xmon/ppc-opc.c {"srlq.", XRC(31,728,1), X_MASK, M601, 0, {RA, RS, RB}}, RB 5969 arch/powerpc/xmon/ppc-opc.c {"sreq", XRC(31,729,0), X_MASK, M601, 0, {RA, RS, RB}}, RB 5970 arch/powerpc/xmon/ppc-opc.c {"sreq.", XRC(31,729,1), X_MASK, M601, 0, {RA, RS, RB}}, RB 5973 arch/powerpc/xmon/ppc-opc.c {"stfdepx", X(31,735), X_MASK, E500MC|PPCA2, 0, {FRS, RA0, RB}}, RB 5975 arch/powerpc/xmon/ppc-opc.c {"stddx", X(31,739), X_MASK, E500MC, 0, {RS, RA, RB}}, RB 5977 arch/powerpc/xmon/ppc-opc.c {"stvswx", X(31,741), X_MASK, PPCVEC2, 0, {VS, RA0, RB}}, RB 5981 arch/powerpc/xmon/ppc-opc.c {"stqfcmux", APU(31,743,0), APU_MASK, PPC405, 0, {FCRT, RA, RB}}, RB 5988 arch/powerpc/xmon/ppc-opc.c {"mulldo", XO(31,233,1,0), XO_MASK, PPC64, 0, {RT, RA, RB}}, RB 5989 arch/powerpc/xmon/ppc-opc.c {"mulldo.", XO(31,233,1,1), XO_MASK, PPC64, 0, {RT, RA, RB}}, RB 5996 arch/powerpc/xmon/ppc-opc.c {"mullwo", XO(31,235,1,0), XO_MASK, PPCCOM, 0, {RT, RA, RB}}, RB 5997 arch/powerpc/xmon/ppc-opc.c {"mulso", XO(31,235,1,0), XO_MASK, PWRCOM, 0, {RT, RA, RB}}, RB 5998 arch/powerpc/xmon/ppc-opc.c {"mullwo.", XO(31,235,1,1), XO_MASK, PPCCOM, 0, {RT, RA, RB}}, RB 5999 arch/powerpc/xmon/ppc-opc.c {"mulso.", XO(31,235,1,1), XO_MASK, PWRCOM, 0, {RT, RA, RB}}, RB 6007 arch/powerpc/xmon/ppc-opc.c {"dcba", X(31,758), XRT_MASK, PPC405|PPC7450|BOOKE|PPCA2|PPC476, 0, {RA0, RB}}, RB 6008 arch/powerpc/xmon/ppc-opc.c {"dcbal", XOPL(31,758,1), XRT_MASK, E500MC, 0, {RA0, RB}}, RB 6010 arch/powerpc/xmon/ppc-opc.c {"stfdux", X(31,759), X_MASK, COM, PPCEFS, {FRS, RAS, RB}}, RB 6015 arch/powerpc/xmon/ppc-opc.c {"lvsm", X(31,773), X_MASK, PPCVEC2, 0, {VD, RA0, RB}}, RB 6017 arch/powerpc/xmon/ppc-opc.c {"copy", XOPL(31,774,1), XRT_MASK, POWER9, 0, {RA0, RB}}, RB 6019 arch/powerpc/xmon/ppc-opc.c {"stvepxl", X(31,775), X_MASK, PPCVEC2, 0, {VS, RA0, RB}}, RB 6020 arch/powerpc/xmon/ppc-opc.c {"lvlxl", X(31,775), X_MASK, CELL, 0, {VD, RA0, RB}}, RB 6021 arch/powerpc/xmon/ppc-opc.c {"ldfcmux", APU(31,775,0), APU_MASK, PPC405, 0, {FCRT, RA, RB}}, RB 6023 arch/powerpc/xmon/ppc-opc.c {"dozo", XO(31,264,1,0), XO_MASK, M601, 0, {RT, RA, RB}}, RB 6024 arch/powerpc/xmon/ppc-opc.c {"dozo.", XO(31,264,1,1), XO_MASK, M601, 0, {RT, RA, RB}}, RB 6026 arch/powerpc/xmon/ppc-opc.c {"addo", XO(31,266,1,0), XO_MASK, PPCCOM, 0, {RT, RA, RB}}, RB 6027 arch/powerpc/xmon/ppc-opc.c {"caxo", XO(31,266,1,0), XO_MASK, PWRCOM, 0, {RT, RA, RB}}, RB 6028 arch/powerpc/xmon/ppc-opc.c {"addo.", XO(31,266,1,1), XO_MASK, PPCCOM, 0, {RT, RA, RB}}, RB 6029 arch/powerpc/xmon/ppc-opc.c {"caxo.", XO(31,266,1,1), XO_MASK, PWRCOM, 0, {RT, RA, RB}}, RB 6031 arch/powerpc/xmon/ppc-opc.c {"modsd", X(31,777), X_MASK, POWER9, 0, {RT, RA, RB}}, RB 6032 arch/powerpc/xmon/ppc-opc.c {"modsw", X(31,779), X_MASK, POWER9, 0, {RT, RA, RB}}, RB 6034 arch/powerpc/xmon/ppc-opc.c {"lxvw4x", X(31,780), XX1_MASK, PPCVSX, 0, {XT6, RA0, RB}}, RB 6035 arch/powerpc/xmon/ppc-opc.c {"lxsibzx", X(31,781), XX1_MASK, PPCVSX3, 0, {XT6, RA0, RB}}, RB 6037 arch/powerpc/xmon/ppc-opc.c {"tabortwc.", XRC(31,782,1), X_MASK, PPCHTM, 0, {TO, RA, RB}}, RB 6039 arch/powerpc/xmon/ppc-opc.c {"tlbivax", X(31,786), XRT_MASK, BOOKE|PPCA2|PPC476, 0, {RA0, RB}}, RB 6041 arch/powerpc/xmon/ppc-opc.c {"lwzcix", X(31,789), X_MASK, POWER6, 0, {RT, RA0, RB}}, RB 6043 arch/powerpc/xmon/ppc-opc.c {"lhbrx", X(31,790), X_MASK, COM, 0, {RT, RA0, RB}}, RB 6045 arch/powerpc/xmon/ppc-opc.c {"lfdpx", X(31,791), X_MASK, POWER6, POWER7, {FRTp, RA0, RB}}, RB 6046 arch/powerpc/xmon/ppc-opc.c {"lfqx", X(31,791), X_MASK, POWER2, 0, {FRT, RA, RB}}, RB 6048 arch/powerpc/xmon/ppc-opc.c {"sraw", XRC(31,792,0), X_MASK, PPCCOM, 0, {RA, RS, RB}}, RB 6049 arch/powerpc/xmon/ppc-opc.c {"sra", XRC(31,792,0), X_MASK, PWRCOM, 0, {RA, RS, RB}}, RB 6050 arch/powerpc/xmon/ppc-opc.c {"sraw.", XRC(31,792,1), X_MASK, PPCCOM, 0, {RA, RS, RB}}, RB 6051 arch/powerpc/xmon/ppc-opc.c {"sra.", XRC(31,792,1), X_MASK, PWRCOM, 0, {RA, RS, RB}}, RB 6053 arch/powerpc/xmon/ppc-opc.c {"srad", XRC(31,794,0), X_MASK, PPC64, 0, {RA, RS, RB}}, RB 6054 arch/powerpc/xmon/ppc-opc.c {"srad.", XRC(31,794,1), X_MASK, PPC64, 0, {RA, RS, RB}}, RB 6056 arch/powerpc/xmon/ppc-opc.c {"lfddx", X(31,803), X_MASK, E500MC, 0, {FRT, RA, RB}}, RB 6058 arch/powerpc/xmon/ppc-opc.c {"lvtrxl", X(31,805), X_MASK, PPCVEC2, 0, {VD, RA0, RB}}, RB 6059 arch/powerpc/xmon/ppc-opc.c {"stvepx", X(31,807), X_MASK, PPCVEC2, 0, {VS, RA0, RB}}, RB 6060 arch/powerpc/xmon/ppc-opc.c {"lvrxl", X(31,807), X_MASK, CELL, 0, {VD, RA0, RB}}, RB 6062 arch/powerpc/xmon/ppc-opc.c {"lxvh8x", X(31,812), XX1_MASK, PPCVSX3, 0, {XT6, RA0, RB}}, RB 6063 arch/powerpc/xmon/ppc-opc.c {"lxsihzx", X(31,813), XX1_MASK, PPCVSX3, 0, {XT6, RA0, RB}}, RB 6065 arch/powerpc/xmon/ppc-opc.c {"tabortdc.", XRC(31,814,1), X_MASK, PPCHTM, 0, {TO, RA, RB}}, RB 6067 arch/powerpc/xmon/ppc-opc.c {"rac", X(31,818), X_MASK, M601, 0, {RT, RA, RB}}, RB 6069 arch/powerpc/xmon/ppc-opc.c {"erativax", X(31,819), X_MASK, PPCA2, 0, {RS, RA0, RB}}, RB 6071 arch/powerpc/xmon/ppc-opc.c {"lhzcix", X(31,821), X_MASK, POWER6, 0, {RT, RA0, RB}}, RB 6075 arch/powerpc/xmon/ppc-opc.c {"lfqux", X(31,823), X_MASK, POWER2, 0, {FRT, RA, RB}}, RB 6085 arch/powerpc/xmon/ppc-opc.c {"lvtlxl", X(31,837), X_MASK, PPCVEC2, 0, {VD, RA0, RB}}, RB 6089 arch/powerpc/xmon/ppc-opc.c {"divo", XO(31,331,1,0), XO_MASK, M601, 0, {RT, RA, RB}}, RB 6090 arch/powerpc/xmon/ppc-opc.c {"divo.", XO(31,331,1,1), XO_MASK, M601, 0, {RT, RA, RB}}, RB 6092 arch/powerpc/xmon/ppc-opc.c {"lxvd2x", X(31,844), XX1_MASK, PPCVSX, 0, {XT6, RA0, RB}}, RB 6093 arch/powerpc/xmon/ppc-opc.c {"lxvx", X(31,844), XX1_MASK, POWER8, POWER9|PPCVSX3, {XT6, RA0, RB}}, RB 6097 arch/powerpc/xmon/ppc-opc.c {"tlbsrx.", XRC(31,850,1), XRT_MASK, PPCA2, 0, {RA0, RB}}, RB 6100 arch/powerpc/xmon/ppc-opc.c {"slbmfev", X(31,851), XRLA_MASK, POWER9, 0, {RT, RB, A_L}}, RB 6101 arch/powerpc/xmon/ppc-opc.c {"slbmfev", X(31,851), XRA_MASK, PPC64, POWER9, {RT, RB}}, RB 6103 arch/powerpc/xmon/ppc-opc.c {"lbzcix", X(31,853), X_MASK, POWER6, 0, {RT, RA0, RB}}, RB 6110 arch/powerpc/xmon/ppc-opc.c {"lfiwax", X(31,855), X_MASK, POWER6|PPCA2|PPC476, 0, {FRT, RA0, RB}}, RB 6112 arch/powerpc/xmon/ppc-opc.c {"lvswxl", X(31,869), X_MASK, PPCVEC2, 0, {VD, RA0, RB}}, RB 6117 arch/powerpc/xmon/ppc-opc.c {"divso", XO(31,363,1,0), XO_MASK, M601, 0, {RT, RA, RB}}, RB 6118 arch/powerpc/xmon/ppc-opc.c {"divso.", XO(31,363,1,1), XO_MASK, M601, 0, {RT, RA, RB}}, RB 6120 arch/powerpc/xmon/ppc-opc.c {"lxvb16x", X(31,876), XX1_MASK, PPCVSX3, 0, {XT6, RA0, RB}}, RB 6124 arch/powerpc/xmon/ppc-opc.c {"rmieg", X(31,882), XRTRA_MASK, POWER9, 0, {RB}}, RB 6126 arch/powerpc/xmon/ppc-opc.c {"ldcix", X(31,885), X_MASK, POWER6, 0, {RT, RA0, RB}}, RB 6130 arch/powerpc/xmon/ppc-opc.c {"lfiwzx", X(31,887), X_MASK, POWER7|PPCA2, 0, {FRT, RA0, RB}}, RB 6135 arch/powerpc/xmon/ppc-opc.c {"paste.", XRCL(31,902,1,1),XRT_MASK, POWER9, 0, {RA0, RB}}, RB 6137 arch/powerpc/xmon/ppc-opc.c {"stvlxl", X(31,903), X_MASK, CELL, 0, {VS, RA0, RB}}, RB 6138 arch/powerpc/xmon/ppc-opc.c {"stdfcmux", APU(31,903,0), APU_MASK, PPC405, 0, {FCRT, RA, RB}}, RB 6140 arch/powerpc/xmon/ppc-opc.c {"divdeuo", XO(31,393,1,0), XO_MASK, POWER7|PPCA2, 0, {RT, RA, RB}}, RB 6141 arch/powerpc/xmon/ppc-opc.c {"divdeuo.", XO(31,393,1,1), XO_MASK, POWER7|PPCA2, 0, {RT, RA, RB}}, RB 6142 arch/powerpc/xmon/ppc-opc.c {"divweuo", XO(31,395,1,0), XO_MASK, POWER7|PPCA2, 0, {RT, RA, RB}}, RB 6143 arch/powerpc/xmon/ppc-opc.c {"divweuo.", XO(31,395,1,1), XO_MASK, POWER7|PPCA2, 0, {RT, RA, RB}}, RB 6145 arch/powerpc/xmon/ppc-opc.c {"stxvw4x", X(31,908), XX1_MASK, PPCVSX, 0, {XS6, RA0, RB}}, RB 6146 arch/powerpc/xmon/ppc-opc.c {"stxsibx", X(31,909), XX1_MASK, PPCVSX3, 0, {XS6, RA0, RB}}, RB 6150 arch/powerpc/xmon/ppc-opc.c {"tlbsx", XRC(31,914,0), X_MASK, PPC403|BOOKE|PPCA2|PPC476, 0, {RTO, RA0, RB}}, RB 6151 arch/powerpc/xmon/ppc-opc.c {"tlbsx.", XRC(31,914,1), X_MASK, PPC403|BOOKE|PPCA2|PPC476, 0, {RTO, RA0, RB}}, RB 6153 arch/powerpc/xmon/ppc-opc.c {"slbmfee", X(31,915), XRLA_MASK, POWER9, 0, {RT, RB, A_L}}, RB 6154 arch/powerpc/xmon/ppc-opc.c {"slbmfee", X(31,915), XRA_MASK, PPC64, POWER9, {RT, RB}}, RB 6156 arch/powerpc/xmon/ppc-opc.c {"stwcix", X(31,917), X_MASK, POWER6, 0, {RS, RA0, RB}}, RB 6158 arch/powerpc/xmon/ppc-opc.c {"sthbrx", X(31,918), X_MASK, COM, 0, {RS, RA0, RB}}, RB 6160 arch/powerpc/xmon/ppc-opc.c {"stfdpx", X(31,919), X_MASK, POWER6, POWER7, {FRSp, RA0, RB}}, RB 6161 arch/powerpc/xmon/ppc-opc.c {"stfqx", X(31,919), X_MASK, POWER2, 0, {FRS, RA0, RB}}, RB 6163 arch/powerpc/xmon/ppc-opc.c {"sraq", XRC(31,920,0), X_MASK, M601, 0, {RA, RS, RB}}, RB 6164 arch/powerpc/xmon/ppc-opc.c {"sraq.", XRC(31,920,1), X_MASK, M601, 0, {RA, RS, RB}}, RB 6166 arch/powerpc/xmon/ppc-opc.c {"srea", XRC(31,921,0), X_MASK, M601, 0, {RA, RS, RB}}, RB 6167 arch/powerpc/xmon/ppc-opc.c {"srea.", XRC(31,921,1), X_MASK, M601, 0, {RA, RS, RB}}, RB 6174 arch/powerpc/xmon/ppc-opc.c {"stfddx", X(31,931), X_MASK, E500MC, 0, {FRS, RA, RB}}, RB 6176 arch/powerpc/xmon/ppc-opc.c {"stvfrxl", X(31,933), X_MASK, PPCVEC2, 0, {VS, RA0, RB}}, RB 6178 arch/powerpc/xmon/ppc-opc.c {"wclrone", XOPL2(31,934,2),XRT_MASK, PPCA2, 0, {RA0, RB}}, RB 6180 arch/powerpc/xmon/ppc-opc.c {"wclr", X(31,934), X_MASK, PPCA2, 0, {L2, RA0, RB}}, RB 6182 arch/powerpc/xmon/ppc-opc.c {"stvrxl", X(31,935), X_MASK, CELL, 0, {VS, RA0, RB}}, RB 6184 arch/powerpc/xmon/ppc-opc.c {"divdeo", XO(31,425,1,0), XO_MASK, POWER7|PPCA2, 0, {RT, RA, RB}}, RB 6185 arch/powerpc/xmon/ppc-opc.c {"divdeo.", XO(31,425,1,1), XO_MASK, POWER7|PPCA2, 0, {RT, RA, RB}}, RB 6186 arch/powerpc/xmon/ppc-opc.c {"divweo", XO(31,427,1,0), XO_MASK, POWER7|PPCA2, 0, {RT, RA, RB}}, RB 6187 arch/powerpc/xmon/ppc-opc.c {"divweo.", XO(31,427,1,1), XO_MASK, POWER7|PPCA2, 0, {RT, RA, RB}}, RB 6189 arch/powerpc/xmon/ppc-opc.c {"stxvh8x", X(31,940), XX1_MASK, PPCVSX3, 0, {XS6, RA0, RB}}, RB 6190 arch/powerpc/xmon/ppc-opc.c {"stxsihx", X(31,941), XX1_MASK, PPCVSX3, 0, {XS6, RA0, RB}}, RB 6198 arch/powerpc/xmon/ppc-opc.c {"sthcix", X(31,949), X_MASK, POWER6, 0, {RS, RA0, RB}}, RB 6200 arch/powerpc/xmon/ppc-opc.c {"icswepx", XRC(31,950,0), X_MASK, PPCA2, 0, {RS, RA, RB}}, RB 6201 arch/powerpc/xmon/ppc-opc.c {"icswepx.", XRC(31,950,1), X_MASK, PPCA2, 0, {RS, RA, RB}}, RB 6203 arch/powerpc/xmon/ppc-opc.c {"stfqux", X(31,951), X_MASK, POWER2, 0, {FRS, RA, RB}}, RB 6211 arch/powerpc/xmon/ppc-opc.c {"stvflxl", X(31,965), X_MASK, PPCVEC2, 0, {VS, RA0, RB}}, RB 6216 arch/powerpc/xmon/ppc-opc.c {"divduo", XO(31,457,1,0), XO_MASK, PPC64, 0, {RT, RA, RB}}, RB 6217 arch/powerpc/xmon/ppc-opc.c {"divduo.", XO(31,457,1,1), XO_MASK, PPC64, 0, {RT, RA, RB}}, RB 6219 arch/powerpc/xmon/ppc-opc.c {"divwuo", XO(31,459,1,0), XO_MASK, PPC, 0, {RT, RA, RB}}, RB 6220 arch/powerpc/xmon/ppc-opc.c {"divwuo.", XO(31,459,1,1), XO_MASK, PPC, 0, {RT, RA, RB}}, RB 6222 arch/powerpc/xmon/ppc-opc.c {"stxvd2x", X(31,972), XX1_MASK, PPCVSX, 0, {XS6, RA0, RB}}, RB 6223 arch/powerpc/xmon/ppc-opc.c {"stxvx", X(31,972), XX1_MASK, POWER8, POWER9|PPCVSX3, {XS6, RA0, RB}}, RB 6225 arch/powerpc/xmon/ppc-opc.c {"tlbld", X(31,978), XRTRA_MASK, PPC, PPC403|BOOKE|PPCA2|PPC476, {RB}}, RB 6230 arch/powerpc/xmon/ppc-opc.c {"slbfee.", XRC(31,979,1), XRA_MASK, POWER6, 0, {RT, RB}}, RB 6232 arch/powerpc/xmon/ppc-opc.c {"stbcix", X(31,981), X_MASK, POWER6, 0, {RS, RA0, RB}}, RB 6234 arch/powerpc/xmon/ppc-opc.c {"icbi", X(31,982), XRT_MASK, PPC, 0, {RA0, RB}}, RB 6236 arch/powerpc/xmon/ppc-opc.c {"stfiwx", X(31,983), X_MASK, PPC, PPCEFS, {FRS, RA0, RB}}, RB 6241 arch/powerpc/xmon/ppc-opc.c {"icbiep", XRT(31,991,0), XRT_MASK, E500MC|PPCA2, 0, {RA0, RB}}, RB 6243 arch/powerpc/xmon/ppc-opc.c {"stvswxl", X(31,997), X_MASK, PPCVEC2, 0, {VS, RA0, RB}}, RB 6245 arch/powerpc/xmon/ppc-opc.c {"icread", X(31,998), XRT_MASK, PPC403|PPC440|PPC476|TITAN, 0, {RA0, RB}}, RB 6250 arch/powerpc/xmon/ppc-opc.c {"divdo", XO(31,489,1,0), XO_MASK, PPC64, 0, {RT, RA, RB}}, RB 6251 arch/powerpc/xmon/ppc-opc.c {"divdo.", XO(31,489,1,1), XO_MASK, PPC64, 0, {RT, RA, RB}}, RB 6253 arch/powerpc/xmon/ppc-opc.c {"divwo", XO(31,491,1,0), XO_MASK, PPC, 0, {RT, RA, RB}}, RB 6254 arch/powerpc/xmon/ppc-opc.c {"divwo.", XO(31,491,1,1), XO_MASK, PPC, 0, {RT, RA, RB}}, RB 6256 arch/powerpc/xmon/ppc-opc.c {"stxvb16x", X(31,1004), XX1_MASK, PPCVSX3, 0, {XS6, RA0, RB}}, RB 6260 arch/powerpc/xmon/ppc-opc.c {"tlbli", X(31,1010), XRTRA_MASK, PPC, TITAN, {RB}}, RB 6262 arch/powerpc/xmon/ppc-opc.c {"stdcix", X(31,1013), X_MASK, POWER6, 0, {RS, RA0, RB}}, RB 6264 arch/powerpc/xmon/ppc-opc.c {"dcbz", X(31,1014), XRT_MASK, PPC, 0, {RA0, RB}}, RB 6265 arch/powerpc/xmon/ppc-opc.c {"dclz", X(31,1014), XRT_MASK, PPC, 0, {RA0, RB}}, RB 6267 arch/powerpc/xmon/ppc-opc.c {"dcbzep", XRT(31,1023,0), XRT_MASK, E500MC|PPCA2, 0, {RA0, RB}}, RB 6269 arch/powerpc/xmon/ppc-opc.c {"dcbzl", XOPL(31,1014,1), XRT_MASK, POWER4|E500MC, PPC476, {RA0, RB}}, RB 6275 arch/powerpc/xmon/ppc-opc.c {"dstt", XDSS(31,342,1), XDSS_MASK, PPCVEC, 0, {RA, RB, STRM}}, RB 6276 arch/powerpc/xmon/ppc-opc.c {"dststt", XDSS(31,374,1), XDSS_MASK, PPCVEC, 0, {RA, RB, STRM}}, RB 6636 arch/powerpc/xmon/ppc-opc.c {"xsiexpdp", X(60,918), XX1_MASK, PPCVSX3, PPCVLE, {XT6, RA, RB}}, RB 7146 arch/powerpc/xmon/ppc-opc.c {"e_cmph", X(31,14), X_MASK, PPCVLE, 0, {CRD, RA, RB}}, RB 7147 arch/powerpc/xmon/ppc-opc.c {"e_cmphl", X(31,46), X_MASK, PPCVLE, 0, {CRD, RA, RB}}, RB 7160 arch/powerpc/xmon/ppc-opc.c {"e_rlw", EX(31,560), EX_MASK, PPCVLE, 0, {RA, RS, RB}}, RB 7161 arch/powerpc/xmon/ppc-opc.c {"e_rlw.", EX(31,561), EX_MASK, PPCVLE, 0, {RA, RS, RB}}, RB 94 drivers/clocksource/timer-atmel-tcb.c writel(0, tcaddr + ATMEL_TC_REG(i, RB)); RB 92 drivers/media/platform/rockchip/rga/rga-hw.c LT, RT, LB, RB, RB 95 drivers/media/platform/rockchip/rga/rga-hw.c RT, LT, RB, LB, RB 98 drivers/media/platform/rockchip/rga/rga-hw.c RB, LB, RT, LT, RB 101 drivers/media/platform/rockchip/rga/rga-hw.c LB, RB, LT, RT, RB 115 drivers/media/platform/rockchip/rga/rga-hw.c case RB: RB 1556 drivers/net/wireless/ath/carl9170/main.c BUILD_BUG_ON(RB > CARL9170_MAX_CMD_PAYLOAD_LEN); RB 1564 drivers/net/wireless/ath/carl9170/main.c RB, (u8 *) rng_load, RB 1565 drivers/net/wireless/ath/carl9170/main.c RB, (u8 *) buf); RB 1891 drivers/net/wireless/ath/carl9170/main.c BUILD_BUG_ON(RB > CARL9170_MAX_CMD_LEN - 4); RB 1894 drivers/net/wireless/ath/carl9170/main.c BUILD_BUG_ON(sizeof(ar->eeprom) % RB); RB 1897 drivers/net/wireless/ath/carl9170/main.c for (i = 0; i < sizeof(ar->eeprom) / RB; i++) { RB 1900 drivers/net/wireless/ath/carl9170/main.c RB * i + 4 * j); RB 1903 drivers/net/wireless/ath/carl9170/main.c RB, (u8 *) &offsets, RB 1904 drivers/net/wireless/ath/carl9170/main.c RB, eeprom + RB * i); RB 112 drivers/pwm/pwm-atmel-tcb.c __raw_readl(regs + ATMEL_TC_REG(group, RB)); RB 271 drivers/pwm/pwm-atmel-tcb.c __raw_writel(tcbpwm->duty, regs + ATMEL_TC_REG(group, RB)); RB 472 drivers/pwm/pwm-atmel-tcb.c chan->rb = readl(base + ATMEL_TC_REG(i, RB)); RB 489 drivers/pwm/pwm-atmel-tcb.c writel(chan->rb, base + ATMEL_TC_REG(i, RB)); RB 9 tools/testing/selftests/powerpc/include/instructions.h #define __COPY(RA, RB, L) \ RB 10 tools/testing/selftests/powerpc/include/instructions.h (0x7c00060c | (RA) << (31-15) | (RB) << (31-20) | (L) << (31-10)) RB 11 tools/testing/selftests/powerpc/include/instructions.h #define COPY(RA, RB, L) \ RB 12 tools/testing/selftests/powerpc/include/instructions.h .long __COPY((RA), (RB), (L)) RB 33 tools/testing/selftests/powerpc/include/instructions.h #define __PASTE(RA, RB, L, RC) \ RB 34 tools/testing/selftests/powerpc/include/instructions.h (0x7c00070c | (RA) << (31-15) | (RB) << (31-20) | (L) << (31-10) | (RC) << (31-31)) RB 35 tools/testing/selftests/powerpc/include/instructions.h #define PASTE(RA, RB, L, RC) \ RB 36 tools/testing/selftests/powerpc/include/instructions.h .long __PASTE((RA), (RB), (L), (RC))