RAM               530 arch/powerpc/xmon/ppc-opc.c #define RAS RAM + 1
RAM              6316 arch/powerpc/xmon/ppc-opc.c {"lmw",		OP(46),		OP_MASK,     PPCCOM,	PPCVLE,		{RT, D, RAM}},
RAM                72 arch/x86/events/intel/ds.c 	OP_LH | P(LVL, LOC_RAM)  | LEVEL(RAM) | P(SNOOP, HIT),       /* 0x0a: L3 miss, shared */
RAM                74 arch/x86/events/intel/ds.c 	OP_LH | P(LVL, LOC_RAM)  | LEVEL(RAM) | SNOOP_NONE_MISS,     /* 0x0c: L3 miss, excl */
RAM                75 arch/x86/events/intel/ds.c 	OP_LH | P(LVL, REM_RAM1) | LEVEL(RAM) | REM | SNOOP_NONE_MISS, /* 0x0d: L3 miss, excl */
RAM                94 arch/x86/events/intel/ds.c 	pebs_data_source[0x0b] = OP_LH | LEVEL(RAM) | REM | P(SNOOP, NONE);
RAM              1789 drivers/atm/firestream.c 		write_fs (dev, RAM, (1 << (28 - FS155_VPI_BITS - FS155_VCI_BITS)) - 1);
RAM                58 drivers/iommu/omap-iommu-debug.c 	pr_reg(RAM);