RADEON_PPLL_REF_DIV  121 drivers/gpu/drm/radeon/radeon_clocks.c 	p1pll->reference_div = RREG32_PLL(RADEON_PPLL_REF_DIV) & 0x3ff;
RADEON_PPLL_REF_DIV  199 drivers/gpu/drm/radeon/radeon_clocks.c 				u32 tmp = RREG32_PLL(RADEON_PPLL_REF_DIV);
RADEON_PPLL_REF_DIV  241 drivers/gpu/drm/radeon/radeon_clocks.c 			    RREG32_PLL(RADEON_PPLL_REF_DIV) & 0x3ff;
RADEON_PPLL_REF_DIV 1155 drivers/gpu/drm/radeon/radeon_combios.c 		    RREG32_PLL(RADEON_PPLL_REF_DIV) & 0x3ff;
RADEON_PPLL_REF_DIV  224 drivers/gpu/drm/radeon/radeon_legacy_crtc.c 	      RREG32_PLL(RADEON_PPLL_REF_DIV) & RADEON_PPLL_ATOMIC_UPDATE_R);
RADEON_PPLL_REF_DIV  232 drivers/gpu/drm/radeon/radeon_legacy_crtc.c 	while (RREG32_PLL(RADEON_PPLL_REF_DIV) & RADEON_PPLL_ATOMIC_UPDATE_R);
RADEON_PPLL_REF_DIV  234 drivers/gpu/drm/radeon/radeon_legacy_crtc.c 	WREG32_PLL_P(RADEON_PPLL_REF_DIV,
RADEON_PPLL_REF_DIV  934 drivers/gpu/drm/radeon/radeon_legacy_crtc.c 			if ((pll_ref_div == (RREG32_PLL(RADEON_PPLL_REF_DIV) & RADEON_PPLL_REF_DIV_MASK)) &&
RADEON_PPLL_REF_DIV  971 drivers/gpu/drm/radeon/radeon_legacy_crtc.c 				WREG32_PLL_P(RADEON_PPLL_REF_DIV,
RADEON_PPLL_REF_DIV  976 drivers/gpu/drm/radeon/radeon_legacy_crtc.c 				WREG32_PLL_P(RADEON_PPLL_REF_DIV,
RADEON_PPLL_REF_DIV  981 drivers/gpu/drm/radeon/radeon_legacy_crtc.c 			WREG32_PLL_P(RADEON_PPLL_REF_DIV,