RADEON_M_SPLL_REF_FB_DIV   44 drivers/gpu/drm/radeon/radeon_clocks.c 	fb_div = RREG32_PLL(RADEON_M_SPLL_REF_FB_DIV);
RADEON_M_SPLL_REF_FB_DIV   50 drivers/gpu/drm/radeon/radeon_clocks.c 	    RREG32_PLL(RADEON_M_SPLL_REF_FB_DIV) & RADEON_M_SPLL_REF_DIV_MASK;
RADEON_M_SPLL_REF_FB_DIV   74 drivers/gpu/drm/radeon/radeon_clocks.c 	fb_div = RREG32_PLL(RADEON_M_SPLL_REF_FB_DIV);
RADEON_M_SPLL_REF_FB_DIV   80 drivers/gpu/drm/radeon/radeon_clocks.c 	    RREG32_PLL(RADEON_M_SPLL_REF_FB_DIV) & RADEON_M_SPLL_REF_DIV_MASK;
RADEON_M_SPLL_REF_FB_DIV  151 drivers/gpu/drm/radeon/radeon_clocks.c 		RREG32_PLL(RADEON_M_SPLL_REF_FB_DIV) &
RADEON_M_SPLL_REF_FB_DIV  215 drivers/gpu/drm/radeon/radeon_clocks.c 					RREG32_PLL(RADEON_M_SPLL_REF_FB_DIV) &
RADEON_M_SPLL_REF_FB_DIV  267 drivers/gpu/drm/radeon/radeon_clocks.c 			    RREG32_PLL(RADEON_M_SPLL_REF_FB_DIV) &
RADEON_M_SPLL_REF_FB_DIV  359 drivers/gpu/drm/radeon/radeon_clocks.c 		    RREG32_PLL(RADEON_M_SPLL_REF_FB_DIV) &
RADEON_M_SPLL_REF_FB_DIV  421 drivers/gpu/drm/radeon/radeon_clocks.c 	tmp = RREG32_PLL(RADEON_M_SPLL_REF_FB_DIV);
RADEON_M_SPLL_REF_FB_DIV  424 drivers/gpu/drm/radeon/radeon_clocks.c 	WREG32_PLL(RADEON_M_SPLL_REF_FB_DIV, tmp);