RADEON_MAX_VCE_HANDLES 1716 drivers/gpu/drm/radeon/radeon.h atomic_t handles[RADEON_MAX_VCE_HANDLES]; RADEON_MAX_VCE_HANDLES 1717 drivers/gpu/drm/radeon/radeon.h struct drm_file *filp[RADEON_MAX_VCE_HANDLES]; RADEON_MAX_VCE_HANDLES 1718 drivers/gpu/drm/radeon/radeon.h unsigned img_size[RADEON_MAX_VCE_HANDLES]; RADEON_MAX_VCE_HANDLES 166 drivers/gpu/drm/radeon/radeon_vce.c for (i = 0; i < RADEON_MAX_VCE_HANDLES; ++i) { RADEON_MAX_VCE_HANDLES 204 drivers/gpu/drm/radeon/radeon_vce.c for (i = 0; i < RADEON_MAX_VCE_HANDLES; ++i) RADEON_MAX_VCE_HANDLES 208 drivers/gpu/drm/radeon/radeon_vce.c if (i == RADEON_MAX_VCE_HANDLES) RADEON_MAX_VCE_HANDLES 319 drivers/gpu/drm/radeon/radeon_vce.c for (i = 0; i < RADEON_MAX_VCE_HANDLES; ++i) { RADEON_MAX_VCE_HANDLES 527 drivers/gpu/drm/radeon/radeon_vce.c for (i = 0; i < RADEON_MAX_VCE_HANDLES; ++i) { RADEON_MAX_VCE_HANDLES 538 drivers/gpu/drm/radeon/radeon_vce.c for (i = 0; i < RADEON_MAX_VCE_HANDLES; ++i) { RADEON_MAX_VCE_HANDLES 679 drivers/gpu/drm/radeon/radeon_vce.c for (i = 0; i < RADEON_MAX_VCE_HANDLES; ++i) RADEON_MAX_VCE_HANDLES 36 drivers/gpu/drm/radeon/vce_v1_0.c #define VCE_V1_0_DATA_SIZE (7808 * (RADEON_MAX_VCE_HANDLES + 1)) RADEON_MAX_VCE_HANDLES 235 drivers/gpu/drm/radeon/vce_v1_0.c WREG32(VCE_VCPU_SCRATCH7, RADEON_MAX_VCE_HANDLES); RADEON_MAX_VCE_HANDLES 36 drivers/gpu/drm/radeon/vce_v2_0.c #define VCE_V2_0_DATA_SIZE (23552 * RADEON_MAX_VCE_HANDLES)