RA0 512 arch/powerpc/xmon/ppc-opc.c #define RAQ RA0 + 1 RA0 3853 arch/powerpc/xmon/ppc-opc.c {"addi", OP(14), OP_MASK, PPCCOM, PPCVLE, {RT, RA0, SI}}, RA0 3854 arch/powerpc/xmon/ppc-opc.c {"cal", OP(14), OP_MASK, PWRCOM, PPCVLE, {RT, D, RA0}}, RA0 3855 arch/powerpc/xmon/ppc-opc.c {"subi", OP(14), OP_MASK, PPCCOM, PPCVLE, {RT, RA0, NSI}}, RA0 3856 arch/powerpc/xmon/ppc-opc.c {"la", OP(14), OP_MASK, PPCCOM, PPCVLE, {RT, D, RA0}}, RA0 3860 arch/powerpc/xmon/ppc-opc.c {"addis", OP(15), OP_MASK, PPCCOM, PPCVLE, {RT, RA0, SISIGNOPT}}, RA0 3861 arch/powerpc/xmon/ppc-opc.c {"cau", OP(15), OP_MASK, PWRCOM, PPCVLE, {RT, RA0, SISIGNOPT}}, RA0 3862 arch/powerpc/xmon/ppc-opc.c {"subis", OP(15), OP_MASK, PPCCOM, PPCVLE, {RT, RA0, NSISIGNOPT}}, RA0 4695 arch/powerpc/xmon/ppc-opc.c {"lvsl", X(31,6), X_MASK, PPCVEC, 0, {VD, RA0, RB}}, RA0 4696 arch/powerpc/xmon/ppc-opc.c {"lvebx", X(31,7), X_MASK, PPCVEC, 0, {VD, RA0, RB}}, RA0 4717 arch/powerpc/xmon/ppc-opc.c {"lxsiwzx", X(31,12), XX1_MASK, PPCVSX2, 0, {XT6, RA0, RB}}, RA0 4719 arch/powerpc/xmon/ppc-opc.c {"isellt", X(31,15), X_MASK, PPCISEL, 0, {RT, RA0, RB}}, RA0 4723 arch/powerpc/xmon/ppc-opc.c {"tlbilxva", XTO(31,18,3), XTO_MASK, E500MC|PPCA2, 0, {RA0, RB}}, RA0 4724 arch/powerpc/xmon/ppc-opc.c {"tlbilx", X(31,18), X_MASK, E500MC|PPCA2, 0, {T, RA0, RB}}, RA0 4729 arch/powerpc/xmon/ppc-opc.c {"lwarx", X(31,20), XEH_MASK, PPC, 0, {RT, RA0, RB, EH}}, RA0 4731 arch/powerpc/xmon/ppc-opc.c {"ldx", X(31,21), X_MASK, PPC64, 0, {RT, RA0, RB}}, RA0 4733 arch/powerpc/xmon/ppc-opc.c {"icbt", X(31,22), X_MASK, BOOKE|PPCE300|PPCA2|PPC476, 0, {CT, RA0, RB}}, RA0 4735 arch/powerpc/xmon/ppc-opc.c {"lwzx", X(31,23), X_MASK, PPCCOM, 0, {RT, RA0, RB}}, RA0 4757 arch/powerpc/xmon/ppc-opc.c {"ldepx", X(31,29), X_MASK, E500MC|PPCA2, 0, {RT, RA0, RB}}, RA0 4762 arch/powerpc/xmon/ppc-opc.c {"lwepx", X(31,31), X_MASK, E500MC|PPCA2, 0, {RT, RA0, RB}}, RA0 4769 arch/powerpc/xmon/ppc-opc.c {"lvsr", X(31,38), X_MASK, PPCVEC, 0, {VD, RA0, RB}}, RA0 4770 arch/powerpc/xmon/ppc-opc.c {"lvehx", X(31,39), X_MASK, PPCVEC, 0, {VD, RA0, RB}}, RA0 4775 arch/powerpc/xmon/ppc-opc.c {"iselgt", X(31,47), X_MASK, PPCISEL, 0, {RT, RA0, RB}}, RA0 4777 arch/powerpc/xmon/ppc-opc.c {"lvewx", X(31,71), X_MASK, PPCVEC, 0, {VD, RA0, RB}}, RA0 4781 arch/powerpc/xmon/ppc-opc.c {"lxsiwax", X(31,76), XX1_MASK, PPCVSX2, 0, {XT6, RA0, RB}}, RA0 4783 arch/powerpc/xmon/ppc-opc.c {"iseleq", X(31,79), X_MASK, PPCISEL, 0, {RT, RA0, RB}}, RA0 4785 arch/powerpc/xmon/ppc-opc.c {"isel", XISEL(31,15), XISEL_MASK, PPCISEL|TITAN, 0, {RT, RA0, RB, CRB}}, RA0 4797 arch/powerpc/xmon/ppc-opc.c {"lbarx", X(31,52), XEH_MASK, POWER8|E6500, 0, {RT, RA0, RB, EH}}, RA0 4801 arch/powerpc/xmon/ppc-opc.c {"dcbst", X(31,54), XRT_MASK, PPC, 0, {RA0, RB}}, RA0 4816 arch/powerpc/xmon/ppc-opc.c {"dcbstep", XRT(31,63,0), XRT_MASK, E500MC|PPCA2, 0, {RA0, RB}}, RA0 4849 arch/powerpc/xmon/ppc-opc.c {"ldarx", X(31,84), XEH_MASK, PPC64, 0, {RT, RA0, RB, EH}}, RA0 4851 arch/powerpc/xmon/ppc-opc.c {"dcbfl", XOPL(31,86,1), XRT_MASK, POWER5, PPC476, {RA0, RB}}, RA0 4852 arch/powerpc/xmon/ppc-opc.c {"dcbf", X(31,86), XLRT_MASK, PPC, 0, {RA0, RB, L2OPT}}, RA0 4854 arch/powerpc/xmon/ppc-opc.c {"lbzx", X(31,87), X_MASK, COM, 0, {RT, RA0, RB}}, RA0 4856 arch/powerpc/xmon/ppc-opc.c {"lbepx", X(31,95), X_MASK, E500MC|PPCA2, 0, {RT, RA0, RB}}, RA0 4860 arch/powerpc/xmon/ppc-opc.c {"lvx", X(31,103), X_MASK, PPCVEC, 0, {VD, RA0, RB}}, RA0 4877 arch/powerpc/xmon/ppc-opc.c {"lharx", X(31,116), XEH_MASK, POWER8|E6500, 0, {RT, RA0, RB, EH}}, RA0 4890 arch/powerpc/xmon/ppc-opc.c {"dcbfep", XRT(31,127,0), XRT_MASK, E500MC|PPCA2, 0, {RA0, RB}}, RA0 4896 arch/powerpc/xmon/ppc-opc.c {"dcbtstls", X(31,134), X_MASK, PPCCHLK|PPC476|TITAN, 0, {CT, RA0, RB}}, RA0 4898 arch/powerpc/xmon/ppc-opc.c {"stvebx", X(31,135), X_MASK, PPCVEC, 0, {VS, RA0, RB}}, RA0 4911 arch/powerpc/xmon/ppc-opc.c {"stxsiwx", X(31,140), XX1_MASK, PPCVSX2, 0, {XS6, RA0, RB}}, RA0 4914 arch/powerpc/xmon/ppc-opc.c {"dcbtstlse", X(31,142), X_MASK, PPCCHLK, E500MC, {CT, RA0, RB}}, RA0 4924 arch/powerpc/xmon/ppc-opc.c {"eratsx", XRC(31,147,0), X_MASK, PPCA2, 0, {RT, RA0, RB}}, RA0 4925 arch/powerpc/xmon/ppc-opc.c {"eratsx.", XRC(31,147,1), X_MASK, PPCA2, 0, {RT, RA0, RB}}, RA0 4927 arch/powerpc/xmon/ppc-opc.c {"stdx", X(31,149), X_MASK, PPC64, 0, {RS, RA0, RB}}, RA0 4929 arch/powerpc/xmon/ppc-opc.c {"stwcx.", XRC(31,150,1), X_MASK, PPC, 0, {RS, RA0, RB}}, RA0 4931 arch/powerpc/xmon/ppc-opc.c {"stwx", X(31,151), X_MASK, PPCCOM, 0, {RS, RA0, RB}}, RA0 4942 arch/powerpc/xmon/ppc-opc.c {"stdepx", X(31,157), X_MASK, E500MC|PPCA2, 0, {RS, RA0, RB}}, RA0 4944 arch/powerpc/xmon/ppc-opc.c {"stwepx", X(31,159), X_MASK, E500MC|PPCA2, 0, {RS, RA0, RB}}, RA0 4948 arch/powerpc/xmon/ppc-opc.c {"dcbtls", X(31,166), X_MASK, PPCCHLK|PPC476|TITAN, 0, {CT, RA0, RB}}, RA0 4950 arch/powerpc/xmon/ppc-opc.c {"stvehx", X(31,167), X_MASK, PPCVEC, 0, {VS, RA0, RB}}, RA0 4956 arch/powerpc/xmon/ppc-opc.c {"dcbtlse", X(31,174), X_MASK, PPCCHLK, E500MC, {CT, RA0, RB}}, RA0 4967 arch/powerpc/xmon/ppc-opc.c {"stqcx.", XRC(31,182,1), X_MASK, POWER8, 0, {RSQ, RA0, RB}}, RA0 4971 arch/powerpc/xmon/ppc-opc.c {"stux", X(31,183), X_MASK, PWRCOM, 0, {RS, RA0, RB}}, RA0 4980 arch/powerpc/xmon/ppc-opc.c {"icblq.", XRC(31,198,1), X_MASK, E6500, 0, {CT, RA0, RB}}, RA0 4982 arch/powerpc/xmon/ppc-opc.c {"stvewx", X(31,199), X_MASK, PPCVEC, 0, {VS, RA0, RB}}, RA0 5004 arch/powerpc/xmon/ppc-opc.c {"ldawx.", XRC(31,212,1), X_MASK, PPCA2, 0, {RT, RA0, RB}}, RA0 5006 arch/powerpc/xmon/ppc-opc.c {"stdcx.", XRC(31,214,1), X_MASK, PPC64, 0, {RS, RA0, RB}}, RA0 5008 arch/powerpc/xmon/ppc-opc.c {"stbx", X(31,215), X_MASK, COM, 0, {RS, RA0, RB}}, RA0 5016 arch/powerpc/xmon/ppc-opc.c {"stbepx", X(31,223), X_MASK, E500MC|PPCA2, 0, {RS, RA0, RB}}, RA0 5020 arch/powerpc/xmon/ppc-opc.c {"icblc", X(31,230), X_MASK, PPCCHLK|PPC476|TITAN, 0, {CT, RA0, RB}}, RA0 5022 arch/powerpc/xmon/ppc-opc.c {"stvx", X(31,231), X_MASK, PPCVEC, 0, {VS, RA0, RB}}, RA0 5052 arch/powerpc/xmon/ppc-opc.c {"dcbtstt", XRT(31,246,0x10), XRT_MASK, POWER7, 0, {RA0, RB}}, RA0 5053 arch/powerpc/xmon/ppc-opc.c {"dcbtst", X(31,246), X_MASK, POWER4, DCBT_EO, {RA0, RB, CT}}, RA0 5054 arch/powerpc/xmon/ppc-opc.c {"dcbtst", X(31,246), X_MASK, DCBT_EO, 0, {CT, RA0, RB}}, RA0 5055 arch/powerpc/xmon/ppc-opc.c {"dcbtst", X(31,246), X_MASK, PPC, POWER4|DCBT_EO, {RA0, RB}}, RA0 5064 arch/powerpc/xmon/ppc-opc.c {"dcbtstep", XRT(31,255,0), X_MASK, E500MC|PPCA2, 0, {RT, RA0, RB}}, RA0 5069 arch/powerpc/xmon/ppc-opc.c {"lvexbx", X(31,261), X_MASK, PPCVEC2, 0, {VD, RA0, RB}}, RA0 5073 arch/powerpc/xmon/ppc-opc.c {"lvepxl", X(31,263), X_MASK, PPCVEC2, 0, {VD, RA0, RB}}, RA0 5088 arch/powerpc/xmon/ppc-opc.c {"lxvx", X(31,268), XX1_MASK|1<<6, PPCVSX3, 0, {XT6, RA0, RB}}, RA0 5089 arch/powerpc/xmon/ppc-opc.c {"lxvl", X(31,269), XX1_MASK, PPCVSX3, 0, {XT6, RA0, RB}}, RA0 5103 arch/powerpc/xmon/ppc-opc.c {"dcbtt", XRT(31,278,0x10), XRT_MASK, POWER7, 0, {RA0, RB}}, RA0 5104 arch/powerpc/xmon/ppc-opc.c {"dcbt", X(31,278), X_MASK, POWER4, DCBT_EO, {RA0, RB, CT}}, RA0 5105 arch/powerpc/xmon/ppc-opc.c {"dcbt", X(31,278), X_MASK, DCBT_EO, 0, {CT, RA0, RB}}, RA0 5106 arch/powerpc/xmon/ppc-opc.c {"dcbt", X(31,278), X_MASK, PPC, POWER4|DCBT_EO, {RA0, RB}}, RA0 5108 arch/powerpc/xmon/ppc-opc.c {"lhzx", X(31,279), X_MASK, COM, 0, {RT, RA0, RB}}, RA0 5115 arch/powerpc/xmon/ppc-opc.c {"lhepx", X(31,287), X_MASK, E500MC|PPCA2, 0, {RT, RA0, RB}}, RA0 5119 arch/powerpc/xmon/ppc-opc.c {"lvexhx", X(31,293), X_MASK, PPCVEC2, 0, {VD, RA0, RB}}, RA0 5120 arch/powerpc/xmon/ppc-opc.c {"lvepx", X(31,295), X_MASK, PPCVEC2, 0, {VD, RA0, RB}}, RA0 5122 arch/powerpc/xmon/ppc-opc.c {"lxvll", X(31,301), XX1_MASK, PPCVSX3, 0, {XT6, RA0, RB}}, RA0 5129 arch/powerpc/xmon/ppc-opc.c {"tlbi", X(31,306), XRT_MASK, POWER, 0, {RA0, RB}}, RA0 5133 arch/powerpc/xmon/ppc-opc.c {"ldmx", X(31,309), X_MASK, POWER9, 0, {RT, RA0, RB}}, RA0 5135 arch/powerpc/xmon/ppc-opc.c {"eciwx", X(31,310), X_MASK, PPC, E500|TITAN, {RT, RA0, RB}}, RA0 5144 arch/powerpc/xmon/ppc-opc.c {"dcbtep", XRT(31,319,0), X_MASK, E500MC|PPCA2, 0, {RT, RA0, RB}}, RA0 5183 arch/powerpc/xmon/ppc-opc.c {"lvexwx", X(31,325), X_MASK, PPCVEC2, 0, {VD, RA0, RB}}, RA0 5185 arch/powerpc/xmon/ppc-opc.c {"dcread", X(31,326), X_MASK, PPC476|TITAN, 0, {RT, RA0, RB}}, RA0 5190 arch/powerpc/xmon/ppc-opc.c {"lxvdsx", X(31,332), XX1_MASK, PPCVSX, 0, {XT6, RA0, RB}}, RA0 5399 arch/powerpc/xmon/ppc-opc.c {"lwax", X(31,341), X_MASK, PPC64, 0, {RT, RA0, RB}}, RA0 5403 arch/powerpc/xmon/ppc-opc.c {"lhax", X(31,343), X_MASK, COM, 0, {RT, RA0, RB}}, RA0 5405 arch/powerpc/xmon/ppc-opc.c {"lvxl", X(31,359), X_MASK, PPCVEC, 0, {VD, RA0, RB}}, RA0 5413 arch/powerpc/xmon/ppc-opc.c {"lxvwsx", X(31,364), XX1_MASK, PPCVSX3, 0, {XT6, RA0, RB}}, RA0 5432 arch/powerpc/xmon/ppc-opc.c {"stvexbx", X(31,389), X_MASK, PPCVEC2, 0, {VS, RA0, RB}}, RA0 5434 arch/powerpc/xmon/ppc-opc.c {"dcblc", X(31,390), X_MASK, PPCCHLK|PPC476|TITAN, 0, {CT, RA0, RB}}, RA0 5442 arch/powerpc/xmon/ppc-opc.c {"stxvx", X(31,396), XX1_MASK, PPCVSX3, 0, {XS6, RA0, RB}}, RA0 5443 arch/powerpc/xmon/ppc-opc.c {"stxvl", X(31,397), XX1_MASK, PPCVSX3, 0, {XS6, RA0, RB}}, RA0 5451 arch/powerpc/xmon/ppc-opc.c {"pbt.", XRC(31,404,1), X_MASK, POWER8, 0, {RS, RA0, RB}}, RA0 5456 arch/powerpc/xmon/ppc-opc.c {"sthx", X(31,407), X_MASK, COM, 0, {RS, RA0, RB}}, RA0 5461 arch/powerpc/xmon/ppc-opc.c {"sthepx", X(31,415), X_MASK, E500MC|PPCA2, 0, {RS, RA0, RB}}, RA0 5465 arch/powerpc/xmon/ppc-opc.c {"stvexhx", X(31,421), X_MASK, PPCVEC2, 0, {VS, RA0, RB}}, RA0 5467 arch/powerpc/xmon/ppc-opc.c {"dcblq.", XRC(31,422,1), X_MASK, E6500, 0, {CT, RA0, RB}}, RA0 5474 arch/powerpc/xmon/ppc-opc.c {"stxvll", X(31,429), XX1_MASK, PPCVSX3, 0, {XS6, RA0, RB}}, RA0 5480 arch/powerpc/xmon/ppc-opc.c {"mtvsrdd", X(31,435), XX1_MASK, PPCVSX3, 0, {XT6, RA0, RB}}, RA0 5482 arch/powerpc/xmon/ppc-opc.c {"ecowx", X(31,438), X_MASK, PPC, E500|TITAN, {RT, RA0, RB}}, RA0 5537 arch/powerpc/xmon/ppc-opc.c {"stvexwx", X(31,453), X_MASK, PPCVEC2, 0, {VS, RA0, RB}}, RA0 5719 arch/powerpc/xmon/ppc-opc.c {"dcbi", X(31,470), XRT_MASK, PPC, 0, {RA0, RB}}, RA0 5726 arch/powerpc/xmon/ppc-opc.c {"dcread", X(31,486), X_MASK, PPC403|PPC440, PPCA2|PPC476, {RT, RA0, RB}}, RA0 5728 arch/powerpc/xmon/ppc-opc.c {"icbtls", X(31,486), X_MASK, PPCCHLK|PPC476|TITAN, 0, {CT, RA0, RB}}, RA0 5730 arch/powerpc/xmon/ppc-opc.c {"stvxl", X(31,487), X_MASK, PPCVEC, 0, {VS, RA0, RB}}, RA0 5759 arch/powerpc/xmon/ppc-opc.c {"lvlx", X(31,519), X_MASK, CELL, 0, {VD, RA0, RB}}, RA0 5774 arch/powerpc/xmon/ppc-opc.c {"lxsspx", X(31,524), XX1_MASK, PPCVSX2, 0, {XT6, RA0, RB}}, RA0 5778 arch/powerpc/xmon/ppc-opc.c {"ldbrx", X(31,532), X_MASK, CELL|POWER7|PPCA2, 0, {RT, RA0, RB}}, RA0 5783 arch/powerpc/xmon/ppc-opc.c {"lwbrx", X(31,534), X_MASK, PPCCOM, 0, {RT, RA0, RB}}, RA0 5786 arch/powerpc/xmon/ppc-opc.c {"lfsx", X(31,535), X_MASK, COM, PPCEFS, {FRT, RA0, RB}}, RA0 5808 arch/powerpc/xmon/ppc-opc.c {"lvtrx", X(31,549), X_MASK, PPCVEC2, 0, {VD, RA0, RB}}, RA0 5812 arch/powerpc/xmon/ppc-opc.c {"lvrx", X(31,551), X_MASK, CELL, 0, {VD, RA0, RB}}, RA0 5832 arch/powerpc/xmon/ppc-opc.c {"lvtlx", X(31,581), X_MASK, PPCVEC2, 0, {VD, RA0, RB}}, RA0 5834 arch/powerpc/xmon/ppc-opc.c {"lwat", X(31,582), X_MASK, POWER9, 0, {RT, RA0, FC}}, RA0 5838 arch/powerpc/xmon/ppc-opc.c {"lxsdx", X(31,588), XX1_MASK, PPCVSX, 0, {XT6, RA0, RB}}, RA0 5843 arch/powerpc/xmon/ppc-opc.c {"lsi", X(31,597), X_MASK, PWRCOM, 0, {RT, RA0, NB}}, RA0 5855 arch/powerpc/xmon/ppc-opc.c {"lfdx", X(31,599), X_MASK, COM, PPCEFS, {FRT, RA0, RB}}, RA0 5858 arch/powerpc/xmon/ppc-opc.c {"lfdepx", X(31,607), X_MASK, E500MC|PPCA2, 0, {FRT, RA0, RB}}, RA0 5862 arch/powerpc/xmon/ppc-opc.c {"lvswx", X(31,613), X_MASK, PPCVEC2, 0, {VD, RA0, RB}}, RA0 5864 arch/powerpc/xmon/ppc-opc.c {"ldat", X(31,614), X_MASK, POWER9, 0, {RT, RA0, FC}}, RA0 5883 arch/powerpc/xmon/ppc-opc.c {"stvlx", X(31,647), X_MASK, CELL, 0, {VS, RA0, RB}}, RA0 5886 arch/powerpc/xmon/ppc-opc.c {"stxsspx", X(31,652), XX1_MASK, PPCVSX2, 0, {XS6, RA0, RB}}, RA0 5902 arch/powerpc/xmon/ppc-opc.c {"stdbrx", X(31,660), X_MASK, CELL|POWER7|PPCA2, 0, {RS, RA0, RB}}, RA0 5904 arch/powerpc/xmon/ppc-opc.c {"stswx", X(31,661), X_MASK, PPCCOM, E500|E500MC, {RS, RA0, RB}}, RA0 5905 arch/powerpc/xmon/ppc-opc.c {"stsx", X(31,661), X_MASK, PWRCOM, 0, {RS, RA0, RB}}, RA0 5907 arch/powerpc/xmon/ppc-opc.c {"stwbrx", X(31,662), X_MASK, PPCCOM, 0, {RS, RA0, RB}}, RA0 5908 arch/powerpc/xmon/ppc-opc.c {"stbrx", X(31,662), X_MASK, PWRCOM, 0, {RS, RA0, RB}}, RA0 5910 arch/powerpc/xmon/ppc-opc.c {"stfsx", X(31,663), X_MASK, COM, PPCEFS, {FRS, RA0, RB}}, RA0 5921 arch/powerpc/xmon/ppc-opc.c {"stvfrx", X(31,677), X_MASK, PPCVEC2, 0, {VS, RA0, RB}}, RA0 5923 arch/powerpc/xmon/ppc-opc.c {"stvrx", X(31,679), X_MASK, CELL, 0, {VS, RA0, RB}}, RA0 5929 arch/powerpc/xmon/ppc-opc.c {"stbcx.", XRC(31,694,1), X_MASK, POWER8|E6500, 0, {RS, RA0, RB}}, RA0 5939 arch/powerpc/xmon/ppc-opc.c {"stvflx", X(31,709), X_MASK, PPCVEC2, 0, {VS, RA0, RB}}, RA0 5941 arch/powerpc/xmon/ppc-opc.c {"stwat", X(31,710), X_MASK, POWER9, 0, {RS, RA0, FC}}, RA0 5945 arch/powerpc/xmon/ppc-opc.c {"stxsdx", X(31,716), XX1_MASK, PPCVSX, 0, {XS6, RA0, RB}}, RA0 5959 arch/powerpc/xmon/ppc-opc.c {"stswi", X(31,725), X_MASK, PPCCOM, E500|E500MC, {RS, RA0, NB}}, RA0 5960 arch/powerpc/xmon/ppc-opc.c {"stsi", X(31,725), X_MASK, PWRCOM, 0, {RS, RA0, NB}}, RA0 5962 arch/powerpc/xmon/ppc-opc.c {"sthcx.", XRC(31,726,1), X_MASK, POWER8|E6500, 0, {RS, RA0, RB}}, RA0 5964 arch/powerpc/xmon/ppc-opc.c {"stfdx", X(31,727), X_MASK, COM, PPCEFS, {FRS, RA0, RB}}, RA0 5973 arch/powerpc/xmon/ppc-opc.c {"stfdepx", X(31,735), X_MASK, E500MC|PPCA2, 0, {FRS, RA0, RB}}, RA0 5977 arch/powerpc/xmon/ppc-opc.c {"stvswx", X(31,741), X_MASK, PPCVEC2, 0, {VS, RA0, RB}}, RA0 5979 arch/powerpc/xmon/ppc-opc.c {"stdat", X(31,742), X_MASK, POWER9, 0, {RS, RA0, FC}}, RA0 6007 arch/powerpc/xmon/ppc-opc.c {"dcba", X(31,758), XRT_MASK, PPC405|PPC7450|BOOKE|PPCA2|PPC476, 0, {RA0, RB}}, RA0 6008 arch/powerpc/xmon/ppc-opc.c {"dcbal", XOPL(31,758,1), XRT_MASK, E500MC, 0, {RA0, RB}}, RA0 6015 arch/powerpc/xmon/ppc-opc.c {"lvsm", X(31,773), X_MASK, PPCVEC2, 0, {VD, RA0, RB}}, RA0 6017 arch/powerpc/xmon/ppc-opc.c {"copy", XOPL(31,774,1), XRT_MASK, POWER9, 0, {RA0, RB}}, RA0 6019 arch/powerpc/xmon/ppc-opc.c {"stvepxl", X(31,775), X_MASK, PPCVEC2, 0, {VS, RA0, RB}}, RA0 6020 arch/powerpc/xmon/ppc-opc.c {"lvlxl", X(31,775), X_MASK, CELL, 0, {VD, RA0, RB}}, RA0 6034 arch/powerpc/xmon/ppc-opc.c {"lxvw4x", X(31,780), XX1_MASK, PPCVSX, 0, {XT6, RA0, RB}}, RA0 6035 arch/powerpc/xmon/ppc-opc.c {"lxsibzx", X(31,781), XX1_MASK, PPCVSX3, 0, {XT6, RA0, RB}}, RA0 6039 arch/powerpc/xmon/ppc-opc.c {"tlbivax", X(31,786), XRT_MASK, BOOKE|PPCA2|PPC476, 0, {RA0, RB}}, RA0 6041 arch/powerpc/xmon/ppc-opc.c {"lwzcix", X(31,789), X_MASK, POWER6, 0, {RT, RA0, RB}}, RA0 6043 arch/powerpc/xmon/ppc-opc.c {"lhbrx", X(31,790), X_MASK, COM, 0, {RT, RA0, RB}}, RA0 6045 arch/powerpc/xmon/ppc-opc.c {"lfdpx", X(31,791), X_MASK, POWER6, POWER7, {FRTp, RA0, RB}}, RA0 6058 arch/powerpc/xmon/ppc-opc.c {"lvtrxl", X(31,805), X_MASK, PPCVEC2, 0, {VD, RA0, RB}}, RA0 6059 arch/powerpc/xmon/ppc-opc.c {"stvepx", X(31,807), X_MASK, PPCVEC2, 0, {VS, RA0, RB}}, RA0 6060 arch/powerpc/xmon/ppc-opc.c {"lvrxl", X(31,807), X_MASK, CELL, 0, {VD, RA0, RB}}, RA0 6062 arch/powerpc/xmon/ppc-opc.c {"lxvh8x", X(31,812), XX1_MASK, PPCVSX3, 0, {XT6, RA0, RB}}, RA0 6063 arch/powerpc/xmon/ppc-opc.c {"lxsihzx", X(31,813), XX1_MASK, PPCVSX3, 0, {XT6, RA0, RB}}, RA0 6069 arch/powerpc/xmon/ppc-opc.c {"erativax", X(31,819), X_MASK, PPCA2, 0, {RS, RA0, RB}}, RA0 6071 arch/powerpc/xmon/ppc-opc.c {"lhzcix", X(31,821), X_MASK, POWER6, 0, {RT, RA0, RB}}, RA0 6085 arch/powerpc/xmon/ppc-opc.c {"lvtlxl", X(31,837), X_MASK, PPCVEC2, 0, {VD, RA0, RB}}, RA0 6092 arch/powerpc/xmon/ppc-opc.c {"lxvd2x", X(31,844), XX1_MASK, PPCVSX, 0, {XT6, RA0, RB}}, RA0 6093 arch/powerpc/xmon/ppc-opc.c {"lxvx", X(31,844), XX1_MASK, POWER8, POWER9|PPCVSX3, {XT6, RA0, RB}}, RA0 6097 arch/powerpc/xmon/ppc-opc.c {"tlbsrx.", XRC(31,850,1), XRT_MASK, PPCA2, 0, {RA0, RB}}, RA0 6103 arch/powerpc/xmon/ppc-opc.c {"lbzcix", X(31,853), X_MASK, POWER6, 0, {RT, RA0, RB}}, RA0 6110 arch/powerpc/xmon/ppc-opc.c {"lfiwax", X(31,855), X_MASK, POWER6|PPCA2|PPC476, 0, {FRT, RA0, RB}}, RA0 6112 arch/powerpc/xmon/ppc-opc.c {"lvswxl", X(31,869), X_MASK, PPCVEC2, 0, {VD, RA0, RB}}, RA0 6120 arch/powerpc/xmon/ppc-opc.c {"lxvb16x", X(31,876), XX1_MASK, PPCVSX3, 0, {XT6, RA0, RB}}, RA0 6126 arch/powerpc/xmon/ppc-opc.c {"ldcix", X(31,885), X_MASK, POWER6, 0, {RT, RA0, RB}}, RA0 6130 arch/powerpc/xmon/ppc-opc.c {"lfiwzx", X(31,887), X_MASK, POWER7|PPCA2, 0, {FRT, RA0, RB}}, RA0 6135 arch/powerpc/xmon/ppc-opc.c {"paste.", XRCL(31,902,1,1),XRT_MASK, POWER9, 0, {RA0, RB}}, RA0 6137 arch/powerpc/xmon/ppc-opc.c {"stvlxl", X(31,903), X_MASK, CELL, 0, {VS, RA0, RB}}, RA0 6145 arch/powerpc/xmon/ppc-opc.c {"stxvw4x", X(31,908), XX1_MASK, PPCVSX, 0, {XS6, RA0, RB}}, RA0 6146 arch/powerpc/xmon/ppc-opc.c {"stxsibx", X(31,909), XX1_MASK, PPCVSX3, 0, {XS6, RA0, RB}}, RA0 6150 arch/powerpc/xmon/ppc-opc.c {"tlbsx", XRC(31,914,0), X_MASK, PPC403|BOOKE|PPCA2|PPC476, 0, {RTO, RA0, RB}}, RA0 6151 arch/powerpc/xmon/ppc-opc.c {"tlbsx.", XRC(31,914,1), X_MASK, PPC403|BOOKE|PPCA2|PPC476, 0, {RTO, RA0, RB}}, RA0 6156 arch/powerpc/xmon/ppc-opc.c {"stwcix", X(31,917), X_MASK, POWER6, 0, {RS, RA0, RB}}, RA0 6158 arch/powerpc/xmon/ppc-opc.c {"sthbrx", X(31,918), X_MASK, COM, 0, {RS, RA0, RB}}, RA0 6160 arch/powerpc/xmon/ppc-opc.c {"stfdpx", X(31,919), X_MASK, POWER6, POWER7, {FRSp, RA0, RB}}, RA0 6161 arch/powerpc/xmon/ppc-opc.c {"stfqx", X(31,919), X_MASK, POWER2, 0, {FRS, RA0, RB}}, RA0 6176 arch/powerpc/xmon/ppc-opc.c {"stvfrxl", X(31,933), X_MASK, PPCVEC2, 0, {VS, RA0, RB}}, RA0 6178 arch/powerpc/xmon/ppc-opc.c {"wclrone", XOPL2(31,934,2),XRT_MASK, PPCA2, 0, {RA0, RB}}, RA0 6180 arch/powerpc/xmon/ppc-opc.c {"wclr", X(31,934), X_MASK, PPCA2, 0, {L2, RA0, RB}}, RA0 6182 arch/powerpc/xmon/ppc-opc.c {"stvrxl", X(31,935), X_MASK, CELL, 0, {VS, RA0, RB}}, RA0 6189 arch/powerpc/xmon/ppc-opc.c {"stxvh8x", X(31,940), XX1_MASK, PPCVSX3, 0, {XS6, RA0, RB}}, RA0 6190 arch/powerpc/xmon/ppc-opc.c {"stxsihx", X(31,941), XX1_MASK, PPCVSX3, 0, {XS6, RA0, RB}}, RA0 6198 arch/powerpc/xmon/ppc-opc.c {"sthcix", X(31,949), X_MASK, POWER6, 0, {RS, RA0, RB}}, RA0 6211 arch/powerpc/xmon/ppc-opc.c {"stvflxl", X(31,965), X_MASK, PPCVEC2, 0, {VS, RA0, RB}}, RA0 6222 arch/powerpc/xmon/ppc-opc.c {"stxvd2x", X(31,972), XX1_MASK, PPCVSX, 0, {XS6, RA0, RB}}, RA0 6223 arch/powerpc/xmon/ppc-opc.c {"stxvx", X(31,972), XX1_MASK, POWER8, POWER9|PPCVSX3, {XS6, RA0, RB}}, RA0 6232 arch/powerpc/xmon/ppc-opc.c {"stbcix", X(31,981), X_MASK, POWER6, 0, {RS, RA0, RB}}, RA0 6234 arch/powerpc/xmon/ppc-opc.c {"icbi", X(31,982), XRT_MASK, PPC, 0, {RA0, RB}}, RA0 6236 arch/powerpc/xmon/ppc-opc.c {"stfiwx", X(31,983), X_MASK, PPC, PPCEFS, {FRS, RA0, RB}}, RA0 6241 arch/powerpc/xmon/ppc-opc.c {"icbiep", XRT(31,991,0), XRT_MASK, E500MC|PPCA2, 0, {RA0, RB}}, RA0 6243 arch/powerpc/xmon/ppc-opc.c {"stvswxl", X(31,997), X_MASK, PPCVEC2, 0, {VS, RA0, RB}}, RA0 6245 arch/powerpc/xmon/ppc-opc.c {"icread", X(31,998), XRT_MASK, PPC403|PPC440|PPC476|TITAN, 0, {RA0, RB}}, RA0 6256 arch/powerpc/xmon/ppc-opc.c {"stxvb16x", X(31,1004), XX1_MASK, PPCVSX3, 0, {XS6, RA0, RB}}, RA0 6262 arch/powerpc/xmon/ppc-opc.c {"stdcix", X(31,1013), X_MASK, POWER6, 0, {RS, RA0, RB}}, RA0 6264 arch/powerpc/xmon/ppc-opc.c {"dcbz", X(31,1014), XRT_MASK, PPC, 0, {RA0, RB}}, RA0 6265 arch/powerpc/xmon/ppc-opc.c {"dclz", X(31,1014), XRT_MASK, PPC, 0, {RA0, RB}}, RA0 6267 arch/powerpc/xmon/ppc-opc.c {"dcbzep", XRT(31,1023,0), XRT_MASK, E500MC|PPCA2, 0, {RA0, RB}}, RA0 6269 arch/powerpc/xmon/ppc-opc.c {"dcbzl", XOPL(31,1014,1), XRT_MASK, POWER4|E500MC, PPC476, {RA0, RB}}, RA0 6284 arch/powerpc/xmon/ppc-opc.c {"lwz", OP(32), OP_MASK, PPCCOM, PPCVLE, {RT, D, RA0}}, RA0 6285 arch/powerpc/xmon/ppc-opc.c {"l", OP(32), OP_MASK, PWRCOM, PPCVLE, {RT, D, RA0}}, RA0 6288 arch/powerpc/xmon/ppc-opc.c {"lu", OP(33), OP_MASK, PWRCOM, PPCVLE, {RT, D, RA0}}, RA0 6290 arch/powerpc/xmon/ppc-opc.c {"lbz", OP(34), OP_MASK, COM, PPCVLE, {RT, D, RA0}}, RA0 6294 arch/powerpc/xmon/ppc-opc.c {"stw", OP(36), OP_MASK, PPCCOM, PPCVLE, {RS, D, RA0}}, RA0 6295 arch/powerpc/xmon/ppc-opc.c {"st", OP(36), OP_MASK, PWRCOM, PPCVLE, {RS, D, RA0}}, RA0 6298 arch/powerpc/xmon/ppc-opc.c {"stu", OP(37), OP_MASK, PWRCOM, PPCVLE, {RS, D, RA0}}, RA0 6300 arch/powerpc/xmon/ppc-opc.c {"stb", OP(38), OP_MASK, COM, PPCVLE, {RS, D, RA0}}, RA0 6304 arch/powerpc/xmon/ppc-opc.c {"lhz", OP(40), OP_MASK, COM, PPCVLE, {RT, D, RA0}}, RA0 6308 arch/powerpc/xmon/ppc-opc.c {"lha", OP(42), OP_MASK, COM, PPCVLE, {RT, D, RA0}}, RA0 6312 arch/powerpc/xmon/ppc-opc.c {"sth", OP(44), OP_MASK, COM, PPCVLE, {RS, D, RA0}}, RA0 6317 arch/powerpc/xmon/ppc-opc.c {"lm", OP(46), OP_MASK, PWRCOM, PPCVLE, {RT, D, RA0}}, RA0 6319 arch/powerpc/xmon/ppc-opc.c {"stmw", OP(47), OP_MASK, PPCCOM, PPCVLE, {RS, D, RA0}}, RA0 6320 arch/powerpc/xmon/ppc-opc.c {"stm", OP(47), OP_MASK, PWRCOM, PPCVLE, {RS, D, RA0}}, RA0 6322 arch/powerpc/xmon/ppc-opc.c {"lfs", OP(48), OP_MASK, COM, PPCEFS|PPCVLE, {FRT, D, RA0}}, RA0 6326 arch/powerpc/xmon/ppc-opc.c {"lfd", OP(50), OP_MASK, COM, PPCEFS|PPCVLE, {FRT, D, RA0}}, RA0 6330 arch/powerpc/xmon/ppc-opc.c {"stfs", OP(52), OP_MASK, COM, PPCEFS|PPCVLE, {FRS, D, RA0}}, RA0 6334 arch/powerpc/xmon/ppc-opc.c {"stfd", OP(54), OP_MASK, COM, PPCEFS|PPCVLE, {FRS, D, RA0}}, RA0 6340 arch/powerpc/xmon/ppc-opc.c {"lfq", OP(56), OP_MASK, POWER2, PPCVLE, {FRT, D, RA0}}, RA0 6342 arch/powerpc/xmon/ppc-opc.c {"lxsd", DSO(57,2), DS_MASK, PPCVSX3, PPCVLE, {VD, DS, RA0}}, RA0 6343 arch/powerpc/xmon/ppc-opc.c {"lxssp", DSO(57,3), DS_MASK, PPCVSX3, PPCVLE, {VD, DS, RA0}}, RA0 6344 arch/powerpc/xmon/ppc-opc.c {"lfdp", OP(57), OP_MASK, POWER6, POWER7|PPCVLE, {FRTp, DS, RA0}}, RA0 6346 arch/powerpc/xmon/ppc-opc.c {"lfqu", OP(57), OP_MASK, POWER2, PPCVLE, {FRT, D, RA0}}, RA0 6348 arch/powerpc/xmon/ppc-opc.c {"ld", DSO(58,0), DS_MASK, PPC64, PPCVLE, {RT, DS, RA0}}, RA0 6350 arch/powerpc/xmon/ppc-opc.c {"lwa", DSO(58,2), DS_MASK, PPC64, PPCVLE, {RT, DS, RA0}}, RA0 6665 arch/powerpc/xmon/ppc-opc.c {"lxv", DQX(61,1), DQX_MASK, PPCVSX3, PPCVLE, {XTQ6, DQ, RA0}}, RA0 6666 arch/powerpc/xmon/ppc-opc.c {"stxv", DQX(61,5), DQX_MASK, PPCVSX3, PPCVLE, {XSQ6, DQ, RA0}}, RA0 6667 arch/powerpc/xmon/ppc-opc.c {"stxsd", DSO(61,2), DS_MASK, PPCVSX3, PPCVLE, {VS, DS, RA0}}, RA0 6668 arch/powerpc/xmon/ppc-opc.c {"stxssp", DSO(61,3), DS_MASK, PPCVSX3, PPCVLE, {VS, DS, RA0}}, RA0 6669 arch/powerpc/xmon/ppc-opc.c {"stfdp", OP(61), OP_MASK, POWER6, POWER7|PPCVLE, {FRSp, DS, RA0}}, RA0 6673 arch/powerpc/xmon/ppc-opc.c {"std", DSO(62,0), DS_MASK, PPC64, PPCVLE, {RS, DS, RA0}}, RA0 6675 arch/powerpc/xmon/ppc-opc.c {"stq", DSO(62,2), DS_MASK, POWER4, PPC476|PPCVLE, {RSQ, DS, RA0}}, RA0 7033 arch/powerpc/xmon/ppc-opc.c {"e_lbzu", OPVUP(6,0), OPVUP_MASK, PPCVLE, 0, {RT, D8, RA0}}, RA0 7034 arch/powerpc/xmon/ppc-opc.c {"e_lhau", OPVUP(6,3), OPVUP_MASK, PPCVLE, 0, {RT, D8, RA0}}, RA0 7035 arch/powerpc/xmon/ppc-opc.c {"e_lhzu", OPVUP(6,1), OPVUP_MASK, PPCVLE, 0, {RT, D8, RA0}}, RA0 7036 arch/powerpc/xmon/ppc-opc.c {"e_lmw", OPVUP(6,8), OPVUP_MASK, PPCVLE, 0, {RT, D8, RA0}}, RA0 7037 arch/powerpc/xmon/ppc-opc.c {"e_lwzu", OPVUP(6,2), OPVUP_MASK, PPCVLE, 0, {RT, D8, RA0}}, RA0 7038 arch/powerpc/xmon/ppc-opc.c {"e_stbu", OPVUP(6,4), OPVUP_MASK, PPCVLE, 0, {RT, D8, RA0}}, RA0 7039 arch/powerpc/xmon/ppc-opc.c {"e_sthu", OPVUP(6,5), OPVUP_MASK, PPCVLE, 0, {RT, D8, RA0}}, RA0 7040 arch/powerpc/xmon/ppc-opc.c {"e_stwu", OPVUP(6,6), OPVUP_MASK, PPCVLE, 0, {RT, D8, RA0}}, RA0 7041 arch/powerpc/xmon/ppc-opc.c {"e_stmw", OPVUP(6,9), OPVUP_MASK, PPCVLE, 0, {RT, D8, RA0}}, RA0 7042 arch/powerpc/xmon/ppc-opc.c {"e_ldmvgprw", OPVUPRT(6,16,0),OPVUPRT_MASK, PPCVLE, 0, {D8, RA0}}, RA0 7043 arch/powerpc/xmon/ppc-opc.c {"e_stmvgprw", OPVUPRT(6,17,0),OPVUPRT_MASK, PPCVLE, 0, {D8, RA0}}, RA0 7044 arch/powerpc/xmon/ppc-opc.c {"e_ldmvsprw", OPVUPRT(6,16,1),OPVUPRT_MASK, PPCVLE, 0, {D8, RA0}}, RA0 7045 arch/powerpc/xmon/ppc-opc.c {"e_stmvsprw", OPVUPRT(6,17,1),OPVUPRT_MASK, PPCVLE, 0, {D8, RA0}}, RA0 7046 arch/powerpc/xmon/ppc-opc.c {"e_ldmvsrrw", OPVUPRT(6,16,4),OPVUPRT_MASK, PPCVLE, 0, {D8, RA0}}, RA0 7047 arch/powerpc/xmon/ppc-opc.c {"e_stmvsrrw", OPVUPRT(6,17,4),OPVUPRT_MASK, PPCVLE, 0, {D8, RA0}}, RA0 7048 arch/powerpc/xmon/ppc-opc.c {"e_ldmvcsrrw", OPVUPRT(6,16,5),OPVUPRT_MASK, PPCVLE, 0, {D8, RA0}}, RA0 7049 arch/powerpc/xmon/ppc-opc.c {"e_stmvcsrrw", OPVUPRT(6,17,5),OPVUPRT_MASK, PPCVLE, 0, {D8, RA0}}, RA0 7050 arch/powerpc/xmon/ppc-opc.c {"e_ldmvdsrrw", OPVUPRT(6,16,6),OPVUPRT_MASK, PPCVLE, 0, {D8, RA0}}, RA0 7051 arch/powerpc/xmon/ppc-opc.c {"e_stmvdsrrw", OPVUPRT(6,17,6),OPVUPRT_MASK, PPCVLE, 0, {D8, RA0}}, RA0 7053 arch/powerpc/xmon/ppc-opc.c {"e_la", OP(7), OP_MASK, PPCVLE, 0, {RT, D, RA0}}, RA0 7064 arch/powerpc/xmon/ppc-opc.c {"e_lbz", OP(12), OP_MASK, PPCVLE, 0, {RT, D, RA0}}, RA0 7065 arch/powerpc/xmon/ppc-opc.c {"e_stb", OP(13), OP_MASK, PPCVLE, 0, {RT, D, RA0}}, RA0 7066 arch/powerpc/xmon/ppc-opc.c {"e_lha", OP(14), OP_MASK, PPCVLE, 0, {RT, D, RA0}}, RA0 7078 arch/powerpc/xmon/ppc-opc.c {"e_lwz", OP(20), OP_MASK, PPCVLE, 0, {RT, D, RA0}}, RA0 7079 arch/powerpc/xmon/ppc-opc.c {"e_stw", OP(21), OP_MASK, PPCVLE, 0, {RT, D, RA0}}, RA0 7080 arch/powerpc/xmon/ppc-opc.c {"e_lhz", OP(22), OP_MASK, PPCVLE, 0, {RT, D, RA0}}, RA0 7081 arch/powerpc/xmon/ppc-opc.c {"e_sth", OP(23), OP_MASK, PPCVLE, 0, {RT, D, RA0}},