RA 325 arch/mips/kvm/entry.c uasm_i_jalr(&p, RA, T9); RA 417 arch/mips/kvm/entry.c uasm_i_jalr(&p, RA, T9); RA 727 arch/mips/kvm/entry.c uasm_i_jalr(&p, RA, T9); RA 798 arch/mips/kvm/entry.c uasm_i_jalr(&p, RA, T9); RA 937 arch/mips/kvm/entry.c UASM_i_LW(&p, RA, offsetof(struct pt_regs, regs[RA]), K1); RA 938 arch/mips/kvm/entry.c uasm_i_jr(&p, RA); RA 350 arch/mips/mm/page.c uasm_i_jr(&buf, RA); RA 594 arch/mips/mm/page.c uasm_i_jr(&buf, RA); RA 318 arch/nds32/mm/alignment.c unaligned_addr = *idx_to_addr(regs, RA(inst)); RA 502 arch/nds32/mm/alignment.c *idx_to_addr(regs, RA(inst)) = unaligned_addr + shift; RA 507 arch/powerpc/xmon/ppc-opc.c #define RA0 RA + 1 RA 3038 arch/powerpc/xmon/ppc-opc.c {"tdlgti", OPTO(2,TOLGT), OPTO_MASK, PPC64, PPCVLE, {RA, SI}}, RA 3039 arch/powerpc/xmon/ppc-opc.c {"tdllti", OPTO(2,TOLLT), OPTO_MASK, PPC64, PPCVLE, {RA, SI}}, RA 3040 arch/powerpc/xmon/ppc-opc.c {"tdeqi", OPTO(2,TOEQ), OPTO_MASK, PPC64, PPCVLE, {RA, SI}}, RA 3041 arch/powerpc/xmon/ppc-opc.c {"tdlgei", OPTO(2,TOLGE), OPTO_MASK, PPC64, PPCVLE, {RA, SI}}, RA 3042 arch/powerpc/xmon/ppc-opc.c {"tdlnli", OPTO(2,TOLNL), OPTO_MASK, PPC64, PPCVLE, {RA, SI}}, RA 3043 arch/powerpc/xmon/ppc-opc.c {"tdllei", OPTO(2,TOLLE), OPTO_MASK, PPC64, PPCVLE, {RA, SI}}, RA 3044 arch/powerpc/xmon/ppc-opc.c {"tdlngi", OPTO(2,TOLNG), OPTO_MASK, PPC64, PPCVLE, {RA, SI}}, RA 3045 arch/powerpc/xmon/ppc-opc.c {"tdgti", OPTO(2,TOGT), OPTO_MASK, PPC64, PPCVLE, {RA, SI}}, RA 3046 arch/powerpc/xmon/ppc-opc.c {"tdgei", OPTO(2,TOGE), OPTO_MASK, PPC64, PPCVLE, {RA, SI}}, RA 3047 arch/powerpc/xmon/ppc-opc.c {"tdnli", OPTO(2,TONL), OPTO_MASK, PPC64, PPCVLE, {RA, SI}}, RA 3048 arch/powerpc/xmon/ppc-opc.c {"tdlti", OPTO(2,TOLT), OPTO_MASK, PPC64, PPCVLE, {RA, SI}}, RA 3049 arch/powerpc/xmon/ppc-opc.c {"tdlei", OPTO(2,TOLE), OPTO_MASK, PPC64, PPCVLE, {RA, SI}}, RA 3050 arch/powerpc/xmon/ppc-opc.c {"tdngi", OPTO(2,TONG), OPTO_MASK, PPC64, PPCVLE, {RA, SI}}, RA 3051 arch/powerpc/xmon/ppc-opc.c {"tdnei", OPTO(2,TONE), OPTO_MASK, PPC64, PPCVLE, {RA, SI}}, RA 3052 arch/powerpc/xmon/ppc-opc.c {"tdui", OPTO(2,TOU), OPTO_MASK, PPC64, PPCVLE, {RA, SI}}, RA 3053 arch/powerpc/xmon/ppc-opc.c {"tdi", OP(2), OP_MASK, PPC64, PPCVLE, {TO, RA, SI}}, RA 3055 arch/powerpc/xmon/ppc-opc.c {"twlgti", OPTO(3,TOLGT), OPTO_MASK, PPCCOM, PPCVLE, {RA, SI}}, RA 3056 arch/powerpc/xmon/ppc-opc.c {"tlgti", OPTO(3,TOLGT), OPTO_MASK, PWRCOM, PPCVLE, {RA, SI}}, RA 3057 arch/powerpc/xmon/ppc-opc.c {"twllti", OPTO(3,TOLLT), OPTO_MASK, PPCCOM, PPCVLE, {RA, SI}}, RA 3058 arch/powerpc/xmon/ppc-opc.c {"tllti", OPTO(3,TOLLT), OPTO_MASK, PWRCOM, PPCVLE, {RA, SI}}, RA 3059 arch/powerpc/xmon/ppc-opc.c {"tweqi", OPTO(3,TOEQ), OPTO_MASK, PPCCOM, PPCVLE, {RA, SI}}, RA 3060 arch/powerpc/xmon/ppc-opc.c {"teqi", OPTO(3,TOEQ), OPTO_MASK, PWRCOM, PPCVLE, {RA, SI}}, RA 3061 arch/powerpc/xmon/ppc-opc.c {"twlgei", OPTO(3,TOLGE), OPTO_MASK, PPCCOM, PPCVLE, {RA, SI}}, RA 3062 arch/powerpc/xmon/ppc-opc.c {"tlgei", OPTO(3,TOLGE), OPTO_MASK, PWRCOM, PPCVLE, {RA, SI}}, RA 3063 arch/powerpc/xmon/ppc-opc.c {"twlnli", OPTO(3,TOLNL), OPTO_MASK, PPCCOM, PPCVLE, {RA, SI}}, RA 3064 arch/powerpc/xmon/ppc-opc.c {"tlnli", OPTO(3,TOLNL), OPTO_MASK, PWRCOM, PPCVLE, {RA, SI}}, RA 3065 arch/powerpc/xmon/ppc-opc.c {"twllei", OPTO(3,TOLLE), OPTO_MASK, PPCCOM, PPCVLE, {RA, SI}}, RA 3066 arch/powerpc/xmon/ppc-opc.c {"tllei", OPTO(3,TOLLE), OPTO_MASK, PWRCOM, PPCVLE, {RA, SI}}, RA 3067 arch/powerpc/xmon/ppc-opc.c {"twlngi", OPTO(3,TOLNG), OPTO_MASK, PPCCOM, PPCVLE, {RA, SI}}, RA 3068 arch/powerpc/xmon/ppc-opc.c {"tlngi", OPTO(3,TOLNG), OPTO_MASK, PWRCOM, PPCVLE, {RA, SI}}, RA 3069 arch/powerpc/xmon/ppc-opc.c {"twgti", OPTO(3,TOGT), OPTO_MASK, PPCCOM, PPCVLE, {RA, SI}}, RA 3070 arch/powerpc/xmon/ppc-opc.c {"tgti", OPTO(3,TOGT), OPTO_MASK, PWRCOM, PPCVLE, {RA, SI}}, RA 3071 arch/powerpc/xmon/ppc-opc.c {"twgei", OPTO(3,TOGE), OPTO_MASK, PPCCOM, PPCVLE, {RA, SI}}, RA 3072 arch/powerpc/xmon/ppc-opc.c {"tgei", OPTO(3,TOGE), OPTO_MASK, PWRCOM, PPCVLE, {RA, SI}}, RA 3073 arch/powerpc/xmon/ppc-opc.c {"twnli", OPTO(3,TONL), OPTO_MASK, PPCCOM, PPCVLE, {RA, SI}}, RA 3074 arch/powerpc/xmon/ppc-opc.c {"tnli", OPTO(3,TONL), OPTO_MASK, PWRCOM, PPCVLE, {RA, SI}}, RA 3075 arch/powerpc/xmon/ppc-opc.c {"twlti", OPTO(3,TOLT), OPTO_MASK, PPCCOM, PPCVLE, {RA, SI}}, RA 3076 arch/powerpc/xmon/ppc-opc.c {"tlti", OPTO(3,TOLT), OPTO_MASK, PWRCOM, PPCVLE, {RA, SI}}, RA 3077 arch/powerpc/xmon/ppc-opc.c {"twlei", OPTO(3,TOLE), OPTO_MASK, PPCCOM, PPCVLE, {RA, SI}}, RA 3078 arch/powerpc/xmon/ppc-opc.c {"tlei", OPTO(3,TOLE), OPTO_MASK, PWRCOM, PPCVLE, {RA, SI}}, RA 3079 arch/powerpc/xmon/ppc-opc.c {"twngi", OPTO(3,TONG), OPTO_MASK, PPCCOM, PPCVLE, {RA, SI}}, RA 3080 arch/powerpc/xmon/ppc-opc.c {"tngi", OPTO(3,TONG), OPTO_MASK, PWRCOM, PPCVLE, {RA, SI}}, RA 3081 arch/powerpc/xmon/ppc-opc.c {"twnei", OPTO(3,TONE), OPTO_MASK, PPCCOM, PPCVLE, {RA, SI}}, RA 3082 arch/powerpc/xmon/ppc-opc.c {"tnei", OPTO(3,TONE), OPTO_MASK, PWRCOM, PPCVLE, {RA, SI}}, RA 3083 arch/powerpc/xmon/ppc-opc.c {"twui", OPTO(3,TOU), OPTO_MASK, PPCCOM, PPCVLE, {RA, SI}}, RA 3084 arch/powerpc/xmon/ppc-opc.c {"tui", OPTO(3,TOU), OPTO_MASK, PWRCOM, PPCVLE, {RA, SI}}, RA 3085 arch/powerpc/xmon/ppc-opc.c {"twi", OP(3), OP_MASK, PPCCOM, PPCVLE, {TO, RA, SI}}, RA 3086 arch/powerpc/xmon/ppc-opc.c {"ti", OP(3), OP_MASK, PWRCOM, PPCVLE, {TO, RA, SI}}, RA 3097 arch/powerpc/xmon/ppc-opc.c {"psq_lx", XW (4, 6,0), XW_MASK, PPCPS, 0, {FRT,RA,RB,PSWM,PSQM}}, RA 3099 arch/powerpc/xmon/ppc-opc.c {"psq_stx", XW (4, 7,0), XW_MASK, PPCPS, 0, {FRS,RA,RB,PSWM,PSQM}}, RA 3101 arch/powerpc/xmon/ppc-opc.c {"mulhhwu", XRC(4, 8,0), X_MASK, MULHW, 0, {RT, RA, RB}}, RA 3102 arch/powerpc/xmon/ppc-opc.c {"mulhhwu.", XRC(4, 8,1), X_MASK, MULHW, 0, {RT, RA, RB}}, RA 3108 arch/powerpc/xmon/ppc-opc.c {"machhwu", XO (4, 12,0,0), XO_MASK, MULHW, 0, {RT, RA, RB}}, RA 3110 arch/powerpc/xmon/ppc-opc.c {"machhwu.", XO (4, 12,0,1), XO_MASK, MULHW, 0, {RT, RA, RB}}, RA 3142 arch/powerpc/xmon/ppc-opc.c {"maddhd", VXA(4, 48), VXA_MASK, POWER9, 0, {RT, RA, RB, RC}}, RA 3144 arch/powerpc/xmon/ppc-opc.c {"maddhdu", VXA(4, 49), VXA_MASK, POWER9, 0, {RT, RA, RB, RC}}, RA 3147 arch/powerpc/xmon/ppc-opc.c {"maddld", VXA(4, 51), VXA_MASK, POWER9, 0, {RT, RA, RB, RC}}, RA 3172 arch/powerpc/xmon/ppc-opc.c {"psq_lux", XW (4, 38,0), XW_MASK, PPCPS, 0, {FRT,RA,RB,PSWM,PSQM}}, RA 3174 arch/powerpc/xmon/ppc-opc.c {"psq_stux", XW (4, 39,0), XW_MASK, PPCPS, 0, {FRS,RA,RB,PSWM,PSQM}}, RA 3177 arch/powerpc/xmon/ppc-opc.c {"mulhhw", XRC(4, 40,0), X_MASK, MULHW, 0, {RT, RA, RB}}, RA 3179 arch/powerpc/xmon/ppc-opc.c {"mulhhw.", XRC(4, 40,1), X_MASK, MULHW, 0, {RT, RA, RB}}, RA 3180 arch/powerpc/xmon/ppc-opc.c {"machhw", XO (4, 44,0,0), XO_MASK, MULHW, 0, {RT, RA, RB}}, RA 3181 arch/powerpc/xmon/ppc-opc.c {"machhw.", XO (4, 44,0,1), XO_MASK, MULHW, 0, {RT, RA, RB}}, RA 3182 arch/powerpc/xmon/ppc-opc.c {"nmachhw", XO (4, 46,0,0), XO_MASK, MULHW, 0, {RT, RA, RB}}, RA 3183 arch/powerpc/xmon/ppc-opc.c {"nmachhw.", XO (4, 46,0,1), XO_MASK, MULHW, 0, {RT, RA, RB}}, RA 3197 arch/powerpc/xmon/ppc-opc.c {"machhwsu", XO (4, 76,0,0), XO_MASK, MULHW, 0, {RT, RA, RB}}, RA 3198 arch/powerpc/xmon/ppc-opc.c {"machhwsu.", XO (4, 76,0,1), XO_MASK, MULHW, 0, {RT, RA, RB}}, RA 3207 arch/powerpc/xmon/ppc-opc.c {"machhws", XO (4, 108,0,0), XO_MASK, MULHW, 0, {RT, RA, RB}}, RA 3208 arch/powerpc/xmon/ppc-opc.c {"machhws.", XO (4, 108,0,1), XO_MASK, MULHW, 0, {RT, RA, RB}}, RA 3209 arch/powerpc/xmon/ppc-opc.c {"nmachhws", XO (4, 110,0,0), XO_MASK, MULHW, 0, {RT, RA, RB}}, RA 3210 arch/powerpc/xmon/ppc-opc.c {"nmachhws.", XO (4, 110,0,1), XO_MASK, MULHW, 0, {RT, RA, RB}}, RA 3220 arch/powerpc/xmon/ppc-opc.c {"mulchwu", XRC(4, 136,0), X_MASK, MULHW, 0, {RT, RA, RB}}, RA 3222 arch/powerpc/xmon/ppc-opc.c {"mulchwu.", XRC(4, 136,1), X_MASK, MULHW, 0, {RT, RA, RB}}, RA 3223 arch/powerpc/xmon/ppc-opc.c {"macchwu", XO (4, 140,0,0), XO_MASK, MULHW, 0, {RT, RA, RB}}, RA 3224 arch/powerpc/xmon/ppc-opc.c {"macchwu.", XO (4, 140,0,1), XO_MASK, MULHW, 0, {RT, RA, RB}}, RA 3233 arch/powerpc/xmon/ppc-opc.c {"mulchw", XRC(4, 168,0), X_MASK, MULHW, 0, {RT, RA, RB}}, RA 3234 arch/powerpc/xmon/ppc-opc.c {"mulchw.", XRC(4, 168,1), X_MASK, MULHW, 0, {RT, RA, RB}}, RA 3235 arch/powerpc/xmon/ppc-opc.c {"macchw", XO (4, 172,0,0), XO_MASK, MULHW, 0, {RT, RA, RB}}, RA 3236 arch/powerpc/xmon/ppc-opc.c {"macchw.", XO (4, 172,0,1), XO_MASK, MULHW, 0, {RT, RA, RB}}, RA 3237 arch/powerpc/xmon/ppc-opc.c {"nmacchw", XO (4, 174,0,0), XO_MASK, MULHW, 0, {RT, RA, RB}}, RA 3238 arch/powerpc/xmon/ppc-opc.c {"nmacchw.", XO (4, 174,0,1), XO_MASK, MULHW, 0, {RT, RA, RB}}, RA 3248 arch/powerpc/xmon/ppc-opc.c {"macchwsu", XO (4, 204,0,0), XO_MASK, MULHW, 0, {RT, RA, RB}}, RA 3249 arch/powerpc/xmon/ppc-opc.c {"macchwsu.", XO (4, 204,0,1), XO_MASK, MULHW, 0, {RT, RA, RB}}, RA 3256 arch/powerpc/xmon/ppc-opc.c {"macchws", XO (4, 236,0,0), XO_MASK, MULHW, 0, {RT, RA, RB}}, RA 3257 arch/powerpc/xmon/ppc-opc.c {"macchws.", XO (4, 236,0,1), XO_MASK, MULHW, 0, {RT, RA, RB}}, RA 3258 arch/powerpc/xmon/ppc-opc.c {"nmacchws", XO (4, 238,0,0), XO_MASK, MULHW, 0, {RT, RA, RB}}, RA 3259 arch/powerpc/xmon/ppc-opc.c {"nmacchws.", XO (4, 238,0,1), XO_MASK, MULHW, 0, {RT, RA, RB}}, RA 3260 arch/powerpc/xmon/ppc-opc.c {"evaddw", VX (4, 512), VX_MASK, PPCSPE, 0, {RS, RA, RB}}, RA 3265 arch/powerpc/xmon/ppc-opc.c {"evsubfw", VX (4, 516), VX_MASK, PPCSPE, 0, {RS, RA, RB}}, RA 3266 arch/powerpc/xmon/ppc-opc.c {"evsubw", VX (4, 516), VX_MASK, PPCSPE, 0, {RS, RB, RA}}, RA 3271 arch/powerpc/xmon/ppc-opc.c {"evabs", VX (4, 520), VX_MASK, PPCSPE, 0, {RS, RA}}, RA 3273 arch/powerpc/xmon/ppc-opc.c {"evneg", VX (4, 521), VX_MASK, PPCSPE, 0, {RS, RA}}, RA 3274 arch/powerpc/xmon/ppc-opc.c {"evextsb", VX (4, 522), VX_MASK, PPCSPE, 0, {RS, RA}}, RA 3276 arch/powerpc/xmon/ppc-opc.c {"evextsh", VX (4, 523), VX_MASK, PPCSPE, 0, {RS, RA}}, RA 3277 arch/powerpc/xmon/ppc-opc.c {"evrndw", VX (4, 524), VX_MASK, PPCSPE, 0, {RS, RA}}, RA 3280 arch/powerpc/xmon/ppc-opc.c {"evcntlzw", VX (4, 525), VX_MASK, PPCSPE, 0, {RS, RA}}, RA 3281 arch/powerpc/xmon/ppc-opc.c {"evcntlsw", VX (4, 526), VX_MASK, PPCSPE, 0, {RS, RA}}, RA 3283 arch/powerpc/xmon/ppc-opc.c {"brinc", VX (4, 527), VX_MASK, PPCSPE, 0, {RS, RA, RB}}, RA 3286 arch/powerpc/xmon/ppc-opc.c {"evand", VX (4, 529), VX_MASK, PPCSPE, 0, {RS, RA, RB}}, RA 3287 arch/powerpc/xmon/ppc-opc.c {"evandc", VX (4, 530), VX_MASK, PPCSPE, 0, {RS, RA, RB}}, RA 3288 arch/powerpc/xmon/ppc-opc.c {"evxor", VX (4, 534), VX_MASK, PPCSPE, 0, {RS, RA, RB}}, RA 3289 arch/powerpc/xmon/ppc-opc.c {"evmr", VX (4, 535), VX_MASK, PPCSPE, 0, {RS, RA, BBA}}, RA 3290 arch/powerpc/xmon/ppc-opc.c {"evor", VX (4, 535), VX_MASK, PPCSPE, 0, {RS, RA, RB}}, RA 3291 arch/powerpc/xmon/ppc-opc.c {"evnor", VX (4, 536), VX_MASK, PPCSPE, 0, {RS, RA, RB}}, RA 3292 arch/powerpc/xmon/ppc-opc.c {"evnot", VX (4, 536), VX_MASK, PPCSPE, 0, {RS, RA, BBA}}, RA 3294 arch/powerpc/xmon/ppc-opc.c {"eveqv", VX (4, 537), VX_MASK, PPCSPE, 0, {RS, RA, RB}}, RA 3295 arch/powerpc/xmon/ppc-opc.c {"evorc", VX (4, 539), VX_MASK, PPCSPE, 0, {RS, RA, RB}}, RA 3296 arch/powerpc/xmon/ppc-opc.c {"evnand", VX (4, 542), VX_MASK, PPCSPE, 0, {RS, RA, RB}}, RA 3297 arch/powerpc/xmon/ppc-opc.c {"evsrwu", VX (4, 544), VX_MASK, PPCSPE, 0, {RS, RA, RB}}, RA 3298 arch/powerpc/xmon/ppc-opc.c {"evsrws", VX (4, 545), VX_MASK, PPCSPE, 0, {RS, RA, RB}}, RA 3299 arch/powerpc/xmon/ppc-opc.c {"evsrwiu", VX (4, 546), VX_MASK, PPCSPE, 0, {RS, RA, EVUIMM}}, RA 3300 arch/powerpc/xmon/ppc-opc.c {"evsrwis", VX (4, 547), VX_MASK, PPCSPE, 0, {RS, RA, EVUIMM}}, RA 3301 arch/powerpc/xmon/ppc-opc.c {"evslw", VX (4, 548), VX_MASK, PPCSPE, 0, {RS, RA, RB}}, RA 3302 arch/powerpc/xmon/ppc-opc.c {"evslwi", VX (4, 550), VX_MASK, PPCSPE, 0, {RS, RA, EVUIMM}}, RA 3303 arch/powerpc/xmon/ppc-opc.c {"evrlw", VX (4, 552), VX_MASK, PPCSPE, 0, {RS, RA, RB}}, RA 3305 arch/powerpc/xmon/ppc-opc.c {"evrlwi", VX (4, 554), VX_MASK, PPCSPE, 0, {RS, RA, EVUIMM}}, RA 3307 arch/powerpc/xmon/ppc-opc.c {"evmergehi", VX (4, 556), VX_MASK, PPCSPE, 0, {RS, RA, RB}}, RA 3308 arch/powerpc/xmon/ppc-opc.c {"evmergelo", VX (4, 557), VX_MASK, PPCSPE, 0, {RS, RA, RB}}, RA 3309 arch/powerpc/xmon/ppc-opc.c {"evmergehilo", VX (4, 558), VX_MASK, PPCSPE, 0, {RS, RA, RB}}, RA 3310 arch/powerpc/xmon/ppc-opc.c {"evmergelohi", VX (4, 559), VX_MASK, PPCSPE, 0, {RS, RA, RB}}, RA 3311 arch/powerpc/xmon/ppc-opc.c {"evcmpgtu", VX (4, 560), VX_MASK, PPCSPE, 0, {CRFD, RA, RB}}, RA 3312 arch/powerpc/xmon/ppc-opc.c {"evcmpgts", VX (4, 561), VX_MASK, PPCSPE, 0, {CRFD, RA, RB}}, RA 3313 arch/powerpc/xmon/ppc-opc.c {"evcmpltu", VX (4, 562), VX_MASK, PPCSPE, 0, {CRFD, RA, RB}}, RA 3314 arch/powerpc/xmon/ppc-opc.c {"evcmplts", VX (4, 563), VX_MASK, PPCSPE, 0, {CRFD, RA, RB}}, RA 3315 arch/powerpc/xmon/ppc-opc.c {"evcmpeq", VX (4, 564), VX_MASK, PPCSPE, 0, {CRFD, RA, RB}}, RA 3328 arch/powerpc/xmon/ppc-opc.c {"evsel", EVSEL(4,79), EVSEL_MASK, PPCSPE, 0, {RS, RA, RB, CRFS}}, RA 3330 arch/powerpc/xmon/ppc-opc.c {"evfsadd", VX (4, 640), VX_MASK, PPCSPE, 0, {RS, RA, RB}}, RA 3332 arch/powerpc/xmon/ppc-opc.c {"evfssub", VX (4, 641), VX_MASK, PPCSPE, 0, {RS, RA, RB}}, RA 3334 arch/powerpc/xmon/ppc-opc.c {"evfsabs", VX (4, 644), VX_MASK, PPCSPE, 0, {RS, RA}}, RA 3336 arch/powerpc/xmon/ppc-opc.c {"evfsnabs", VX (4, 645), VX_MASK, PPCSPE, 0, {RS, RA}}, RA 3337 arch/powerpc/xmon/ppc-opc.c {"evfsneg", VX (4, 646), VX_MASK, PPCSPE, 0, {RS, RA}}, RA 3340 arch/powerpc/xmon/ppc-opc.c {"evfsmul", VX (4, 648), VX_MASK, PPCSPE, 0, {RS, RA, RB}}, RA 3341 arch/powerpc/xmon/ppc-opc.c {"evfsdiv", VX (4, 649), VX_MASK, PPCSPE, 0, {RS, RA, RB}}, RA 3343 arch/powerpc/xmon/ppc-opc.c {"evfscmpgt", VX (4, 652), VX_MASK, PPCSPE, 0, {CRFD, RA, RB}}, RA 3346 arch/powerpc/xmon/ppc-opc.c {"evfscmplt", VX (4, 653), VX_MASK, PPCSPE, 0, {CRFD, RA, RB}}, RA 3347 arch/powerpc/xmon/ppc-opc.c {"evfscmpeq", VX (4, 654), VX_MASK, PPCSPE, 0, {CRFD, RA, RB}}, RA 3358 arch/powerpc/xmon/ppc-opc.c {"put", APU(4, 332,0), APU_RT_MASK, PPC405, 0, {RA, FSL}}, RA 3360 arch/powerpc/xmon/ppc-opc.c {"evfststgt", VX (4, 668), VX_MASK, PPCSPE, 0, {CRFD, RA, RB}}, RA 3361 arch/powerpc/xmon/ppc-opc.c {"evfststlt", VX (4, 669), VX_MASK, PPCSPE, 0, {CRFD, RA, RB}}, RA 3362 arch/powerpc/xmon/ppc-opc.c {"evfststeq", VX (4, 670), VX_MASK, PPCSPE, 0, {CRFD, RA, RB}}, RA 3363 arch/powerpc/xmon/ppc-opc.c {"cput", APU(4, 348,0), APU_RT_MASK, PPC405, 0, {RA, FSL}}, RA 3364 arch/powerpc/xmon/ppc-opc.c {"efsadd", VX (4, 704), VX_MASK, PPCEFS, 0, {RS, RA, RB}}, RA 3365 arch/powerpc/xmon/ppc-opc.c {"efssub", VX (4, 705), VX_MASK, PPCEFS, 0, {RS, RA, RB}}, RA 3367 arch/powerpc/xmon/ppc-opc.c {"efsabs", VX (4, 708), VX_MASK, PPCEFS, 0, {RS, RA}}, RA 3369 arch/powerpc/xmon/ppc-opc.c {"efsnabs", VX (4, 709), VX_MASK, PPCEFS, 0, {RS, RA}}, RA 3370 arch/powerpc/xmon/ppc-opc.c {"efsneg", VX (4, 710), VX_MASK, PPCEFS, 0, {RS, RA}}, RA 3373 arch/powerpc/xmon/ppc-opc.c {"efsmul", VX (4, 712), VX_MASK, PPCEFS, 0, {RS, RA, RB}}, RA 3374 arch/powerpc/xmon/ppc-opc.c {"efsdiv", VX (4, 713), VX_MASK, PPCEFS, 0, {RS, RA, RB}}, RA 3376 arch/powerpc/xmon/ppc-opc.c {"efscmpgt", VX (4, 716), VX_MASK, PPCEFS, 0, {CRFD, RA, RB}}, RA 3378 arch/powerpc/xmon/ppc-opc.c {"efscmplt", VX (4, 717), VX_MASK, PPCEFS, 0, {CRFD, RA, RB}}, RA 3379 arch/powerpc/xmon/ppc-opc.c {"efscmpeq", VX (4, 718), VX_MASK, PPCEFS, 0, {CRFD, RA, RB}}, RA 3391 arch/powerpc/xmon/ppc-opc.c {"nput", APU(4, 364,0), APU_RT_MASK, PPC405, 0, {RA, FSL}}, RA 3393 arch/powerpc/xmon/ppc-opc.c {"efststgt", VX (4, 732), VX_MASK, PPCEFS, 0, {CRFD, RA, RB}}, RA 3394 arch/powerpc/xmon/ppc-opc.c {"efststlt", VX (4, 733), VX_MASK, PPCEFS, 0, {CRFD, RA, RB}}, RA 3395 arch/powerpc/xmon/ppc-opc.c {"efststeq", VX (4, 734), VX_MASK, PPCEFS, 0, {CRFD, RA, RB}}, RA 3396 arch/powerpc/xmon/ppc-opc.c {"efdadd", VX (4, 736), VX_MASK, PPCEFS, 0, {RS, RA, RB}}, RA 3397 arch/powerpc/xmon/ppc-opc.c {"efdsub", VX (4, 737), VX_MASK, PPCEFS, 0, {RS, RA, RB}}, RA 3400 arch/powerpc/xmon/ppc-opc.c {"efdabs", VX (4, 740), VX_MASK, PPCEFS, 0, {RS, RA}}, RA 3401 arch/powerpc/xmon/ppc-opc.c {"efdnabs", VX (4, 741), VX_MASK, PPCEFS, 0, {RS, RA}}, RA 3402 arch/powerpc/xmon/ppc-opc.c {"efdneg", VX (4, 742), VX_MASK, PPCEFS, 0, {RS, RA}}, RA 3403 arch/powerpc/xmon/ppc-opc.c {"efdmul", VX (4, 744), VX_MASK, PPCEFS, 0, {RS, RA, RB}}, RA 3404 arch/powerpc/xmon/ppc-opc.c {"efddiv", VX (4, 745), VX_MASK, PPCEFS, 0, {RS, RA, RB}}, RA 3407 arch/powerpc/xmon/ppc-opc.c {"efdcmpgt", VX (4, 748), VX_MASK, PPCEFS, 0, {CRFD, RA, RB}}, RA 3408 arch/powerpc/xmon/ppc-opc.c {"efdcmplt", VX (4, 749), VX_MASK, PPCEFS, 0, {CRFD, RA, RB}}, RA 3409 arch/powerpc/xmon/ppc-opc.c {"efdcmpeq", VX (4, 750), VX_MASK, PPCEFS, 0, {CRFD, RA, RB}}, RA 3420 arch/powerpc/xmon/ppc-opc.c {"ncput", APU(4, 380,0), APU_RT_MASK, PPC405, 0, {RA, FSL}}, RA 3422 arch/powerpc/xmon/ppc-opc.c {"efdtstgt", VX (4, 764), VX_MASK, PPCEFS, 0, {CRFD, RA, RB}}, RA 3423 arch/powerpc/xmon/ppc-opc.c {"efdtstlt", VX (4, 765), VX_MASK, PPCEFS, 0, {CRFD, RA, RB}}, RA 3424 arch/powerpc/xmon/ppc-opc.c {"efdtsteq", VX (4, 766), VX_MASK, PPCEFS, 0, {CRFD, RA, RB}}, RA 3425 arch/powerpc/xmon/ppc-opc.c {"evlddx", VX (4, 768), VX_MASK, PPCSPE, 0, {RS, RA, RB}}, RA 3427 arch/powerpc/xmon/ppc-opc.c {"evldd", VX (4, 769), VX_MASK, PPCSPE, 0, {RS, EVUIMM_8, RA}}, RA 3428 arch/powerpc/xmon/ppc-opc.c {"evldwx", VX (4, 770), VX_MASK, PPCSPE, 0, {RS, RA, RB}}, RA 3430 arch/powerpc/xmon/ppc-opc.c {"evldw", VX (4, 771), VX_MASK, PPCSPE, 0, {RS, EVUIMM_8, RA}}, RA 3431 arch/powerpc/xmon/ppc-opc.c {"evldhx", VX (4, 772), VX_MASK, PPCSPE, 0, {RS, RA, RB}}, RA 3433 arch/powerpc/xmon/ppc-opc.c {"evldh", VX (4, 773), VX_MASK, PPCSPE, 0, {RS, EVUIMM_8, RA}}, RA 3435 arch/powerpc/xmon/ppc-opc.c {"evlhhesplatx",VX (4, 776), VX_MASK, PPCSPE, 0, {RS, RA, RB}}, RA 3437 arch/powerpc/xmon/ppc-opc.c {"evlhhesplat", VX (4, 777), VX_MASK, PPCSPE, 0, {RS, EVUIMM_2, RA}}, RA 3440 arch/powerpc/xmon/ppc-opc.c {"evlhhousplatx",VX(4, 780), VX_MASK, PPCSPE, 0, {RS, RA, RB}}, RA 3443 arch/powerpc/xmon/ppc-opc.c {"evlhhousplat",VX (4, 781), VX_MASK, PPCSPE, 0, {RS, EVUIMM_2, RA}}, RA 3444 arch/powerpc/xmon/ppc-opc.c {"evlhhossplatx",VX(4, 782), VX_MASK, PPCSPE, 0, {RS, RA, RB}}, RA 3446 arch/powerpc/xmon/ppc-opc.c {"evlhhossplat",VX (4, 783), VX_MASK, PPCSPE, 0, {RS, EVUIMM_2, RA}}, RA 3447 arch/powerpc/xmon/ppc-opc.c {"mullhwu", XRC(4, 392,0), X_MASK, MULHW, 0, {RT, RA, RB}}, RA 3448 arch/powerpc/xmon/ppc-opc.c {"evlwhex", VX (4, 784), VX_MASK, PPCSPE, 0, {RS, RA, RB}}, RA 3449 arch/powerpc/xmon/ppc-opc.c {"mullhwu.", XRC(4, 392,1), X_MASK, MULHW, 0, {RT, RA, RB}}, RA 3450 arch/powerpc/xmon/ppc-opc.c {"evlwhe", VX (4, 785), VX_MASK, PPCSPE, 0, {RS, EVUIMM_4, RA}}, RA 3451 arch/powerpc/xmon/ppc-opc.c {"evlwhoux", VX (4, 788), VX_MASK, PPCSPE, 0, {RS, RA, RB}}, RA 3452 arch/powerpc/xmon/ppc-opc.c {"evlwhou", VX (4, 789), VX_MASK, PPCSPE, 0, {RS, EVUIMM_4, RA}}, RA 3453 arch/powerpc/xmon/ppc-opc.c {"evlwhosx", VX (4, 790), VX_MASK, PPCSPE, 0, {RS, RA, RB}}, RA 3454 arch/powerpc/xmon/ppc-opc.c {"evlwhos", VX (4, 791), VX_MASK, PPCSPE, 0, {RS, EVUIMM_4, RA}}, RA 3455 arch/powerpc/xmon/ppc-opc.c {"maclhwu", XO (4, 396,0,0),XO_MASK, MULHW, 0, {RT, RA, RB}}, RA 3456 arch/powerpc/xmon/ppc-opc.c {"evlwwsplatx", VX (4, 792), VX_MASK, PPCSPE, 0, {RS, RA, RB}}, RA 3457 arch/powerpc/xmon/ppc-opc.c {"maclhwu.", XO (4, 396,0,1),XO_MASK, MULHW, 0, {RT, RA, RB}}, RA 3458 arch/powerpc/xmon/ppc-opc.c {"evlwwsplat", VX (4, 793), VX_MASK, PPCSPE, 0, {RS, EVUIMM_4, RA}}, RA 3459 arch/powerpc/xmon/ppc-opc.c {"evlwhsplatx", VX (4, 796), VX_MASK, PPCSPE, 0, {RS, RA, RB}}, RA 3460 arch/powerpc/xmon/ppc-opc.c {"evlwhsplat", VX (4, 797), VX_MASK, PPCSPE, 0, {RS, EVUIMM_4, RA}}, RA 3461 arch/powerpc/xmon/ppc-opc.c {"evstddx", VX (4, 800), VX_MASK, PPCSPE, 0, {RS, RA, RB}}, RA 3462 arch/powerpc/xmon/ppc-opc.c {"evstdd", VX (4, 801), VX_MASK, PPCSPE, 0, {RS, EVUIMM_8, RA}}, RA 3463 arch/powerpc/xmon/ppc-opc.c {"evstdwx", VX (4, 802), VX_MASK, PPCSPE, 0, {RS, RA, RB}}, RA 3464 arch/powerpc/xmon/ppc-opc.c {"evstdw", VX (4, 803), VX_MASK, PPCSPE, 0, {RS, EVUIMM_8, RA}}, RA 3465 arch/powerpc/xmon/ppc-opc.c {"evstdhx", VX (4, 804), VX_MASK, PPCSPE, 0, {RS, RA, RB}}, RA 3466 arch/powerpc/xmon/ppc-opc.c {"evstdh", VX (4, 805), VX_MASK, PPCSPE, 0, {RS, EVUIMM_8, RA}}, RA 3467 arch/powerpc/xmon/ppc-opc.c {"evstwhex", VX (4, 816), VX_MASK, PPCSPE, 0, {RS, RA, RB}}, RA 3468 arch/powerpc/xmon/ppc-opc.c {"evstwhe", VX (4, 817), VX_MASK, PPCSPE, 0, {RS, EVUIMM_4, RA}}, RA 3469 arch/powerpc/xmon/ppc-opc.c {"evstwhox", VX (4, 820), VX_MASK, PPCSPE, 0, {RS, RA, RB}}, RA 3470 arch/powerpc/xmon/ppc-opc.c {"evstwho", VX (4, 821), VX_MASK, PPCSPE, 0, {RS, EVUIMM_4, RA}}, RA 3471 arch/powerpc/xmon/ppc-opc.c {"evstwwex", VX (4, 824), VX_MASK, PPCSPE, 0, {RS, RA, RB}}, RA 3472 arch/powerpc/xmon/ppc-opc.c {"evstwwe", VX (4, 825), VX_MASK, PPCSPE, 0, {RS, EVUIMM_4, RA}}, RA 3473 arch/powerpc/xmon/ppc-opc.c {"evstwwox", VX (4, 828), VX_MASK, PPCSPE, 0, {RS, RA, RB}}, RA 3474 arch/powerpc/xmon/ppc-opc.c {"evstwwo", VX (4, 829), VX_MASK, PPCSPE, 0, {RS, EVUIMM_4, RA}}, RA 3486 arch/powerpc/xmon/ppc-opc.c {"mullhw", XRC(4, 424,0), X_MASK, MULHW, 0, {RT, RA, RB}}, RA 3487 arch/powerpc/xmon/ppc-opc.c {"mullhw.", XRC(4, 424,1), X_MASK, MULHW, 0, {RT, RA, RB}}, RA 3488 arch/powerpc/xmon/ppc-opc.c {"maclhw", XO (4, 428,0,0),XO_MASK, MULHW, 0, {RT, RA, RB}}, RA 3489 arch/powerpc/xmon/ppc-opc.c {"maclhw.", XO (4, 428,0,1),XO_MASK, MULHW, 0, {RT, RA, RB}}, RA 3490 arch/powerpc/xmon/ppc-opc.c {"nmaclhw", XO (4, 430,0,0),XO_MASK, MULHW, 0, {RT, RA, RB}}, RA 3491 arch/powerpc/xmon/ppc-opc.c {"nmaclhw.", XO (4, 430,0,1),XO_MASK, MULHW, 0, {RT, RA, RB}}, RA 3501 arch/powerpc/xmon/ppc-opc.c {"maclhwsu", XO (4, 460,0,0), XO_MASK, MULHW, 0, {RT, RA, RB}}, RA 3502 arch/powerpc/xmon/ppc-opc.c {"maclhwsu.", XO (4, 460,0,1), XO_MASK, MULHW, 0, {RT, RA, RB}}, RA 3511 arch/powerpc/xmon/ppc-opc.c {"maclhws", XO (4, 492,0,0), XO_MASK, MULHW, 0, {RT, RA, RB}}, RA 3512 arch/powerpc/xmon/ppc-opc.c {"maclhws.", XO (4, 492,0,1), XO_MASK, MULHW, 0, {RT, RA, RB}}, RA 3513 arch/powerpc/xmon/ppc-opc.c {"nmaclhws", XO (4, 494,0,0), XO_MASK, MULHW, 0, {RT, RA, RB}}, RA 3514 arch/powerpc/xmon/ppc-opc.c {"nmaclhws.", XO (4, 494,0,1), XO_MASK, MULHW, 0, {RT, RA, RB}}, RA 3519 arch/powerpc/xmon/ppc-opc.c {"evmhessf", VX (4,1027), VX_MASK, PPCSPE, 0, {RS, RA, RB}}, RA 3525 arch/powerpc/xmon/ppc-opc.c {"evmhossf", VX (4,1031), VX_MASK, PPCSPE, 0, {RS, RA, RB}}, RA 3527 arch/powerpc/xmon/ppc-opc.c {"evmheumi", VX (4,1032), VX_MASK, PPCSPE, 0, {RS, RA, RB}}, RA 3528 arch/powerpc/xmon/ppc-opc.c {"evmhesmi", VX (4,1033), VX_MASK, PPCSPE, 0, {RS, RA, RB}}, RA 3530 arch/powerpc/xmon/ppc-opc.c {"evmhesmf", VX (4,1035), VX_MASK, PPCSPE, 0, {RS, RA, RB}}, RA 3531 arch/powerpc/xmon/ppc-opc.c {"evmhoumi", VX (4,1036), VX_MASK, PPCSPE, 0, {RS, RA, RB}}, RA 3533 arch/powerpc/xmon/ppc-opc.c {"evmhosmi", VX (4,1037), VX_MASK, PPCSPE, 0, {RS, RA, RB}}, RA 3534 arch/powerpc/xmon/ppc-opc.c {"evmhosmf", VX (4,1039), VX_MASK, PPCSPE, 0, {RS, RA, RB}}, RA 3535 arch/powerpc/xmon/ppc-opc.c {"machhwuo", XO (4, 12,1,0), XO_MASK, MULHW, 0, {RT, RA, RB}}, RA 3536 arch/powerpc/xmon/ppc-opc.c {"machhwuo.", XO (4, 12,1,1), XO_MASK, MULHW, 0, {RT, RA, RB}}, RA 3539 arch/powerpc/xmon/ppc-opc.c {"evmhessfa", VX (4,1059), VX_MASK, PPCSPE, 0, {RS, RA, RB}}, RA 3540 arch/powerpc/xmon/ppc-opc.c {"evmhossfa", VX (4,1063), VX_MASK, PPCSPE, 0, {RS, RA, RB}}, RA 3541 arch/powerpc/xmon/ppc-opc.c {"evmheumia", VX (4,1064), VX_MASK, PPCSPE, 0, {RS, RA, RB}}, RA 3542 arch/powerpc/xmon/ppc-opc.c {"evmhesmia", VX (4,1065), VX_MASK, PPCSPE, 0, {RS, RA, RB}}, RA 3543 arch/powerpc/xmon/ppc-opc.c {"evmhesmfa", VX (4,1067), VX_MASK, PPCSPE, 0, {RS, RA, RB}}, RA 3544 arch/powerpc/xmon/ppc-opc.c {"evmhoumia", VX (4,1068), VX_MASK, PPCSPE, 0, {RS, RA, RB}}, RA 3545 arch/powerpc/xmon/ppc-opc.c {"evmhosmia", VX (4,1069), VX_MASK, PPCSPE, 0, {RS, RA, RB}}, RA 3546 arch/powerpc/xmon/ppc-opc.c {"evmhosmfa", VX (4,1071), VX_MASK, PPCSPE, 0, {RS, RA, RB}}, RA 3556 arch/powerpc/xmon/ppc-opc.c {"evmwhssf", VX (4,1095), VX_MASK, PPCSPE, 0, {RS, RA, RB}}, RA 3558 arch/powerpc/xmon/ppc-opc.c {"evmwlumi", VX (4,1096), VX_MASK, PPCSPE, 0, {RS, RA, RB}}, RA 3560 arch/powerpc/xmon/ppc-opc.c {"evmwhumi", VX (4,1100), VX_MASK, PPCSPE, 0, {RS, RA, RB}}, RA 3562 arch/powerpc/xmon/ppc-opc.c {"evmwhsmi", VX (4,1101), VX_MASK, PPCSPE, 0, {RS, RA, RB}}, RA 3564 arch/powerpc/xmon/ppc-opc.c {"evmwhsmf", VX (4,1103), VX_MASK, PPCSPE, 0, {RS, RA, RB}}, RA 3565 arch/powerpc/xmon/ppc-opc.c {"evmwssf", VX (4,1107), VX_MASK, PPCSPE, 0, {RS, RA, RB}}, RA 3566 arch/powerpc/xmon/ppc-opc.c {"machhwo", XO (4, 44,1,0), XO_MASK, MULHW, 0, {RT, RA, RB}}, RA 3567 arch/powerpc/xmon/ppc-opc.c {"evmwumi", VX (4,1112), VX_MASK, PPCSPE, 0, {RS, RA, RB}}, RA 3568 arch/powerpc/xmon/ppc-opc.c {"machhwo.", XO (4, 44,1,1), XO_MASK, MULHW, 0, {RT, RA, RB}}, RA 3569 arch/powerpc/xmon/ppc-opc.c {"evmwsmi", VX (4,1113), VX_MASK, PPCSPE, 0, {RS, RA, RB}}, RA 3570 arch/powerpc/xmon/ppc-opc.c {"evmwsmf", VX (4,1115), VX_MASK, PPCSPE, 0, {RS, RA, RB}}, RA 3571 arch/powerpc/xmon/ppc-opc.c {"nmachhwo", XO (4, 46,1,0), XO_MASK, MULHW, 0, {RT, RA, RB}}, RA 3572 arch/powerpc/xmon/ppc-opc.c {"nmachhwo.", XO (4, 46,1,1), XO_MASK, MULHW, 0, {RT, RA, RB}}, RA 3575 arch/powerpc/xmon/ppc-opc.c {"evmwhssfa", VX (4,1127), VX_MASK, PPCSPE, 0, {RS, RA, RB}}, RA 3576 arch/powerpc/xmon/ppc-opc.c {"evmwlumia", VX (4,1128), VX_MASK, PPCSPE, 0, {RS, RA, RB}}, RA 3577 arch/powerpc/xmon/ppc-opc.c {"evmwhumia", VX (4,1132), VX_MASK, PPCSPE, 0, {RS, RA, RB}}, RA 3578 arch/powerpc/xmon/ppc-opc.c {"evmwhsmia", VX (4,1133), VX_MASK, PPCSPE, 0, {RS, RA, RB}}, RA 3579 arch/powerpc/xmon/ppc-opc.c {"evmwhsmfa", VX (4,1135), VX_MASK, PPCSPE, 0, {RS, RA, RB}}, RA 3580 arch/powerpc/xmon/ppc-opc.c {"evmwssfa", VX (4,1139), VX_MASK, PPCSPE, 0, {RS, RA, RB}}, RA 3581 arch/powerpc/xmon/ppc-opc.c {"evmwumia", VX (4,1144), VX_MASK, PPCSPE, 0, {RS, RA, RB}}, RA 3582 arch/powerpc/xmon/ppc-opc.c {"evmwsmia", VX (4,1145), VX_MASK, PPCSPE, 0, {RS, RA, RB}}, RA 3583 arch/powerpc/xmon/ppc-opc.c {"evmwsmfa", VX (4,1147), VX_MASK, PPCSPE, 0, {RS, RA, RB}}, RA 3595 arch/powerpc/xmon/ppc-opc.c {"machhwsuo", XO (4, 76,1,0), XO_MASK, MULHW, 0, {RT, RA, RB}}, RA 3596 arch/powerpc/xmon/ppc-opc.c {"machhwsuo.", XO (4, 76,1,1), XO_MASK, MULHW, 0, {RT, RA, RB}}, RA 3600 arch/powerpc/xmon/ppc-opc.c {"evaddusiaaw", VX (4,1216), VX_MASK, PPCSPE, 0, {RS, RA}}, RA 3602 arch/powerpc/xmon/ppc-opc.c {"evaddssiaaw", VX (4,1217), VX_MASK, PPCSPE, 0, {RS, RA}}, RA 3603 arch/powerpc/xmon/ppc-opc.c {"evsubfusiaaw",VX (4,1218), VX_MASK, PPCSPE, 0, {RS, RA}}, RA 3604 arch/powerpc/xmon/ppc-opc.c {"evsubfssiaaw",VX (4,1219), VX_MASK, PPCSPE, 0, {RS, RA}}, RA 3605 arch/powerpc/xmon/ppc-opc.c {"evmra", VX (4,1220), VX_MASK, PPCSPE, 0, {RS, RA}}, RA 3607 arch/powerpc/xmon/ppc-opc.c {"evdivws", VX (4,1222), VX_MASK, PPCSPE, 0, {RS, RA, RB}}, RA 3612 arch/powerpc/xmon/ppc-opc.c {"evdivwu", VX (4,1223), VX_MASK, PPCSPE, 0, {RS, RA, RB}}, RA 3614 arch/powerpc/xmon/ppc-opc.c {"evaddumiaaw", VX (4,1224), VX_MASK, PPCSPE, 0, {RS, RA}}, RA 3615 arch/powerpc/xmon/ppc-opc.c {"evaddsmiaaw", VX (4,1225), VX_MASK, PPCSPE, 0, {RS, RA}}, RA 3616 arch/powerpc/xmon/ppc-opc.c {"evsubfumiaaw",VX (4,1226), VX_MASK, PPCSPE, 0, {RS, RA}}, RA 3617 arch/powerpc/xmon/ppc-opc.c {"evsubfsmiaaw",VX (4,1227), VX_MASK, PPCSPE, 0, {RS, RA}}, RA 3619 arch/powerpc/xmon/ppc-opc.c {"machhwso", XO (4, 108,1,0), XO_MASK, MULHW, 0, {RT, RA, RB}}, RA 3620 arch/powerpc/xmon/ppc-opc.c {"machhwso.", XO (4, 108,1,1), XO_MASK, MULHW, 0, {RT, RA, RB}}, RA 3621 arch/powerpc/xmon/ppc-opc.c {"nmachhwso", XO (4, 110,1,0), XO_MASK, MULHW, 0, {RT, RA, RB}}, RA 3622 arch/powerpc/xmon/ppc-opc.c {"nmachhwso.", XO (4, 110,1,1), XO_MASK, MULHW, 0, {RT, RA, RB}}, RA 3626 arch/powerpc/xmon/ppc-opc.c {"evmheusiaaw", VX (4,1280), VX_MASK, PPCSPE, 0, {RS, RA, RB}}, RA 3628 arch/powerpc/xmon/ppc-opc.c {"evmhessiaaw", VX (4,1281), VX_MASK, PPCSPE, 0, {RS, RA, RB}}, RA 3630 arch/powerpc/xmon/ppc-opc.c {"evmhessfaaw", VX (4,1283), VX_MASK, PPCSPE, 0, {RS, RA, RB}}, RA 3631 arch/powerpc/xmon/ppc-opc.c {"evmhousiaaw", VX (4,1284), VX_MASK, PPCSPE, 0, {RS, RA, RB}}, RA 3634 arch/powerpc/xmon/ppc-opc.c {"evmhossiaaw", VX (4,1285), VX_MASK, PPCSPE, 0, {RS, RA, RB}}, RA 3638 arch/powerpc/xmon/ppc-opc.c {"evmhossfaaw", VX (4,1287), VX_MASK, PPCSPE, 0, {RS, RA, RB}}, RA 3639 arch/powerpc/xmon/ppc-opc.c {"evmheumiaaw", VX (4,1288), VX_MASK, PPCSPE, 0, {RS, RA, RB}}, RA 3642 arch/powerpc/xmon/ppc-opc.c {"evmhesmiaaw", VX (4,1289), VX_MASK, PPCSPE, 0, {RS, RA, RB}}, RA 3643 arch/powerpc/xmon/ppc-opc.c {"evmhesmfaaw", VX (4,1291), VX_MASK, PPCSPE, 0, {RS, RA, RB}}, RA 3645 arch/powerpc/xmon/ppc-opc.c {"evmhoumiaaw", VX (4,1292), VX_MASK, PPCSPE, 0, {RS, RA, RB}}, RA 3646 arch/powerpc/xmon/ppc-opc.c {"evmhosmiaaw", VX (4,1293), VX_MASK, PPCSPE, 0, {RS, RA, RB}}, RA 3647 arch/powerpc/xmon/ppc-opc.c {"evmhosmfaaw", VX (4,1295), VX_MASK, PPCSPE, 0, {RS, RA, RB}}, RA 3648 arch/powerpc/xmon/ppc-opc.c {"macchwuo", XO (4, 140,1,0), XO_MASK, MULHW, 0, {RT, RA, RB}}, RA 3649 arch/powerpc/xmon/ppc-opc.c {"macchwuo.", XO (4, 140,1,1), XO_MASK, MULHW, 0, {RT, RA, RB}}, RA 3650 arch/powerpc/xmon/ppc-opc.c {"evmhegumiaa", VX (4,1320), VX_MASK, PPCSPE, 0, {RS, RA, RB}}, RA 3651 arch/powerpc/xmon/ppc-opc.c {"evmhegsmiaa", VX (4,1321), VX_MASK, PPCSPE, 0, {RS, RA, RB}}, RA 3652 arch/powerpc/xmon/ppc-opc.c {"evmhegsmfaa", VX (4,1323), VX_MASK, PPCSPE, 0, {RS, RA, RB}}, RA 3653 arch/powerpc/xmon/ppc-opc.c {"evmhogumiaa", VX (4,1324), VX_MASK, PPCSPE, 0, {RS, RA, RB}}, RA 3654 arch/powerpc/xmon/ppc-opc.c {"evmhogsmiaa", VX (4,1325), VX_MASK, PPCSPE, 0, {RS, RA, RB}}, RA 3655 arch/powerpc/xmon/ppc-opc.c {"evmhogsmfaa", VX (4,1327), VX_MASK, PPCSPE, 0, {RS, RA, RB}}, RA 3657 arch/powerpc/xmon/ppc-opc.c {"evmwlusiaaw", VX (4,1344), VX_MASK, PPCSPE, 0, {RS, RA, RB}}, RA 3659 arch/powerpc/xmon/ppc-opc.c {"evmwlssiaaw", VX (4,1345), VX_MASK, PPCSPE, 0, {RS, RA, RB}}, RA 3666 arch/powerpc/xmon/ppc-opc.c {"evmwlumiaaw", VX (4,1352), VX_MASK, PPCSPE, 0, {RS, RA, RB}}, RA 3668 arch/powerpc/xmon/ppc-opc.c {"evmwlsmiaaw", VX (4,1353), VX_MASK, PPCSPE, 0, {RS, RA, RB}}, RA 3671 arch/powerpc/xmon/ppc-opc.c {"evmwssfaa", VX (4,1363), VX_MASK, PPCSPE, 0, {RS, RA, RB}}, RA 3672 arch/powerpc/xmon/ppc-opc.c {"macchwo", XO (4, 172,1,0), XO_MASK, MULHW, 0, {RT, RA, RB}}, RA 3673 arch/powerpc/xmon/ppc-opc.c {"evmwumiaa", VX (4,1368), VX_MASK, PPCSPE, 0, {RS, RA, RB}}, RA 3674 arch/powerpc/xmon/ppc-opc.c {"macchwo.", XO (4, 172,1,1), XO_MASK, MULHW, 0, {RT, RA, RB}}, RA 3675 arch/powerpc/xmon/ppc-opc.c {"evmwsmiaa", VX (4,1369), VX_MASK, PPCSPE, 0, {RS, RA, RB}}, RA 3676 arch/powerpc/xmon/ppc-opc.c {"evmwsmfaa", VX (4,1371), VX_MASK, PPCSPE, 0, {RS, RA, RB}}, RA 3677 arch/powerpc/xmon/ppc-opc.c {"nmacchwo", XO (4, 174,1,0), XO_MASK, MULHW, 0, {RT, RA, RB}}, RA 3678 arch/powerpc/xmon/ppc-opc.c {"nmacchwo.", XO (4, 174,1,1), XO_MASK, MULHW, 0, {RT, RA, RB}}, RA 3679 arch/powerpc/xmon/ppc-opc.c {"evmheusianw", VX (4,1408), VX_MASK, PPCSPE, 0, {RS, RA, RB}}, RA 3681 arch/powerpc/xmon/ppc-opc.c {"evmhessianw", VX (4,1409), VX_MASK, PPCSPE, 0, {RS, RA, RB}}, RA 3690 arch/powerpc/xmon/ppc-opc.c {"evmhessfanw", VX (4,1411), VX_MASK, PPCSPE, 0, {RS, RA, RB}}, RA 3692 arch/powerpc/xmon/ppc-opc.c {"evmhousianw", VX (4,1412), VX_MASK, PPCSPE, 0, {RS, RA, RB}}, RA 3693 arch/powerpc/xmon/ppc-opc.c {"evmhossianw", VX (4,1413), VX_MASK, PPCSPE, 0, {RS, RA, RB}}, RA 3697 arch/powerpc/xmon/ppc-opc.c {"evmhossfanw", VX (4,1415), VX_MASK, PPCSPE, 0, {RS, RA, RB}}, RA 3698 arch/powerpc/xmon/ppc-opc.c {"evmheumianw", VX (4,1416), VX_MASK, PPCSPE, 0, {RS, RA, RB}}, RA 3699 arch/powerpc/xmon/ppc-opc.c {"evmhesmianw", VX (4,1417), VX_MASK, PPCSPE, 0, {RS, RA, RB}}, RA 3700 arch/powerpc/xmon/ppc-opc.c {"evmhesmfanw", VX (4,1419), VX_MASK, PPCSPE, 0, {RS, RA, RB}}, RA 3701 arch/powerpc/xmon/ppc-opc.c {"evmhoumianw", VX (4,1420), VX_MASK, PPCSPE, 0, {RS, RA, RB}}, RA 3702 arch/powerpc/xmon/ppc-opc.c {"evmhosmianw", VX (4,1421), VX_MASK, PPCSPE, 0, {RS, RA, RB}}, RA 3703 arch/powerpc/xmon/ppc-opc.c {"evmhosmfanw", VX (4,1423), VX_MASK, PPCSPE, 0, {RS, RA, RB}}, RA 3704 arch/powerpc/xmon/ppc-opc.c {"macchwsuo", XO (4, 204,1,0), XO_MASK, MULHW, 0, {RT, RA, RB}}, RA 3705 arch/powerpc/xmon/ppc-opc.c {"macchwsuo.", XO (4, 204,1,1), XO_MASK, MULHW, 0, {RT, RA, RB}}, RA 3706 arch/powerpc/xmon/ppc-opc.c {"evmhegumian", VX (4,1448), VX_MASK, PPCSPE, 0, {RS, RA, RB}}, RA 3707 arch/powerpc/xmon/ppc-opc.c {"evmhegsmian", VX (4,1449), VX_MASK, PPCSPE, 0, {RS, RA, RB}}, RA 3708 arch/powerpc/xmon/ppc-opc.c {"evmhegsmfan", VX (4,1451), VX_MASK, PPCSPE, 0, {RS, RA, RB}}, RA 3709 arch/powerpc/xmon/ppc-opc.c {"evmhogumian", VX (4,1452), VX_MASK, PPCSPE, 0, {RS, RA, RB}}, RA 3710 arch/powerpc/xmon/ppc-opc.c {"evmhogsmian", VX (4,1453), VX_MASK, PPCSPE, 0, {RS, RA, RB}}, RA 3711 arch/powerpc/xmon/ppc-opc.c {"evmhogsmfan", VX (4,1455), VX_MASK, PPCSPE, 0, {RS, RA, RB}}, RA 3712 arch/powerpc/xmon/ppc-opc.c {"evmwlusianw", VX (4,1472), VX_MASK, PPCSPE, 0, {RS, RA, RB}}, RA 3714 arch/powerpc/xmon/ppc-opc.c {"evmwlssianw", VX (4,1473), VX_MASK, PPCSPE, 0, {RS, RA, RB}}, RA 3720 arch/powerpc/xmon/ppc-opc.c {"evmwlumianw", VX (4,1480), VX_MASK, PPCSPE, 0, {RS, RA, RB}}, RA 3721 arch/powerpc/xmon/ppc-opc.c {"evmwlsmianw", VX (4,1481), VX_MASK, PPCSPE, 0, {RS, RA, RB}}, RA 3724 arch/powerpc/xmon/ppc-opc.c {"evmwssfan", VX (4,1491), VX_MASK, PPCSPE, 0, {RS, RA, RB}}, RA 3725 arch/powerpc/xmon/ppc-opc.c {"macchwso", XO (4, 236,1,0), XO_MASK, MULHW, 0, {RT, RA, RB}}, RA 3726 arch/powerpc/xmon/ppc-opc.c {"evmwumian", VX (4,1496), VX_MASK, PPCSPE, 0, {RS, RA, RB}}, RA 3727 arch/powerpc/xmon/ppc-opc.c {"macchwso.", XO (4, 236,1,1), XO_MASK, MULHW, 0, {RT, RA, RB}}, RA 3728 arch/powerpc/xmon/ppc-opc.c {"evmwsmian", VX (4,1497), VX_MASK, PPCSPE, 0, {RS, RA, RB}}, RA 3729 arch/powerpc/xmon/ppc-opc.c {"evmwsmfan", VX (4,1499), VX_MASK, PPCSPE, 0, {RS, RA, RB}}, RA 3730 arch/powerpc/xmon/ppc-opc.c {"nmacchwso", XO (4, 238,1,0), XO_MASK, MULHW, 0, {RT, RA, RB}}, RA 3731 arch/powerpc/xmon/ppc-opc.c {"nmacchwso.", XO (4, 238,1,1), XO_MASK, MULHW, 0, {RT, RA, RB}}, RA 3754 arch/powerpc/xmon/ppc-opc.c {"vextublx", VX (4,1549), VX_MASK, PPCVEC3, 0, {RT, RA, VB}}, RA 3761 arch/powerpc/xmon/ppc-opc.c {"vextuhlx", VX (4,1613), VX_MASK, PPCVEC3, 0, {RT, RA, VB}}, RA 3771 arch/powerpc/xmon/ppc-opc.c {"vextuwlx", VX (4,1677), VX_MASK, PPCVEC3, 0, {RT, RA, VB}}, RA 3787 arch/powerpc/xmon/ppc-opc.c {"vextubrx", VX (4,1805), VX_MASK, PPCVEC3, 0, {RT, RA, VB}}, RA 3788 arch/powerpc/xmon/ppc-opc.c {"maclhwuo", XO (4, 396,1,0), XO_MASK, MULHW, 0, {RT, RA, RB}}, RA 3789 arch/powerpc/xmon/ppc-opc.c {"maclhwuo.", XO (4, 396,1,1), XO_MASK, MULHW, 0, {RT, RA, RB}}, RA 3795 arch/powerpc/xmon/ppc-opc.c {"vextuhrx", VX (4,1869), VX_MASK, PPCVEC3, 0, {RT, RA, VB}}, RA 3798 arch/powerpc/xmon/ppc-opc.c {"maclhwo", XO (4, 428,1,0), XO_MASK, MULHW, 0, {RT, RA, RB}}, RA 3799 arch/powerpc/xmon/ppc-opc.c {"maclhwo.", XO (4, 428,1,1), XO_MASK, MULHW, 0, {RT, RA, RB}}, RA 3800 arch/powerpc/xmon/ppc-opc.c {"nmaclhwo", XO (4, 430,1,0), XO_MASK, MULHW, 0, {RT, RA, RB}}, RA 3801 arch/powerpc/xmon/ppc-opc.c {"nmaclhwo.", XO (4, 430,1,1), XO_MASK, MULHW, 0, {RT, RA, RB}}, RA 3810 arch/powerpc/xmon/ppc-opc.c {"vextuwrx", VX (4,1933), VX_MASK, PPCVEC3, 0, {RT, RA, VB}}, RA 3811 arch/powerpc/xmon/ppc-opc.c {"maclhwsuo", XO (4, 460,1,0), XO_MASK, MULHW, 0, {RT, RA, RB}}, RA 3812 arch/powerpc/xmon/ppc-opc.c {"maclhwsuo.", XO (4, 460,1,1), XO_MASK, MULHW, 0, {RT, RA, RB}}, RA 3819 arch/powerpc/xmon/ppc-opc.c {"maclhwso", XO (4, 492,1,0), XO_MASK, MULHW, 0, {RT, RA, RB}}, RA 3820 arch/powerpc/xmon/ppc-opc.c {"maclhwso.", XO (4, 492,1,1), XO_MASK, MULHW, 0, {RT, RA, RB}}, RA 3821 arch/powerpc/xmon/ppc-opc.c {"nmaclhwso", XO (4, 494,1,0), XO_MASK, MULHW, 0, {RT, RA, RB}}, RA 3822 arch/powerpc/xmon/ppc-opc.c {"nmaclhwso.", XO (4, 494,1,1), XO_MASK, MULHW, 0, {RT, RA, RB}}, RA 3823 arch/powerpc/xmon/ppc-opc.c {"dcbz_l", X (4,1014), XRT_MASK, PPCPS, 0, {RA, RB}}, RA 3825 arch/powerpc/xmon/ppc-opc.c {"mulli", OP(7), OP_MASK, PPCCOM, PPCVLE, {RT, RA, SI}}, RA 3826 arch/powerpc/xmon/ppc-opc.c {"muli", OP(7), OP_MASK, PWRCOM, PPCVLE, {RT, RA, SI}}, RA 3828 arch/powerpc/xmon/ppc-opc.c {"subfic", OP(8), OP_MASK, PPCCOM, PPCVLE, {RT, RA, SI}}, RA 3829 arch/powerpc/xmon/ppc-opc.c {"sfi", OP(8), OP_MASK, PWRCOM, PPCVLE, {RT, RA, SI}}, RA 3831 arch/powerpc/xmon/ppc-opc.c {"dozi", OP(9), OP_MASK, M601, PPCVLE, {RT, RA, SI}}, RA 3833 arch/powerpc/xmon/ppc-opc.c {"cmplwi", OPL(10,0), OPL_MASK, PPCCOM, PPCVLE, {OBF, RA, UISIGNOPT}}, RA 3834 arch/powerpc/xmon/ppc-opc.c {"cmpldi", OPL(10,1), OPL_MASK, PPC64, PPCVLE, {OBF, RA, UISIGNOPT}}, RA 3835 arch/powerpc/xmon/ppc-opc.c {"cmpli", OP(10), OP_MASK, PPC, PPCVLE, {BF, L32OPT, RA, UISIGNOPT}}, RA 3836 arch/powerpc/xmon/ppc-opc.c {"cmpli", OP(10), OP_MASK, PWRCOM, PPC|PPCVLE, {BF, RA, UISIGNOPT}}, RA 3838 arch/powerpc/xmon/ppc-opc.c {"cmpwi", OPL(11,0), OPL_MASK, PPCCOM, PPCVLE, {OBF, RA, SI}}, RA 3839 arch/powerpc/xmon/ppc-opc.c {"cmpdi", OPL(11,1), OPL_MASK, PPC64, PPCVLE, {OBF, RA, SI}}, RA 3840 arch/powerpc/xmon/ppc-opc.c {"cmpi", OP(11), OP_MASK, PPC, PPCVLE, {BF, L32OPT, RA, SI}}, RA 3841 arch/powerpc/xmon/ppc-opc.c {"cmpi", OP(11), OP_MASK, PWRCOM, PPC|PPCVLE, {BF, RA, SI}}, RA 3843 arch/powerpc/xmon/ppc-opc.c {"addic", OP(12), OP_MASK, PPCCOM, PPCVLE, {RT, RA, SI}}, RA 3844 arch/powerpc/xmon/ppc-opc.c {"ai", OP(12), OP_MASK, PWRCOM, PPCVLE, {RT, RA, SI}}, RA 3845 arch/powerpc/xmon/ppc-opc.c {"subic", OP(12), OP_MASK, PPCCOM, PPCVLE, {RT, RA, NSI}}, RA 3847 arch/powerpc/xmon/ppc-opc.c {"addic.", OP(13), OP_MASK, PPCCOM, PPCVLE, {RT, RA, SI}}, RA 3848 arch/powerpc/xmon/ppc-opc.c {"ai.", OP(13), OP_MASK, PWRCOM, PPCVLE, {RT, RA, SI}}, RA 3849 arch/powerpc/xmon/ppc-opc.c {"subic.", OP(13), OP_MASK, PPCCOM, PPCVLE, {RT, RA, NSI}}, RA 4587 arch/powerpc/xmon/ppc-opc.c {"rlwimi", M(20,0), M_MASK, PPCCOM, PPCVLE, {RA, RS, SH, MBE, ME}}, RA 4588 arch/powerpc/xmon/ppc-opc.c {"rlimi", M(20,0), M_MASK, PWRCOM, PPCVLE, {RA, RS, SH, MBE, ME}}, RA 4590 arch/powerpc/xmon/ppc-opc.c {"rlwimi.", M(20,1), M_MASK, PPCCOM, PPCVLE, {RA, RS, SH, MBE, ME}}, RA 4591 arch/powerpc/xmon/ppc-opc.c {"rlimi.", M(20,1), M_MASK, PWRCOM, PPCVLE, {RA, RS, SH, MBE, ME}}, RA 4593 arch/powerpc/xmon/ppc-opc.c {"rotlwi", MME(21,31,0), MMBME_MASK, PPCCOM, PPCVLE, {RA, RS, SH}}, RA 4594 arch/powerpc/xmon/ppc-opc.c {"clrlwi", MME(21,31,0), MSHME_MASK, PPCCOM, PPCVLE, {RA, RS, MB}}, RA 4595 arch/powerpc/xmon/ppc-opc.c {"rlwinm", M(21,0), M_MASK, PPCCOM, PPCVLE, {RA, RS, SH, MBE, ME}}, RA 4596 arch/powerpc/xmon/ppc-opc.c {"rlinm", M(21,0), M_MASK, PWRCOM, PPCVLE, {RA, RS, SH, MBE, ME}}, RA 4597 arch/powerpc/xmon/ppc-opc.c {"rotlwi.", MME(21,31,1), MMBME_MASK, PPCCOM, PPCVLE, {RA, RS, SH}}, RA 4598 arch/powerpc/xmon/ppc-opc.c {"clrlwi.", MME(21,31,1), MSHME_MASK, PPCCOM, PPCVLE, {RA, RS, MB}}, RA 4599 arch/powerpc/xmon/ppc-opc.c {"rlwinm.", M(21,1), M_MASK, PPCCOM, PPCVLE, {RA, RS, SH, MBE, ME}}, RA 4600 arch/powerpc/xmon/ppc-opc.c {"rlinm.", M(21,1), M_MASK, PWRCOM, PPCVLE, {RA, RS, SH, MBE, ME}}, RA 4602 arch/powerpc/xmon/ppc-opc.c {"rlmi", M(22,0), M_MASK, M601, PPCVLE, {RA, RS, RB, MBE, ME}}, RA 4603 arch/powerpc/xmon/ppc-opc.c {"rlmi.", M(22,1), M_MASK, M601, PPCVLE, {RA, RS, RB, MBE, ME}}, RA 4605 arch/powerpc/xmon/ppc-opc.c {"rotlw", MME(23,31,0), MMBME_MASK, PPCCOM, PPCVLE, {RA, RS, RB}}, RA 4606 arch/powerpc/xmon/ppc-opc.c {"rlwnm", M(23,0), M_MASK, PPCCOM, PPCVLE, {RA, RS, RB, MBE, ME}}, RA 4607 arch/powerpc/xmon/ppc-opc.c {"rlnm", M(23,0), M_MASK, PWRCOM, PPCVLE, {RA, RS, RB, MBE, ME}}, RA 4608 arch/powerpc/xmon/ppc-opc.c {"rotlw.", MME(23,31,1), MMBME_MASK, PPCCOM, PPCVLE, {RA, RS, RB}}, RA 4609 arch/powerpc/xmon/ppc-opc.c {"rlwnm.", M(23,1), M_MASK, PPCCOM, PPCVLE, {RA, RS, RB, MBE, ME}}, RA 4610 arch/powerpc/xmon/ppc-opc.c {"rlnm.", M(23,1), M_MASK, PWRCOM, PPCVLE, {RA, RS, RB, MBE, ME}}, RA 4613 arch/powerpc/xmon/ppc-opc.c {"ori", OP(24), OP_MASK, PPCCOM, PPCVLE, {RA, RS, UI}}, RA 4614 arch/powerpc/xmon/ppc-opc.c {"oril", OP(24), OP_MASK, PWRCOM, PPCVLE, {RA, RS, UI}}, RA 4616 arch/powerpc/xmon/ppc-opc.c {"oris", OP(25), OP_MASK, PPCCOM, PPCVLE, {RA, RS, UI}}, RA 4617 arch/powerpc/xmon/ppc-opc.c {"oriu", OP(25), OP_MASK, PWRCOM, PPCVLE, {RA, RS, UI}}, RA 4620 arch/powerpc/xmon/ppc-opc.c {"xori", OP(26), OP_MASK, PPCCOM, PPCVLE, {RA, RS, UI}}, RA 4621 arch/powerpc/xmon/ppc-opc.c {"xoril", OP(26), OP_MASK, PWRCOM, PPCVLE, {RA, RS, UI}}, RA 4623 arch/powerpc/xmon/ppc-opc.c {"xoris", OP(27), OP_MASK, PPCCOM, PPCVLE, {RA, RS, UI}}, RA 4624 arch/powerpc/xmon/ppc-opc.c {"xoriu", OP(27), OP_MASK, PWRCOM, PPCVLE, {RA, RS, UI}}, RA 4626 arch/powerpc/xmon/ppc-opc.c {"andi.", OP(28), OP_MASK, PPCCOM, PPCVLE, {RA, RS, UI}}, RA 4627 arch/powerpc/xmon/ppc-opc.c {"andil.", OP(28), OP_MASK, PWRCOM, PPCVLE, {RA, RS, UI}}, RA 4629 arch/powerpc/xmon/ppc-opc.c {"andis.", OP(29), OP_MASK, PPCCOM, PPCVLE, {RA, RS, UI}}, RA 4630 arch/powerpc/xmon/ppc-opc.c {"andiu.", OP(29), OP_MASK, PWRCOM, PPCVLE, {RA, RS, UI}}, RA 4632 arch/powerpc/xmon/ppc-opc.c {"rotldi", MD(30,0,0), MDMB_MASK, PPC64, PPCVLE, {RA, RS, SH6}}, RA 4633 arch/powerpc/xmon/ppc-opc.c {"clrldi", MD(30,0,0), MDSH_MASK, PPC64, PPCVLE, {RA, RS, MB6}}, RA 4634 arch/powerpc/xmon/ppc-opc.c {"rldicl", MD(30,0,0), MD_MASK, PPC64, PPCVLE, {RA, RS, SH6, MB6}}, RA 4635 arch/powerpc/xmon/ppc-opc.c {"rotldi.", MD(30,0,1), MDMB_MASK, PPC64, PPCVLE, {RA, RS, SH6}}, RA 4636 arch/powerpc/xmon/ppc-opc.c {"clrldi.", MD(30,0,1), MDSH_MASK, PPC64, PPCVLE, {RA, RS, MB6}}, RA 4637 arch/powerpc/xmon/ppc-opc.c {"rldicl.", MD(30,0,1), MD_MASK, PPC64, PPCVLE, {RA, RS, SH6, MB6}}, RA 4639 arch/powerpc/xmon/ppc-opc.c {"rldicr", MD(30,1,0), MD_MASK, PPC64, PPCVLE, {RA, RS, SH6, ME6}}, RA 4640 arch/powerpc/xmon/ppc-opc.c {"rldicr.", MD(30,1,1), MD_MASK, PPC64, PPCVLE, {RA, RS, SH6, ME6}}, RA 4642 arch/powerpc/xmon/ppc-opc.c {"rldic", MD(30,2,0), MD_MASK, PPC64, PPCVLE, {RA, RS, SH6, MB6}}, RA 4643 arch/powerpc/xmon/ppc-opc.c {"rldic.", MD(30,2,1), MD_MASK, PPC64, PPCVLE, {RA, RS, SH6, MB6}}, RA 4645 arch/powerpc/xmon/ppc-opc.c {"rldimi", MD(30,3,0), MD_MASK, PPC64, PPCVLE, {RA, RS, SH6, MB6}}, RA 4646 arch/powerpc/xmon/ppc-opc.c {"rldimi.", MD(30,3,1), MD_MASK, PPC64, PPCVLE, {RA, RS, SH6, MB6}}, RA 4648 arch/powerpc/xmon/ppc-opc.c {"rotld", MDS(30,8,0), MDSMB_MASK, PPC64, PPCVLE, {RA, RS, RB}}, RA 4649 arch/powerpc/xmon/ppc-opc.c {"rldcl", MDS(30,8,0), MDS_MASK, PPC64, PPCVLE, {RA, RS, RB, MB6}}, RA 4650 arch/powerpc/xmon/ppc-opc.c {"rotld.", MDS(30,8,1), MDSMB_MASK, PPC64, PPCVLE, {RA, RS, RB}}, RA 4651 arch/powerpc/xmon/ppc-opc.c {"rldcl.", MDS(30,8,1), MDS_MASK, PPC64, PPCVLE, {RA, RS, RB, MB6}}, RA 4653 arch/powerpc/xmon/ppc-opc.c {"rldcr", MDS(30,9,0), MDS_MASK, PPC64, PPCVLE, {RA, RS, RB, ME6}}, RA 4654 arch/powerpc/xmon/ppc-opc.c {"rldcr.", MDS(30,9,1), MDS_MASK, PPC64, PPCVLE, {RA, RS, RB, ME6}}, RA 4656 arch/powerpc/xmon/ppc-opc.c {"cmpw", XOPL(31,0,0), XCMPL_MASK, PPCCOM, 0, {OBF, RA, RB}}, RA 4657 arch/powerpc/xmon/ppc-opc.c {"cmpd", XOPL(31,0,1), XCMPL_MASK, PPC64, 0, {OBF, RA, RB}}, RA 4658 arch/powerpc/xmon/ppc-opc.c {"cmp", X(31,0), XCMP_MASK, PPC, 0, {BF, L32OPT, RA, RB}}, RA 4659 arch/powerpc/xmon/ppc-opc.c {"cmp", X(31,0), XCMPL_MASK, PWRCOM, PPC, {BF, RA, RB}}, RA 4661 arch/powerpc/xmon/ppc-opc.c {"twlgt", XTO(31,4,TOLGT), XTO_MASK, PPCCOM, 0, {RA, RB}}, RA 4662 arch/powerpc/xmon/ppc-opc.c {"tlgt", XTO(31,4,TOLGT), XTO_MASK, PWRCOM, 0, {RA, RB}}, RA 4663 arch/powerpc/xmon/ppc-opc.c {"twllt", XTO(31,4,TOLLT), XTO_MASK, PPCCOM, 0, {RA, RB}}, RA 4664 arch/powerpc/xmon/ppc-opc.c {"tllt", XTO(31,4,TOLLT), XTO_MASK, PWRCOM, 0, {RA, RB}}, RA 4665 arch/powerpc/xmon/ppc-opc.c {"tweq", XTO(31,4,TOEQ), XTO_MASK, PPCCOM, 0, {RA, RB}}, RA 4666 arch/powerpc/xmon/ppc-opc.c {"teq", XTO(31,4,TOEQ), XTO_MASK, PWRCOM, 0, {RA, RB}}, RA 4667 arch/powerpc/xmon/ppc-opc.c {"twlge", XTO(31,4,TOLGE), XTO_MASK, PPCCOM, 0, {RA, RB}}, RA 4668 arch/powerpc/xmon/ppc-opc.c {"tlge", XTO(31,4,TOLGE), XTO_MASK, PWRCOM, 0, {RA, RB}}, RA 4669 arch/powerpc/xmon/ppc-opc.c {"twlnl", XTO(31,4,TOLNL), XTO_MASK, PPCCOM, 0, {RA, RB}}, RA 4670 arch/powerpc/xmon/ppc-opc.c {"tlnl", XTO(31,4,TOLNL), XTO_MASK, PWRCOM, 0, {RA, RB}}, RA 4671 arch/powerpc/xmon/ppc-opc.c {"twlle", XTO(31,4,TOLLE), XTO_MASK, PPCCOM, 0, {RA, RB}}, RA 4672 arch/powerpc/xmon/ppc-opc.c {"tlle", XTO(31,4,TOLLE), XTO_MASK, PWRCOM, 0, {RA, RB}}, RA 4673 arch/powerpc/xmon/ppc-opc.c {"twlng", XTO(31,4,TOLNG), XTO_MASK, PPCCOM, 0, {RA, RB}}, RA 4674 arch/powerpc/xmon/ppc-opc.c {"tlng", XTO(31,4,TOLNG), XTO_MASK, PWRCOM, 0, {RA, RB}}, RA 4675 arch/powerpc/xmon/ppc-opc.c {"twgt", XTO(31,4,TOGT), XTO_MASK, PPCCOM, 0, {RA, RB}}, RA 4676 arch/powerpc/xmon/ppc-opc.c {"tgt", XTO(31,4,TOGT), XTO_MASK, PWRCOM, 0, {RA, RB}}, RA 4677 arch/powerpc/xmon/ppc-opc.c {"twge", XTO(31,4,TOGE), XTO_MASK, PPCCOM, 0, {RA, RB}}, RA 4678 arch/powerpc/xmon/ppc-opc.c {"tge", XTO(31,4,TOGE), XTO_MASK, PWRCOM, 0, {RA, RB}}, RA 4679 arch/powerpc/xmon/ppc-opc.c {"twnl", XTO(31,4,TONL), XTO_MASK, PPCCOM, 0, {RA, RB}}, RA 4680 arch/powerpc/xmon/ppc-opc.c {"tnl", XTO(31,4,TONL), XTO_MASK, PWRCOM, 0, {RA, RB}}, RA 4681 arch/powerpc/xmon/ppc-opc.c {"twlt", XTO(31,4,TOLT), XTO_MASK, PPCCOM, 0, {RA, RB}}, RA 4682 arch/powerpc/xmon/ppc-opc.c {"tlt", XTO(31,4,TOLT), XTO_MASK, PWRCOM, 0, {RA, RB}}, RA 4683 arch/powerpc/xmon/ppc-opc.c {"twle", XTO(31,4,TOLE), XTO_MASK, PPCCOM, 0, {RA, RB}}, RA 4684 arch/powerpc/xmon/ppc-opc.c {"tle", XTO(31,4,TOLE), XTO_MASK, PWRCOM, 0, {RA, RB}}, RA 4685 arch/powerpc/xmon/ppc-opc.c {"twng", XTO(31,4,TONG), XTO_MASK, PPCCOM, 0, {RA, RB}}, RA 4686 arch/powerpc/xmon/ppc-opc.c {"tng", XTO(31,4,TONG), XTO_MASK, PWRCOM, 0, {RA, RB}}, RA 4687 arch/powerpc/xmon/ppc-opc.c {"twne", XTO(31,4,TONE), XTO_MASK, PPCCOM, 0, {RA, RB}}, RA 4688 arch/powerpc/xmon/ppc-opc.c {"tne", XTO(31,4,TONE), XTO_MASK, PWRCOM, 0, {RA, RB}}, RA 4690 arch/powerpc/xmon/ppc-opc.c {"twu", XTO(31,4,TOU), XTO_MASK, PPCCOM, 0, {RA, RB}}, RA 4691 arch/powerpc/xmon/ppc-opc.c {"tu", XTO(31,4,TOU), XTO_MASK, PWRCOM, 0, {RA, RB}}, RA 4692 arch/powerpc/xmon/ppc-opc.c {"tw", X(31,4), X_MASK, PPCCOM, 0, {TO, RA, RB}}, RA 4693 arch/powerpc/xmon/ppc-opc.c {"t", X(31,4), X_MASK, PWRCOM, 0, {TO, RA, RB}}, RA 4697 arch/powerpc/xmon/ppc-opc.c {"lbfcmx", APU(31,7,0), APU_MASK, PPC405, 0, {FCRT, RA, RB}}, RA 4699 arch/powerpc/xmon/ppc-opc.c {"subfc", XO(31,8,0,0), XO_MASK, PPCCOM, 0, {RT, RA, RB}}, RA 4700 arch/powerpc/xmon/ppc-opc.c {"sf", XO(31,8,0,0), XO_MASK, PWRCOM, 0, {RT, RA, RB}}, RA 4701 arch/powerpc/xmon/ppc-opc.c {"subc", XO(31,8,0,0), XO_MASK, PPCCOM, 0, {RT, RB, RA}}, RA 4702 arch/powerpc/xmon/ppc-opc.c {"subfc.", XO(31,8,0,1), XO_MASK, PPCCOM, 0, {RT, RA, RB}}, RA 4703 arch/powerpc/xmon/ppc-opc.c {"sf.", XO(31,8,0,1), XO_MASK, PWRCOM, 0, {RT, RA, RB}}, RA 4704 arch/powerpc/xmon/ppc-opc.c {"subc.", XO(31,8,0,1), XO_MASK, PPCCOM, 0, {RT, RB, RA}}, RA 4706 arch/powerpc/xmon/ppc-opc.c {"mulhdu", XO(31,9,0,0), XO_MASK, PPC64, 0, {RT, RA, RB}}, RA 4707 arch/powerpc/xmon/ppc-opc.c {"mulhdu.", XO(31,9,0,1), XO_MASK, PPC64, 0, {RT, RA, RB}}, RA 4709 arch/powerpc/xmon/ppc-opc.c {"addc", XO(31,10,0,0), XO_MASK, PPCCOM, 0, {RT, RA, RB}}, RA 4710 arch/powerpc/xmon/ppc-opc.c {"a", XO(31,10,0,0), XO_MASK, PWRCOM, 0, {RT, RA, RB}}, RA 4711 arch/powerpc/xmon/ppc-opc.c {"addc.", XO(31,10,0,1), XO_MASK, PPCCOM, 0, {RT, RA, RB}}, RA 4712 arch/powerpc/xmon/ppc-opc.c {"a.", XO(31,10,0,1), XO_MASK, PWRCOM, 0, {RT, RA, RB}}, RA 4714 arch/powerpc/xmon/ppc-opc.c {"mulhwu", XO(31,11,0,0), XO_MASK, PPC, 0, {RT, RA, RB}}, RA 4715 arch/powerpc/xmon/ppc-opc.c {"mulhwu.", XO(31,11,0,1), XO_MASK, PPC, 0, {RT, RA, RB}}, RA 4736 arch/powerpc/xmon/ppc-opc.c {"lx", X(31,23), X_MASK, PWRCOM, 0, {RT, RA, RB}}, RA 4738 arch/powerpc/xmon/ppc-opc.c {"slw", XRC(31,24,0), X_MASK, PPCCOM, 0, {RA, RS, RB}}, RA 4739 arch/powerpc/xmon/ppc-opc.c {"sl", XRC(31,24,0), X_MASK, PWRCOM, 0, {RA, RS, RB}}, RA 4740 arch/powerpc/xmon/ppc-opc.c {"slw.", XRC(31,24,1), X_MASK, PPCCOM, 0, {RA, RS, RB}}, RA 4741 arch/powerpc/xmon/ppc-opc.c {"sl.", XRC(31,24,1), X_MASK, PWRCOM, 0, {RA, RS, RB}}, RA 4743 arch/powerpc/xmon/ppc-opc.c {"cntlzw", XRC(31,26,0), XRB_MASK, PPCCOM, 0, {RA, RS}}, RA 4744 arch/powerpc/xmon/ppc-opc.c {"cntlz", XRC(31,26,0), XRB_MASK, PWRCOM, 0, {RA, RS}}, RA 4745 arch/powerpc/xmon/ppc-opc.c {"cntlzw.", XRC(31,26,1), XRB_MASK, PPCCOM, 0, {RA, RS}}, RA 4746 arch/powerpc/xmon/ppc-opc.c {"cntlz.", XRC(31,26,1), XRB_MASK, PWRCOM, 0, {RA, RS}}, RA 4748 arch/powerpc/xmon/ppc-opc.c {"sld", XRC(31,27,0), X_MASK, PPC64, 0, {RA, RS, RB}}, RA 4749 arch/powerpc/xmon/ppc-opc.c {"sld.", XRC(31,27,1), X_MASK, PPC64, 0, {RA, RS, RB}}, RA 4751 arch/powerpc/xmon/ppc-opc.c {"and", XRC(31,28,0), X_MASK, COM, 0, {RA, RS, RB}}, RA 4752 arch/powerpc/xmon/ppc-opc.c {"and.", XRC(31,28,1), X_MASK, COM, 0, {RA, RS, RB}}, RA 4754 arch/powerpc/xmon/ppc-opc.c {"maskg", XRC(31,29,0), X_MASK, M601, PPCA2, {RA, RS, RB}}, RA 4755 arch/powerpc/xmon/ppc-opc.c {"maskg.", XRC(31,29,1), X_MASK, M601, PPCA2, {RA, RS, RB}}, RA 4764 arch/powerpc/xmon/ppc-opc.c {"cmplw", XOPL(31,32,0), XCMPL_MASK, PPCCOM, 0, {OBF, RA, RB}}, RA 4765 arch/powerpc/xmon/ppc-opc.c {"cmpld", XOPL(31,32,1), XCMPL_MASK, PPC64, 0, {OBF, RA, RB}}, RA 4766 arch/powerpc/xmon/ppc-opc.c {"cmpl", X(31,32), XCMP_MASK, PPC, 0, {BF, L32OPT, RA, RB}}, RA 4767 arch/powerpc/xmon/ppc-opc.c {"cmpl", X(31,32), XCMPL_MASK, PWRCOM, PPC, {BF, RA, RB}}, RA 4771 arch/powerpc/xmon/ppc-opc.c {"lhfcmx", APU(31,39,0), APU_MASK, PPC405, 0, {FCRT, RA, RB}}, RA 4773 arch/powerpc/xmon/ppc-opc.c {"mviwsplt", X(31,46), X_MASK, PPCVEC2, 0, {VD, RA, RB}}, RA 4779 arch/powerpc/xmon/ppc-opc.c {"addg6s", XO(31,74,0,0), XO_MASK, POWER6, 0, {RT, RA, RB}}, RA 4787 arch/powerpc/xmon/ppc-opc.c {"subf", XO(31,40,0,0), XO_MASK, PPC, 0, {RT, RA, RB}}, RA 4788 arch/powerpc/xmon/ppc-opc.c {"sub", XO(31,40,0,0), XO_MASK, PPC, 0, {RT, RB, RA}}, RA 4789 arch/powerpc/xmon/ppc-opc.c {"subf.", XO(31,40,0,1), XO_MASK, PPC, 0, {RT, RA, RB}}, RA 4790 arch/powerpc/xmon/ppc-opc.c {"sub.", XO(31,40,0,1), XO_MASK, PPC, 0, {RT, RB, RA}}, RA 4792 arch/powerpc/xmon/ppc-opc.c {"mfvsrd", X(31,51), XX1RB_MASK, PPCVSX2, 0, {RA, XS6}}, RA 4793 arch/powerpc/xmon/ppc-opc.c {"mffprd", X(31,51), XX1RB_MASK|1, PPCVSX2, 0, {RA, FRS}}, RA 4794 arch/powerpc/xmon/ppc-opc.c {"mfvrd", X(31,51)|1, XX1RB_MASK|1, PPCVSX2, 0, {RA, VS}}, RA 4795 arch/powerpc/xmon/ppc-opc.c {"eratilx", X(31,51), X_MASK, PPCA2, 0, {ERAT_T, RA, RB}}, RA 4804 arch/powerpc/xmon/ppc-opc.c {"lux", X(31,55), X_MASK, PWRCOM, 0, {RT, RA, RB}}, RA 4806 arch/powerpc/xmon/ppc-opc.c {"cntlzd", XRC(31,58,0), XRB_MASK, PPC64, 0, {RA, RS}}, RA 4807 arch/powerpc/xmon/ppc-opc.c {"cntlzd.", XRC(31,58,1), XRB_MASK, PPC64, 0, {RA, RS}}, RA 4809 arch/powerpc/xmon/ppc-opc.c {"andc", XRC(31,60,0), X_MASK, COM, 0, {RA, RS, RB}}, RA 4810 arch/powerpc/xmon/ppc-opc.c {"andc.", XRC(31,60,1), X_MASK, COM, 0, {RA, RS, RB}}, RA 4818 arch/powerpc/xmon/ppc-opc.c {"tdlgt", XTO(31,68,TOLGT), XTO_MASK, PPC64, 0, {RA, RB}}, RA 4819 arch/powerpc/xmon/ppc-opc.c {"tdllt", XTO(31,68,TOLLT), XTO_MASK, PPC64, 0, {RA, RB}}, RA 4820 arch/powerpc/xmon/ppc-opc.c {"tdeq", XTO(31,68,TOEQ), XTO_MASK, PPC64, 0, {RA, RB}}, RA 4821 arch/powerpc/xmon/ppc-opc.c {"tdlge", XTO(31,68,TOLGE), XTO_MASK, PPC64, 0, {RA, RB}}, RA 4822 arch/powerpc/xmon/ppc-opc.c {"tdlnl", XTO(31,68,TOLNL), XTO_MASK, PPC64, 0, {RA, RB}}, RA 4823 arch/powerpc/xmon/ppc-opc.c {"tdlle", XTO(31,68,TOLLE), XTO_MASK, PPC64, 0, {RA, RB}}, RA 4824 arch/powerpc/xmon/ppc-opc.c {"tdlng", XTO(31,68,TOLNG), XTO_MASK, PPC64, 0, {RA, RB}}, RA 4825 arch/powerpc/xmon/ppc-opc.c {"tdgt", XTO(31,68,TOGT), XTO_MASK, PPC64, 0, {RA, RB}}, RA 4826 arch/powerpc/xmon/ppc-opc.c {"tdge", XTO(31,68,TOGE), XTO_MASK, PPC64, 0, {RA, RB}}, RA 4827 arch/powerpc/xmon/ppc-opc.c {"tdnl", XTO(31,68,TONL), XTO_MASK, PPC64, 0, {RA, RB}}, RA 4828 arch/powerpc/xmon/ppc-opc.c {"tdlt", XTO(31,68,TOLT), XTO_MASK, PPC64, 0, {RA, RB}}, RA 4829 arch/powerpc/xmon/ppc-opc.c {"tdle", XTO(31,68,TOLE), XTO_MASK, PPC64, 0, {RA, RB}}, RA 4830 arch/powerpc/xmon/ppc-opc.c {"tdng", XTO(31,68,TONG), XTO_MASK, PPC64, 0, {RA, RB}}, RA 4831 arch/powerpc/xmon/ppc-opc.c {"tdne", XTO(31,68,TONE), XTO_MASK, PPC64, 0, {RA, RB}}, RA 4832 arch/powerpc/xmon/ppc-opc.c {"tdu", XTO(31,68,TOU), XTO_MASK, PPC64, 0, {RA, RB}}, RA 4833 arch/powerpc/xmon/ppc-opc.c {"td", X(31,68), X_MASK, PPC64, 0, {TO, RA, RB}}, RA 4835 arch/powerpc/xmon/ppc-opc.c {"lwfcmx", APU(31,71,0), APU_MASK, PPC405, 0, {FCRT, RA, RB}}, RA 4836 arch/powerpc/xmon/ppc-opc.c {"mulhd", XO(31,73,0,0), XO_MASK, PPC64, 0, {RT, RA, RB}}, RA 4837 arch/powerpc/xmon/ppc-opc.c {"mulhd.", XO(31,73,0,1), XO_MASK, PPC64, 0, {RT, RA, RB}}, RA 4839 arch/powerpc/xmon/ppc-opc.c {"mulhw", XO(31,75,0,0), XO_MASK, PPC, 0, {RT, RA, RB}}, RA 4840 arch/powerpc/xmon/ppc-opc.c {"mulhw.", XO(31,75,0,1), XO_MASK, PPC, 0, {RT, RA, RB}}, RA 4842 arch/powerpc/xmon/ppc-opc.c {"dlmzb", XRC(31,78,0), X_MASK, PPC403|PPC440|TITAN, 0, {RA, RS, RB}}, RA 4843 arch/powerpc/xmon/ppc-opc.c {"dlmzb.", XRC(31,78,1), X_MASK, PPC403|PPC440|TITAN, 0, {RA, RS, RB}}, RA 4861 arch/powerpc/xmon/ppc-opc.c {"lqfcmx", APU(31,103,0), APU_MASK, PPC405, 0, {FCRT, RA, RB}}, RA 4863 arch/powerpc/xmon/ppc-opc.c {"neg", XO(31,104,0,0), XORB_MASK, COM, 0, {RT, RA}}, RA 4864 arch/powerpc/xmon/ppc-opc.c {"neg.", XO(31,104,0,1), XORB_MASK, COM, 0, {RT, RA}}, RA 4866 arch/powerpc/xmon/ppc-opc.c {"mul", XO(31,107,0,0), XO_MASK, M601, 0, {RT, RA, RB}}, RA 4867 arch/powerpc/xmon/ppc-opc.c {"mul.", XO(31,107,0,1), XO_MASK, M601, 0, {RT, RA, RB}}, RA 4869 arch/powerpc/xmon/ppc-opc.c {"mvidsplt", X(31,110), X_MASK, PPCVEC2, 0, {VD, RA, RB}}, RA 4873 arch/powerpc/xmon/ppc-opc.c {"mffprwz", X(31,115), XX1RB_MASK|1, PPCVSX2, 0, {RA, FRS}}, RA 4874 arch/powerpc/xmon/ppc-opc.c {"mfvrwz", X(31,115)|1, XX1RB_MASK|1, PPCVSX2, 0, {RA, VS}}, RA 4875 arch/powerpc/xmon/ppc-opc.c {"mfvsrwz", X(31,115), XX1RB_MASK, PPCVSX2, 0, {RA, XS6}}, RA 4879 arch/powerpc/xmon/ppc-opc.c {"clf", X(31,118), XTO_MASK, POWER, 0, {RA, RB}}, RA 4883 arch/powerpc/xmon/ppc-opc.c {"popcntb", X(31,122), XRB_MASK, POWER5, 0, {RA, RS}}, RA 4885 arch/powerpc/xmon/ppc-opc.c {"not", XRC(31,124,0), X_MASK, COM, 0, {RA, RS, RBS}}, RA 4886 arch/powerpc/xmon/ppc-opc.c {"nor", XRC(31,124,0), X_MASK, COM, 0, {RA, RS, RB}}, RA 4887 arch/powerpc/xmon/ppc-opc.c {"not.", XRC(31,124,1), X_MASK, COM, 0, {RA, RS, RBS}}, RA 4888 arch/powerpc/xmon/ppc-opc.c {"nor.", XRC(31,124,1), X_MASK, COM, 0, {RA, RS, RB}}, RA 4899 arch/powerpc/xmon/ppc-opc.c {"stbfcmx", APU(31,135,0), APU_MASK, PPC405, 0, {FCRT, RA, RB}}, RA 4901 arch/powerpc/xmon/ppc-opc.c {"subfe", XO(31,136,0,0), XO_MASK, PPCCOM, 0, {RT, RA, RB}}, RA 4902 arch/powerpc/xmon/ppc-opc.c {"sfe", XO(31,136,0,0), XO_MASK, PWRCOM, 0, {RT, RA, RB}}, RA 4903 arch/powerpc/xmon/ppc-opc.c {"subfe.", XO(31,136,0,1), XO_MASK, PPCCOM, 0, {RT, RA, RB}}, RA 4904 arch/powerpc/xmon/ppc-opc.c {"sfe.", XO(31,136,0,1), XO_MASK, PWRCOM, 0, {RT, RA, RB}}, RA 4906 arch/powerpc/xmon/ppc-opc.c {"adde", XO(31,138,0,0), XO_MASK, PPCCOM, 0, {RT, RA, RB}}, RA 4907 arch/powerpc/xmon/ppc-opc.c {"ae", XO(31,138,0,0), XO_MASK, PWRCOM, 0, {RT, RA, RB}}, RA 4908 arch/powerpc/xmon/ppc-opc.c {"adde.", XO(31,138,0,1), XO_MASK, PPCCOM, 0, {RT, RA, RB}}, RA 4909 arch/powerpc/xmon/ppc-opc.c {"ae.", XO(31,138,0,1), XO_MASK, PWRCOM, 0, {RT, RA, RB}}, RA 4932 arch/powerpc/xmon/ppc-opc.c {"stx", X(31,151), X_MASK, PWRCOM, 0, {RS, RA, RB}}, RA 4934 arch/powerpc/xmon/ppc-opc.c {"slq", XRC(31,152,0), X_MASK, M601, 0, {RA, RS, RB}}, RA 4935 arch/powerpc/xmon/ppc-opc.c {"slq.", XRC(31,152,1), X_MASK, M601, 0, {RA, RS, RB}}, RA 4937 arch/powerpc/xmon/ppc-opc.c {"sle", XRC(31,153,0), X_MASK, M601, 0, {RA, RS, RB}}, RA 4938 arch/powerpc/xmon/ppc-opc.c {"sle.", XRC(31,153,1), X_MASK, M601, 0, {RA, RS, RB}}, RA 4940 arch/powerpc/xmon/ppc-opc.c {"prtyw", X(31,154), XRB_MASK, POWER6|PPCA2|PPC476, 0, {RA, RS}}, RA 4951 arch/powerpc/xmon/ppc-opc.c {"sthfcmx", APU(31,167,0), APU_MASK, PPC405, 0, {FCRT, RA, RB}}, RA 4953 arch/powerpc/xmon/ppc-opc.c {"addex", ZRC(31,170,0), Z2_MASK, POWER9, 0, {RT, RA, RB, CY}}, RA 4960 arch/powerpc/xmon/ppc-opc.c {"mtvsrd", X(31,179), XX1RB_MASK, PPCVSX2, 0, {XT6, RA}}, RA 4961 arch/powerpc/xmon/ppc-opc.c {"mtfprd", X(31,179), XX1RB_MASK|1, PPCVSX2, 0, {FRT, RA}}, RA 4962 arch/powerpc/xmon/ppc-opc.c {"mtvrd", X(31,179)|1, XX1RB_MASK|1, PPCVSX2, 0, {VD, RA}}, RA 4963 arch/powerpc/xmon/ppc-opc.c {"eratre", X(31,179), X_MASK, PPCA2, 0, {RT, RA, WS}}, RA 4973 arch/powerpc/xmon/ppc-opc.c {"sliq", XRC(31,184,0), X_MASK, M601, 0, {RA, RS, SH}}, RA 4974 arch/powerpc/xmon/ppc-opc.c {"sliq.", XRC(31,184,1), X_MASK, M601, 0, {RA, RS, SH}}, RA 4976 arch/powerpc/xmon/ppc-opc.c {"prtyd", X(31,186), XRB_MASK, POWER6|PPCA2, 0, {RA, RS}}, RA 4978 arch/powerpc/xmon/ppc-opc.c {"cmprb", X(31,192), XCMP_MASK, POWER9, 0, {BF, L, RA, RB}}, RA 4983 arch/powerpc/xmon/ppc-opc.c {"stwfcmx", APU(31,199,0), APU_MASK, PPC405, 0, {FCRT, RA, RB}}, RA 4985 arch/powerpc/xmon/ppc-opc.c {"subfze", XO(31,200,0,0), XORB_MASK, PPCCOM, 0, {RT, RA}}, RA 4986 arch/powerpc/xmon/ppc-opc.c {"sfze", XO(31,200,0,0), XORB_MASK, PWRCOM, 0, {RT, RA}}, RA 4987 arch/powerpc/xmon/ppc-opc.c {"subfze.", XO(31,200,0,1), XORB_MASK, PPCCOM, 0, {RT, RA}}, RA 4988 arch/powerpc/xmon/ppc-opc.c {"sfze.", XO(31,200,0,1), XORB_MASK, PWRCOM, 0, {RT, RA}}, RA 4990 arch/powerpc/xmon/ppc-opc.c {"addze", XO(31,202,0,0), XORB_MASK, PPCCOM, 0, {RT, RA}}, RA 4991 arch/powerpc/xmon/ppc-opc.c {"aze", XO(31,202,0,0), XORB_MASK, PWRCOM, 0, {RT, RA}}, RA 4992 arch/powerpc/xmon/ppc-opc.c {"addze.", XO(31,202,0,1), XORB_MASK, PPCCOM, 0, {RT, RA}}, RA 4993 arch/powerpc/xmon/ppc-opc.c {"aze.", XO(31,202,0,1), XORB_MASK, PWRCOM, 0, {RT, RA}}, RA 4999 arch/powerpc/xmon/ppc-opc.c {"mtfprwa", X(31,211), XX1RB_MASK|1, PPCVSX2, 0, {FRT, RA}}, RA 5000 arch/powerpc/xmon/ppc-opc.c {"mtvrwa", X(31,211)|1, XX1RB_MASK|1, PPCVSX2, 0, {VD, RA}}, RA 5001 arch/powerpc/xmon/ppc-opc.c {"mtvsrwa", X(31,211), XX1RB_MASK, PPCVSX2, 0, {XT6, RA}}, RA 5002 arch/powerpc/xmon/ppc-opc.c {"eratwe", X(31,211), X_MASK, PPCA2, 0, {RS, RA, WS}}, RA 5010 arch/powerpc/xmon/ppc-opc.c {"sllq", XRC(31,216,0), X_MASK, M601, 0, {RA, RS, RB}}, RA 5011 arch/powerpc/xmon/ppc-opc.c {"sllq.", XRC(31,216,1), X_MASK, M601, 0, {RA, RS, RB}}, RA 5013 arch/powerpc/xmon/ppc-opc.c {"sleq", XRC(31,217,0), X_MASK, M601, 0, {RA, RS, RB}}, RA 5014 arch/powerpc/xmon/ppc-opc.c {"sleq.", XRC(31,217,1), X_MASK, M601, 0, {RA, RS, RB}}, RA 5018 arch/powerpc/xmon/ppc-opc.c {"cmpeqb", X(31,224), XCMPL_MASK, POWER9, 0, {BF, RA, RB}}, RA 5023 arch/powerpc/xmon/ppc-opc.c {"stqfcmx", APU(31,231,0), APU_MASK, PPC405, 0, {FCRT, RA, RB}}, RA 5025 arch/powerpc/xmon/ppc-opc.c {"subfme", XO(31,232,0,0), XORB_MASK, PPCCOM, 0, {RT, RA}}, RA 5026 arch/powerpc/xmon/ppc-opc.c {"sfme", XO(31,232,0,0), XORB_MASK, PWRCOM, 0, {RT, RA}}, RA 5027 arch/powerpc/xmon/ppc-opc.c {"subfme.", XO(31,232,0,1), XORB_MASK, PPCCOM, 0, {RT, RA}}, RA 5028 arch/powerpc/xmon/ppc-opc.c {"sfme.", XO(31,232,0,1), XORB_MASK, PWRCOM, 0, {RT, RA}}, RA 5030 arch/powerpc/xmon/ppc-opc.c {"mulld", XO(31,233,0,0), XO_MASK, PPC64, 0, {RT, RA, RB}}, RA 5031 arch/powerpc/xmon/ppc-opc.c {"mulld.", XO(31,233,0,1), XO_MASK, PPC64, 0, {RT, RA, RB}}, RA 5033 arch/powerpc/xmon/ppc-opc.c {"addme", XO(31,234,0,0), XORB_MASK, PPCCOM, 0, {RT, RA}}, RA 5034 arch/powerpc/xmon/ppc-opc.c {"ame", XO(31,234,0,0), XORB_MASK, PWRCOM, 0, {RT, RA}}, RA 5035 arch/powerpc/xmon/ppc-opc.c {"addme.", XO(31,234,0,1), XORB_MASK, PPCCOM, 0, {RT, RA}}, RA 5036 arch/powerpc/xmon/ppc-opc.c {"ame.", XO(31,234,0,1), XORB_MASK, PWRCOM, 0, {RT, RA}}, RA 5038 arch/powerpc/xmon/ppc-opc.c {"mullw", XO(31,235,0,0), XO_MASK, PPCCOM, 0, {RT, RA, RB}}, RA 5039 arch/powerpc/xmon/ppc-opc.c {"muls", XO(31,235,0,0), XO_MASK, PWRCOM, 0, {RT, RA, RB}}, RA 5040 arch/powerpc/xmon/ppc-opc.c {"mullw.", XO(31,235,0,1), XO_MASK, PPCCOM, 0, {RT, RA, RB}}, RA 5041 arch/powerpc/xmon/ppc-opc.c {"muls.", XO(31,235,0,1), XO_MASK, PWRCOM, 0, {RT, RA, RB}}, RA 5043 arch/powerpc/xmon/ppc-opc.c {"icblce", X(31,238), X_MASK, PPCCHLK, E500MC|PPCA2, {CT, RA, RB}}, RA 5048 arch/powerpc/xmon/ppc-opc.c {"mtfprwz", X(31,243), XX1RB_MASK|1, PPCVSX2, 0, {FRT, RA}}, RA 5049 arch/powerpc/xmon/ppc-opc.c {"mtvrwz", X(31,243)|1, XX1RB_MASK|1, PPCVSX2, 0, {VD, RA}}, RA 5050 arch/powerpc/xmon/ppc-opc.c {"mtvsrwz", X(31,243), XX1RB_MASK, PPCVSX2, 0, {XT6, RA}}, RA 5059 arch/powerpc/xmon/ppc-opc.c {"slliq", XRC(31,248,0), X_MASK, M601, 0, {RA, RS, SH}}, RA 5060 arch/powerpc/xmon/ppc-opc.c {"slliq.", XRC(31,248,1), X_MASK, M601, 0, {RA, RS, SH}}, RA 5062 arch/powerpc/xmon/ppc-opc.c {"bpermd", X(31,252), X_MASK, POWER7|PPCA2, 0, {RA, RS, RB}}, RA 5066 arch/powerpc/xmon/ppc-opc.c {"mfdcrx", X(31,259), X_MASK, BOOKE|PPCA2|PPC476, TITAN, {RS, RA}}, RA 5067 arch/powerpc/xmon/ppc-opc.c {"mfdcrx.", XRC(31,259,1), X_MASK, PPCA2, 0, {RS, RA}}, RA 5071 arch/powerpc/xmon/ppc-opc.c {"icbt", X(31,262), XRT_MASK, PPC403, 0, {RA, RB}}, RA 5075 arch/powerpc/xmon/ppc-opc.c {"ldfcmx", APU(31,263,0), APU_MASK, PPC405, 0, {FCRT, RA, RB}}, RA 5076 arch/powerpc/xmon/ppc-opc.c {"doz", XO(31,264,0,0), XO_MASK, M601, 0, {RT, RA, RB}}, RA 5077 arch/powerpc/xmon/ppc-opc.c {"doz.", XO(31,264,0,1), XO_MASK, M601, 0, {RT, RA, RB}}, RA 5079 arch/powerpc/xmon/ppc-opc.c {"modud", X(31,265), X_MASK, POWER9, 0, {RT, RA, RB}}, RA 5081 arch/powerpc/xmon/ppc-opc.c {"add", XO(31,266,0,0), XO_MASK, PPCCOM, 0, {RT, RA, RB}}, RA 5082 arch/powerpc/xmon/ppc-opc.c {"cax", XO(31,266,0,0), XO_MASK, PWRCOM, 0, {RT, RA, RB}}, RA 5083 arch/powerpc/xmon/ppc-opc.c {"add.", XO(31,266,0,1), XO_MASK, PPCCOM, 0, {RT, RA, RB}}, RA 5084 arch/powerpc/xmon/ppc-opc.c {"cax.", XO(31,266,0,1), XO_MASK, PWRCOM, 0, {RT, RA, RB}}, RA 5086 arch/powerpc/xmon/ppc-opc.c {"moduw", X(31,267), X_MASK, POWER9, 0, {RT, RA, RB}}, RA 5096 arch/powerpc/xmon/ppc-opc.c {"mfapidi", X(31,275), X_MASK, BOOKE, E500|TITAN, {RT, RA}}, RA 5100 arch/powerpc/xmon/ppc-opc.c {"lscbx", XRC(31,277,0), X_MASK, M601, 0, {RT, RA, RB}}, RA 5101 arch/powerpc/xmon/ppc-opc.c {"lscbx.", XRC(31,277,1), X_MASK, M601, 0, {RT, RA, RB}}, RA 5110 arch/powerpc/xmon/ppc-opc.c {"cdtbcd", X(31,282), XRB_MASK, POWER6, 0, {RA, RS}}, RA 5112 arch/powerpc/xmon/ppc-opc.c {"eqv", XRC(31,284,0), X_MASK, COM, 0, {RA, RS, RB}}, RA 5113 arch/powerpc/xmon/ppc-opc.c {"eqv.", XRC(31,284,1), X_MASK, COM, 0, {RA, RS, RB}}, RA 5117 arch/powerpc/xmon/ppc-opc.c {"mfdcrux", X(31,291), X_MASK, PPC464, 0, {RS, RA}}, RA 5131 arch/powerpc/xmon/ppc-opc.c {"mfvsrld", X(31,307), XX1RB_MASK, PPCVSX3, 0, {RA, XS6}}, RA 5139 arch/powerpc/xmon/ppc-opc.c {"cbcdtd", X(31,314), XRB_MASK, POWER6, 0, {RA, RS}}, RA 5141 arch/powerpc/xmon/ppc-opc.c {"xor", XRC(31,316,0), X_MASK, COM, 0, {RA, RS, RB}}, RA 5142 arch/powerpc/xmon/ppc-opc.c {"xor.", XRC(31,316,1), X_MASK, COM, 0, {RA, RS, RB}}, RA 5187 arch/powerpc/xmon/ppc-opc.c {"div", XO(31,331,0,0), XO_MASK, M601, 0, {RT, RA, RB}}, RA 5188 arch/powerpc/xmon/ppc-opc.c {"div.", XO(31,331,0,1), XO_MASK, M601, 0, {RT, RA, RB}}, RA 5401 arch/powerpc/xmon/ppc-opc.c {"dst", XDSS(31,342,0), XDSS_MASK, PPCVEC, 0, {RA, RB, STRM}}, RA 5407 arch/powerpc/xmon/ppc-opc.c {"abs", XO(31,360,0,0), XORB_MASK, M601, 0, {RT, RA}}, RA 5408 arch/powerpc/xmon/ppc-opc.c {"abs.", XO(31,360,0,1), XORB_MASK, M601, 0, {RT, RA}}, RA 5410 arch/powerpc/xmon/ppc-opc.c {"divs", XO(31,363,0,0), XO_MASK, M601, 0, {RT, RA, RB}}, RA 5411 arch/powerpc/xmon/ppc-opc.c {"divs.", XO(31,363,0,1), XO_MASK, M601, 0, {RT, RA, RB}}, RA 5423 arch/powerpc/xmon/ppc-opc.c {"dstst", XDSS(31,374,0), XDSS_MASK, PPCVEC, 0, {RA, RB, STRM}}, RA 5427 arch/powerpc/xmon/ppc-opc.c {"popcntw", X(31,378), XRB_MASK, POWER7|PPCA2, 0, {RA, RS}}, RA 5429 arch/powerpc/xmon/ppc-opc.c {"mtdcrx", X(31,387), X_MASK, BOOKE|PPCA2|PPC476, TITAN, {RA, RS}}, RA 5430 arch/powerpc/xmon/ppc-opc.c {"mtdcrx.", XRC(31,387,1), X_MASK, PPCA2, 0, {RA, RS}}, RA 5435 arch/powerpc/xmon/ppc-opc.c {"stdfcmx", APU(31,391,0), APU_MASK, PPC405, 0, {FCRT, RA, RB}}, RA 5437 arch/powerpc/xmon/ppc-opc.c {"divdeu", XO(31,393,0,0), XO_MASK, POWER7|PPCA2, 0, {RT, RA, RB}}, RA 5438 arch/powerpc/xmon/ppc-opc.c {"divdeu.", XO(31,393,0,1), XO_MASK, POWER7|PPCA2, 0, {RT, RA, RB}}, RA 5439 arch/powerpc/xmon/ppc-opc.c {"divweu", XO(31,395,0,0), XO_MASK, POWER7|PPCA2, 0, {RT, RA, RB}}, RA 5440 arch/powerpc/xmon/ppc-opc.c {"divweu.", XO(31,395,0,1), XO_MASK, POWER7|PPCA2, 0, {RT, RA, RB}}, RA 5445 arch/powerpc/xmon/ppc-opc.c {"dcblce", X(31,398), X_MASK, PPCCHLK, E500MC, {CT, RA, RB}}, RA 5449 arch/powerpc/xmon/ppc-opc.c {"mtvsrws", X(31,403), XX1RB_MASK, PPCVSX3, 0, {XT6, RA}}, RA 5453 arch/powerpc/xmon/ppc-opc.c {"icswx", XRC(31,406,0), X_MASK, POWER7|PPCA2, 0, {RS, RA, RB}}, RA 5454 arch/powerpc/xmon/ppc-opc.c {"icswx.", XRC(31,406,1), X_MASK, POWER7|PPCA2, 0, {RS, RA, RB}}, RA 5458 arch/powerpc/xmon/ppc-opc.c {"orc", XRC(31,412,0), X_MASK, COM, 0, {RA, RS, RB}}, RA 5459 arch/powerpc/xmon/ppc-opc.c {"orc.", XRC(31,412,1), X_MASK, COM, 0, {RA, RS, RB}}, RA 5463 arch/powerpc/xmon/ppc-opc.c {"mtdcrux", X(31,419), X_MASK, PPC464, 0, {RA, RS}}, RA 5469 arch/powerpc/xmon/ppc-opc.c {"divde", XO(31,425,0,0), XO_MASK, POWER7|PPCA2, 0, {RT, RA, RB}}, RA 5470 arch/powerpc/xmon/ppc-opc.c {"divde.", XO(31,425,0,1), XO_MASK, POWER7|PPCA2, 0, {RT, RA, RB}}, RA 5471 arch/powerpc/xmon/ppc-opc.c {"divwe", XO(31,427,0,0), XO_MASK, POWER7|PPCA2, 0, {RT, RA, RB}}, RA 5472 arch/powerpc/xmon/ppc-opc.c {"divwe.", XO(31,427,0,1), XO_MASK, POWER7|PPCA2, 0, {RT, RA, RB}}, RA 5495 arch/powerpc/xmon/ppc-opc.c {"mr", XRC(31,444,0), X_MASK, COM, 0, {RA, RS, RBS}}, RA 5496 arch/powerpc/xmon/ppc-opc.c {"or", XRC(31,444,0), X_MASK, COM, 0, {RA, RS, RB}}, RA 5497 arch/powerpc/xmon/ppc-opc.c {"mr.", XRC(31,444,1), X_MASK, COM, 0, {RA, RS, RBS}}, RA 5498 arch/powerpc/xmon/ppc-opc.c {"or.", XRC(31,444,1), X_MASK, COM, 0, {RA, RS, RB}}, RA 5542 arch/powerpc/xmon/ppc-opc.c {"divdu", XO(31,457,0,0), XO_MASK, PPC64, 0, {RT, RA, RB}}, RA 5543 arch/powerpc/xmon/ppc-opc.c {"divdu.", XO(31,457,0,1), XO_MASK, PPC64, 0, {RT, RA, RB}}, RA 5545 arch/powerpc/xmon/ppc-opc.c {"divwu", XO(31,459,0,0), XO_MASK, PPC, 0, {RT, RA, RB}}, RA 5546 arch/powerpc/xmon/ppc-opc.c {"divwu.", XO(31,459,0,1), XO_MASK, PPC, 0, {RT, RA, RB}}, RA 5721 arch/powerpc/xmon/ppc-opc.c {"nand", XRC(31,476,0), X_MASK, COM, 0, {RA, RS, RB}}, RA 5722 arch/powerpc/xmon/ppc-opc.c {"nand.", XRC(31,476,1), X_MASK, COM, 0, {RA, RS, RB}}, RA 5724 arch/powerpc/xmon/ppc-opc.c {"dsn", X(31,483), XRT_MASK, E500MC, 0, {RA, RB}}, RA 5732 arch/powerpc/xmon/ppc-opc.c {"nabs", XO(31,488,0,0), XORB_MASK, M601, 0, {RT, RA}}, RA 5733 arch/powerpc/xmon/ppc-opc.c {"nabs.", XO(31,488,0,1), XORB_MASK, M601, 0, {RT, RA}}, RA 5735 arch/powerpc/xmon/ppc-opc.c {"divd", XO(31,489,0,0), XO_MASK, PPC64, 0, {RT, RA, RB}}, RA 5736 arch/powerpc/xmon/ppc-opc.c {"divd.", XO(31,489,0,1), XO_MASK, PPC64, 0, {RT, RA, RB}}, RA 5738 arch/powerpc/xmon/ppc-opc.c {"divw", XO(31,491,0,0), XO_MASK, PPC, 0, {RT, RA, RB}}, RA 5739 arch/powerpc/xmon/ppc-opc.c {"divw.", XO(31,491,0,1), XO_MASK, PPC, 0, {RT, RA, RB}}, RA 5741 arch/powerpc/xmon/ppc-opc.c {"icbtlse", X(31,494), X_MASK, PPCCHLK, E500MC, {CT, RA, RB}}, RA 5746 arch/powerpc/xmon/ppc-opc.c {"cli", X(31,502), XRB_MASK, POWER, 0, {RT, RA}}, RA 5748 arch/powerpc/xmon/ppc-opc.c {"popcntd", X(31,506), XRB_MASK, POWER7|PPCA2, 0, {RA, RS}}, RA 5750 arch/powerpc/xmon/ppc-opc.c {"cmpb", X(31,508), X_MASK, POWER6|PPCA2|PPC476, 0, {RA, RS, RB}}, RA 5754 arch/powerpc/xmon/ppc-opc.c {"lbdcbx", X(31,514), X_MASK, E200Z4, 0, {RT, RA, RB}}, RA 5755 arch/powerpc/xmon/ppc-opc.c {"lbdx", X(31,515), X_MASK, E500MC, 0, {RT, RA, RB}}, RA 5760 arch/powerpc/xmon/ppc-opc.c {"lbfcmux", APU(31,519,0), APU_MASK, PPC405, 0, {FCRT, RA, RB}}, RA 5762 arch/powerpc/xmon/ppc-opc.c {"subfco", XO(31,8,1,0), XO_MASK, PPCCOM, 0, {RT, RA, RB}}, RA 5763 arch/powerpc/xmon/ppc-opc.c {"sfo", XO(31,8,1,0), XO_MASK, PWRCOM, 0, {RT, RA, RB}}, RA 5764 arch/powerpc/xmon/ppc-opc.c {"subco", XO(31,8,1,0), XO_MASK, PPCCOM, 0, {RT, RB, RA}}, RA 5765 arch/powerpc/xmon/ppc-opc.c {"subfco.", XO(31,8,1,1), XO_MASK, PPCCOM, 0, {RT, RA, RB}}, RA 5766 arch/powerpc/xmon/ppc-opc.c {"sfo.", XO(31,8,1,1), XO_MASK, PWRCOM, 0, {RT, RA, RB}}, RA 5767 arch/powerpc/xmon/ppc-opc.c {"subco.", XO(31,8,1,1), XO_MASK, PPCCOM, 0, {RT, RB, RA}}, RA 5769 arch/powerpc/xmon/ppc-opc.c {"addco", XO(31,10,1,0), XO_MASK, PPCCOM, 0, {RT, RA, RB}}, RA 5770 arch/powerpc/xmon/ppc-opc.c {"ao", XO(31,10,1,0), XO_MASK, PWRCOM, 0, {RT, RA, RB}}, RA 5771 arch/powerpc/xmon/ppc-opc.c {"addco.", XO(31,10,1,1), XO_MASK, PPCCOM, 0, {RT, RA, RB}}, RA 5772 arch/powerpc/xmon/ppc-opc.c {"ao.", XO(31,10,1,1), XO_MASK, PWRCOM, 0, {RT, RA, RB}}, RA 5776 arch/powerpc/xmon/ppc-opc.c {"clcs", X(31,531), XRB_MASK, M601, 0, {RT, RA}}, RA 5781 arch/powerpc/xmon/ppc-opc.c {"lsx", X(31,533), X_MASK, PWRCOM, 0, {RT, RA, RB}}, RA 5784 arch/powerpc/xmon/ppc-opc.c {"lbrx", X(31,534), X_MASK, PWRCOM, 0, {RT, RA, RB}}, RA 5788 arch/powerpc/xmon/ppc-opc.c {"srw", XRC(31,536,0), X_MASK, PPCCOM, 0, {RA, RS, RB}}, RA 5789 arch/powerpc/xmon/ppc-opc.c {"sr", XRC(31,536,0), X_MASK, PWRCOM, 0, {RA, RS, RB}}, RA 5790 arch/powerpc/xmon/ppc-opc.c {"srw.", XRC(31,536,1), X_MASK, PPCCOM, 0, {RA, RS, RB}}, RA 5791 arch/powerpc/xmon/ppc-opc.c {"sr.", XRC(31,536,1), X_MASK, PWRCOM, 0, {RA, RS, RB}}, RA 5793 arch/powerpc/xmon/ppc-opc.c {"rrib", XRC(31,537,0), X_MASK, M601, 0, {RA, RS, RB}}, RA 5794 arch/powerpc/xmon/ppc-opc.c {"rrib.", XRC(31,537,1), X_MASK, M601, 0, {RA, RS, RB}}, RA 5796 arch/powerpc/xmon/ppc-opc.c {"cnttzw", XRC(31,538,0), XRB_MASK, POWER9, 0, {RA, RS}}, RA 5797 arch/powerpc/xmon/ppc-opc.c {"cnttzw.", XRC(31,538,1), XRB_MASK, POWER9, 0, {RA, RS}}, RA 5799 arch/powerpc/xmon/ppc-opc.c {"srd", XRC(31,539,0), X_MASK, PPC64, 0, {RA, RS, RB}}, RA 5800 arch/powerpc/xmon/ppc-opc.c {"srd.", XRC(31,539,1), X_MASK, PPC64, 0, {RA, RS, RB}}, RA 5802 arch/powerpc/xmon/ppc-opc.c {"maskir", XRC(31,541,0), X_MASK, M601, 0, {RA, RS, RB}}, RA 5803 arch/powerpc/xmon/ppc-opc.c {"maskir.", XRC(31,541,1), X_MASK, M601, 0, {RA, RS, RB}}, RA 5805 arch/powerpc/xmon/ppc-opc.c {"lhdcbx", X(31,546), X_MASK, E200Z4, 0, {RT, RA, RB}}, RA 5806 arch/powerpc/xmon/ppc-opc.c {"lhdx", X(31,547), X_MASK, E500MC, 0, {RT, RA, RB}}, RA 5813 arch/powerpc/xmon/ppc-opc.c {"lhfcmux", APU(31,551,0), APU_MASK, PPC405, 0, {FCRT, RA, RB}}, RA 5815 arch/powerpc/xmon/ppc-opc.c {"subfo", XO(31,40,1,0), XO_MASK, PPC, 0, {RT, RA, RB}}, RA 5816 arch/powerpc/xmon/ppc-opc.c {"subo", XO(31,40,1,0), XO_MASK, PPC, 0, {RT, RB, RA}}, RA 5817 arch/powerpc/xmon/ppc-opc.c {"subfo.", XO(31,40,1,1), XO_MASK, PPC, 0, {RT, RA, RB}}, RA 5818 arch/powerpc/xmon/ppc-opc.c {"subo.", XO(31,40,1,1), XO_MASK, PPC, 0, {RT, RB, RA}}, RA 5824 arch/powerpc/xmon/ppc-opc.c {"cnttzd", XRC(31,570,0), XRB_MASK, POWER9, 0, {RA, RS}}, RA 5825 arch/powerpc/xmon/ppc-opc.c {"cnttzd.", XRC(31,570,1), XRB_MASK, POWER9, 0, {RA, RS}}, RA 5829 arch/powerpc/xmon/ppc-opc.c {"lwdcbx", X(31,578), X_MASK, E200Z4, 0, {RT, RA, RB}}, RA 5830 arch/powerpc/xmon/ppc-opc.c {"lwdx", X(31,579), X_MASK, E500MC, 0, {RT, RA, RB}}, RA 5836 arch/powerpc/xmon/ppc-opc.c {"lwfcmux", APU(31,583,0), APU_MASK, PPC405, 0, {FCRT, RA, RB}}, RA 5860 arch/powerpc/xmon/ppc-opc.c {"lddx", X(31,611), X_MASK, E500MC, 0, {RT, RA, RB}}, RA 5866 arch/powerpc/xmon/ppc-opc.c {"lqfcmux", APU(31,615,0), APU_MASK, PPC405, 0, {FCRT, RA, RB}}, RA 5868 arch/powerpc/xmon/ppc-opc.c {"nego", XO(31,104,1,0), XORB_MASK, COM, 0, {RT, RA}}, RA 5869 arch/powerpc/xmon/ppc-opc.c {"nego.", XO(31,104,1,1), XORB_MASK, COM, 0, {RT, RA}}, RA 5871 arch/powerpc/xmon/ppc-opc.c {"mulo", XO(31,107,1,0), XO_MASK, M601, 0, {RT, RA, RB}}, RA 5872 arch/powerpc/xmon/ppc-opc.c {"mulo.", XO(31,107,1,1), XO_MASK, M601, 0, {RT, RA, RB}}, RA 5874 arch/powerpc/xmon/ppc-opc.c {"mfsri", X(31,627), X_MASK, M601, 0, {RT, RA, RB}}, RA 5876 arch/powerpc/xmon/ppc-opc.c {"dclst", X(31,630), XRB_MASK, M601, 0, {RS, RA}}, RA 5880 arch/powerpc/xmon/ppc-opc.c {"stbdcbx", X(31,642), X_MASK, E200Z4, 0, {RS, RA, RB}}, RA 5881 arch/powerpc/xmon/ppc-opc.c {"stbdx", X(31,643), X_MASK, E500MC, 0, {RS, RA, RB}}, RA 5884 arch/powerpc/xmon/ppc-opc.c {"stbfcmux", APU(31,647,0), APU_MASK, PPC405, 0, {FCRT, RA, RB}}, RA 5890 arch/powerpc/xmon/ppc-opc.c {"subfeo", XO(31,136,1,0), XO_MASK, PPCCOM, 0, {RT, RA, RB}}, RA 5891 arch/powerpc/xmon/ppc-opc.c {"sfeo", XO(31,136,1,0), XO_MASK, PWRCOM, 0, {RT, RA, RB}}, RA 5892 arch/powerpc/xmon/ppc-opc.c {"subfeo.", XO(31,136,1,1), XO_MASK, PPCCOM, 0, {RT, RA, RB}}, RA 5893 arch/powerpc/xmon/ppc-opc.c {"sfeo.", XO(31,136,1,1), XO_MASK, PWRCOM, 0, {RT, RA, RB}}, RA 5895 arch/powerpc/xmon/ppc-opc.c {"addeo", XO(31,138,1,0), XO_MASK, PPCCOM, 0, {RT, RA, RB}}, RA 5896 arch/powerpc/xmon/ppc-opc.c {"aeo", XO(31,138,1,0), XO_MASK, PWRCOM, 0, {RT, RA, RB}}, RA 5897 arch/powerpc/xmon/ppc-opc.c {"addeo.", XO(31,138,1,1), XO_MASK, PPCCOM, 0, {RT, RA, RB}}, RA 5898 arch/powerpc/xmon/ppc-opc.c {"aeo.", XO(31,138,1,1), XO_MASK, PWRCOM, 0, {RT, RA, RB}}, RA 5912 arch/powerpc/xmon/ppc-opc.c {"srq", XRC(31,664,0), X_MASK, M601, 0, {RA, RS, RB}}, RA 5913 arch/powerpc/xmon/ppc-opc.c {"srq.", XRC(31,664,1), X_MASK, M601, 0, {RA, RS, RB}}, RA 5915 arch/powerpc/xmon/ppc-opc.c {"sre", XRC(31,665,0), X_MASK, M601, 0, {RA, RS, RB}}, RA 5916 arch/powerpc/xmon/ppc-opc.c {"sre.", XRC(31,665,1), X_MASK, M601, 0, {RA, RS, RB}}, RA 5918 arch/powerpc/xmon/ppc-opc.c {"sthdcbx", X(31,674), X_MASK, E200Z4, 0, {RS, RA, RB}}, RA 5919 arch/powerpc/xmon/ppc-opc.c {"sthdx", X(31,675), X_MASK, E500MC, 0, {RS, RA, RB}}, RA 5924 arch/powerpc/xmon/ppc-opc.c {"sthfcmux", APU(31,679,0), APU_MASK, PPC405, 0, {FCRT, RA, RB}}, RA 5933 arch/powerpc/xmon/ppc-opc.c {"sriq", XRC(31,696,0), X_MASK, M601, 0, {RA, RS, SH}}, RA 5934 arch/powerpc/xmon/ppc-opc.c {"sriq.", XRC(31,696,1), X_MASK, M601, 0, {RA, RS, SH}}, RA 5936 arch/powerpc/xmon/ppc-opc.c {"stwdcbx", X(31,706), X_MASK, E200Z4, 0, {RS, RA, RB}}, RA 5937 arch/powerpc/xmon/ppc-opc.c {"stwdx", X(31,707), X_MASK, E500MC, 0, {RS, RA, RB}}, RA 5943 arch/powerpc/xmon/ppc-opc.c {"stwfcmux", APU(31,711,0), APU_MASK, PPC405, 0, {FCRT, RA, RB}}, RA 5949 arch/powerpc/xmon/ppc-opc.c {"subfzeo", XO(31,200,1,0), XORB_MASK, PPCCOM, 0, {RT, RA}}, RA 5950 arch/powerpc/xmon/ppc-opc.c {"sfzeo", XO(31,200,1,0), XORB_MASK, PWRCOM, 0, {RT, RA}}, RA 5951 arch/powerpc/xmon/ppc-opc.c {"subfzeo.", XO(31,200,1,1), XORB_MASK, PPCCOM, 0, {RT, RA}}, RA 5952 arch/powerpc/xmon/ppc-opc.c {"sfzeo.", XO(31,200,1,1), XORB_MASK, PWRCOM, 0, {RT, RA}}, RA 5954 arch/powerpc/xmon/ppc-opc.c {"addzeo", XO(31,202,1,0), XORB_MASK, PPCCOM, 0, {RT, RA}}, RA 5955 arch/powerpc/xmon/ppc-opc.c {"azeo", XO(31,202,1,0), XORB_MASK, PWRCOM, 0, {RT, RA}}, RA 5956 arch/powerpc/xmon/ppc-opc.c {"addzeo.", XO(31,202,1,1), XORB_MASK, PPCCOM, 0, {RT, RA}}, RA 5957 arch/powerpc/xmon/ppc-opc.c {"azeo.", XO(31,202,1,1), XORB_MASK, PWRCOM, 0, {RT, RA}}, RA 5966 arch/powerpc/xmon/ppc-opc.c {"srlq", XRC(31,728,0), X_MASK, M601, 0, {RA, RS, RB}}, RA 5967 arch/powerpc/xmon/ppc-opc.c {"srlq.", XRC(31,728,1), X_MASK, M601, 0, {RA, RS, RB}}, RA 5969 arch/powerpc/xmon/ppc-opc.c {"sreq", XRC(31,729,0), X_MASK, M601, 0, {RA, RS, RB}}, RA 5970 arch/powerpc/xmon/ppc-opc.c {"sreq.", XRC(31,729,1), X_MASK, M601, 0, {RA, RS, RB}}, RA 5975 arch/powerpc/xmon/ppc-opc.c {"stddx", X(31,739), X_MASK, E500MC, 0, {RS, RA, RB}}, RA 5981 arch/powerpc/xmon/ppc-opc.c {"stqfcmux", APU(31,743,0), APU_MASK, PPC405, 0, {FCRT, RA, RB}}, RA 5983 arch/powerpc/xmon/ppc-opc.c {"subfmeo", XO(31,232,1,0), XORB_MASK, PPCCOM, 0, {RT, RA}}, RA 5984 arch/powerpc/xmon/ppc-opc.c {"sfmeo", XO(31,232,1,0), XORB_MASK, PWRCOM, 0, {RT, RA}}, RA 5985 arch/powerpc/xmon/ppc-opc.c {"subfmeo.", XO(31,232,1,1), XORB_MASK, PPCCOM, 0, {RT, RA}}, RA 5986 arch/powerpc/xmon/ppc-opc.c {"sfmeo.", XO(31,232,1,1), XORB_MASK, PWRCOM, 0, {RT, RA}}, RA 5988 arch/powerpc/xmon/ppc-opc.c {"mulldo", XO(31,233,1,0), XO_MASK, PPC64, 0, {RT, RA, RB}}, RA 5989 arch/powerpc/xmon/ppc-opc.c {"mulldo.", XO(31,233,1,1), XO_MASK, PPC64, 0, {RT, RA, RB}}, RA 5991 arch/powerpc/xmon/ppc-opc.c {"addmeo", XO(31,234,1,0), XORB_MASK, PPCCOM, 0, {RT, RA}}, RA 5992 arch/powerpc/xmon/ppc-opc.c {"ameo", XO(31,234,1,0), XORB_MASK, PWRCOM, 0, {RT, RA}}, RA 5993 arch/powerpc/xmon/ppc-opc.c {"addmeo.", XO(31,234,1,1), XORB_MASK, PPCCOM, 0, {RT, RA}}, RA 5994 arch/powerpc/xmon/ppc-opc.c {"ameo.", XO(31,234,1,1), XORB_MASK, PWRCOM, 0, {RT, RA}}, RA 5996 arch/powerpc/xmon/ppc-opc.c {"mullwo", XO(31,235,1,0), XO_MASK, PPCCOM, 0, {RT, RA, RB}}, RA 5997 arch/powerpc/xmon/ppc-opc.c {"mulso", XO(31,235,1,0), XO_MASK, PWRCOM, 0, {RT, RA, RB}}, RA 5998 arch/powerpc/xmon/ppc-opc.c {"mullwo.", XO(31,235,1,1), XO_MASK, PPCCOM, 0, {RT, RA, RB}}, RA 5999 arch/powerpc/xmon/ppc-opc.c {"mulso.", XO(31,235,1,1), XO_MASK, PWRCOM, 0, {RT, RA, RB}}, RA 6012 arch/powerpc/xmon/ppc-opc.c {"srliq", XRC(31,760,0), X_MASK, M601, 0, {RA, RS, SH}}, RA 6013 arch/powerpc/xmon/ppc-opc.c {"srliq.", XRC(31,760,1), X_MASK, M601, 0, {RA, RS, SH}}, RA 6021 arch/powerpc/xmon/ppc-opc.c {"ldfcmux", APU(31,775,0), APU_MASK, PPC405, 0, {FCRT, RA, RB}}, RA 6023 arch/powerpc/xmon/ppc-opc.c {"dozo", XO(31,264,1,0), XO_MASK, M601, 0, {RT, RA, RB}}, RA 6024 arch/powerpc/xmon/ppc-opc.c {"dozo.", XO(31,264,1,1), XO_MASK, M601, 0, {RT, RA, RB}}, RA 6026 arch/powerpc/xmon/ppc-opc.c {"addo", XO(31,266,1,0), XO_MASK, PPCCOM, 0, {RT, RA, RB}}, RA 6027 arch/powerpc/xmon/ppc-opc.c {"caxo", XO(31,266,1,0), XO_MASK, PWRCOM, 0, {RT, RA, RB}}, RA 6028 arch/powerpc/xmon/ppc-opc.c {"addo.", XO(31,266,1,1), XO_MASK, PPCCOM, 0, {RT, RA, RB}}, RA 6029 arch/powerpc/xmon/ppc-opc.c {"caxo.", XO(31,266,1,1), XO_MASK, PWRCOM, 0, {RT, RA, RB}}, RA 6031 arch/powerpc/xmon/ppc-opc.c {"modsd", X(31,777), X_MASK, POWER9, 0, {RT, RA, RB}}, RA 6032 arch/powerpc/xmon/ppc-opc.c {"modsw", X(31,779), X_MASK, POWER9, 0, {RT, RA, RB}}, RA 6037 arch/powerpc/xmon/ppc-opc.c {"tabortwc.", XRC(31,782,1), X_MASK, PPCHTM, 0, {TO, RA, RB}}, RA 6046 arch/powerpc/xmon/ppc-opc.c {"lfqx", X(31,791), X_MASK, POWER2, 0, {FRT, RA, RB}}, RA 6048 arch/powerpc/xmon/ppc-opc.c {"sraw", XRC(31,792,0), X_MASK, PPCCOM, 0, {RA, RS, RB}}, RA 6049 arch/powerpc/xmon/ppc-opc.c {"sra", XRC(31,792,0), X_MASK, PWRCOM, 0, {RA, RS, RB}}, RA 6050 arch/powerpc/xmon/ppc-opc.c {"sraw.", XRC(31,792,1), X_MASK, PPCCOM, 0, {RA, RS, RB}}, RA 6051 arch/powerpc/xmon/ppc-opc.c {"sra.", XRC(31,792,1), X_MASK, PWRCOM, 0, {RA, RS, RB}}, RA 6053 arch/powerpc/xmon/ppc-opc.c {"srad", XRC(31,794,0), X_MASK, PPC64, 0, {RA, RS, RB}}, RA 6054 arch/powerpc/xmon/ppc-opc.c {"srad.", XRC(31,794,1), X_MASK, PPC64, 0, {RA, RS, RB}}, RA 6056 arch/powerpc/xmon/ppc-opc.c {"lfddx", X(31,803), X_MASK, E500MC, 0, {FRT, RA, RB}}, RA 6065 arch/powerpc/xmon/ppc-opc.c {"tabortdc.", XRC(31,814,1), X_MASK, PPCHTM, 0, {TO, RA, RB}}, RA 6067 arch/powerpc/xmon/ppc-opc.c {"rac", X(31,818), X_MASK, M601, 0, {RT, RA, RB}}, RA 6075 arch/powerpc/xmon/ppc-opc.c {"lfqux", X(31,823), X_MASK, POWER2, 0, {FRT, RA, RB}}, RA 6077 arch/powerpc/xmon/ppc-opc.c {"srawi", XRC(31,824,0), X_MASK, PPCCOM, 0, {RA, RS, SH}}, RA 6078 arch/powerpc/xmon/ppc-opc.c {"srai", XRC(31,824,0), X_MASK, PWRCOM, 0, {RA, RS, SH}}, RA 6079 arch/powerpc/xmon/ppc-opc.c {"srawi.", XRC(31,824,1), X_MASK, PPCCOM, 0, {RA, RS, SH}}, RA 6080 arch/powerpc/xmon/ppc-opc.c {"srai.", XRC(31,824,1), X_MASK, PWRCOM, 0, {RA, RS, SH}}, RA 6082 arch/powerpc/xmon/ppc-opc.c {"sradi", XS(31,413,0), XS_MASK, PPC64, 0, {RA, RS, SH6}}, RA 6083 arch/powerpc/xmon/ppc-opc.c {"sradi.", XS(31,413,1), XS_MASK, PPC64, 0, {RA, RS, SH6}}, RA 6089 arch/powerpc/xmon/ppc-opc.c {"divo", XO(31,331,1,0), XO_MASK, M601, 0, {RT, RA, RB}}, RA 6090 arch/powerpc/xmon/ppc-opc.c {"divo.", XO(31,331,1,1), XO_MASK, M601, 0, {RT, RA, RB}}, RA 6095 arch/powerpc/xmon/ppc-opc.c {"tabortwci.", XRC(31,846,1), X_MASK, PPCHTM, 0, {TO, RA, HTM_SI}}, RA 6114 arch/powerpc/xmon/ppc-opc.c {"abso", XO(31,360,1,0), XORB_MASK, M601, 0, {RT, RA}}, RA 6115 arch/powerpc/xmon/ppc-opc.c {"abso.", XO(31,360,1,1), XORB_MASK, M601, 0, {RT, RA}}, RA 6117 arch/powerpc/xmon/ppc-opc.c {"divso", XO(31,363,1,0), XO_MASK, M601, 0, {RT, RA, RB}}, RA 6118 arch/powerpc/xmon/ppc-opc.c {"divso.", XO(31,363,1,1), XO_MASK, M601, 0, {RT, RA, RB}}, RA 6122 arch/powerpc/xmon/ppc-opc.c {"tabortdci.", XRC(31,878,1), X_MASK, PPCHTM, 0, {TO, RA, HTM_SI}}, RA 6132 arch/powerpc/xmon/ppc-opc.c {"extswsli", XS(31,445,0), XS_MASK, POWER9, 0, {RA, RS, SH6}}, RA 6133 arch/powerpc/xmon/ppc-opc.c {"extswsli.", XS(31,445,1), XS_MASK, POWER9, 0, {RA, RS, SH6}}, RA 6138 arch/powerpc/xmon/ppc-opc.c {"stdfcmux", APU(31,903,0), APU_MASK, PPC405, 0, {FCRT, RA, RB}}, RA 6140 arch/powerpc/xmon/ppc-opc.c {"divdeuo", XO(31,393,1,0), XO_MASK, POWER7|PPCA2, 0, {RT, RA, RB}}, RA 6141 arch/powerpc/xmon/ppc-opc.c {"divdeuo.", XO(31,393,1,1), XO_MASK, POWER7|PPCA2, 0, {RT, RA, RB}}, RA 6142 arch/powerpc/xmon/ppc-opc.c {"divweuo", XO(31,395,1,0), XO_MASK, POWER7|PPCA2, 0, {RT, RA, RB}}, RA 6143 arch/powerpc/xmon/ppc-opc.c {"divweuo.", XO(31,395,1,1), XO_MASK, POWER7|PPCA2, 0, {RT, RA, RB}}, RA 6148 arch/powerpc/xmon/ppc-opc.c {"tabort.", XRC(31,910,1), XRTRB_MASK, PPCHTM, 0, {RA}}, RA 6163 arch/powerpc/xmon/ppc-opc.c {"sraq", XRC(31,920,0), X_MASK, M601, 0, {RA, RS, RB}}, RA 6164 arch/powerpc/xmon/ppc-opc.c {"sraq.", XRC(31,920,1), X_MASK, M601, 0, {RA, RS, RB}}, RA 6166 arch/powerpc/xmon/ppc-opc.c {"srea", XRC(31,921,0), X_MASK, M601, 0, {RA, RS, RB}}, RA 6167 arch/powerpc/xmon/ppc-opc.c {"srea.", XRC(31,921,1), X_MASK, M601, 0, {RA, RS, RB}}, RA 6169 arch/powerpc/xmon/ppc-opc.c {"extsh", XRC(31,922,0), XRB_MASK, PPCCOM, 0, {RA, RS}}, RA 6170 arch/powerpc/xmon/ppc-opc.c {"exts", XRC(31,922,0), XRB_MASK, PWRCOM, 0, {RA, RS}}, RA 6171 arch/powerpc/xmon/ppc-opc.c {"extsh.", XRC(31,922,1), XRB_MASK, PPCCOM, 0, {RA, RS}}, RA 6172 arch/powerpc/xmon/ppc-opc.c {"exts.", XRC(31,922,1), XRB_MASK, PWRCOM, 0, {RA, RS}}, RA 6174 arch/powerpc/xmon/ppc-opc.c {"stfddx", X(31,931), X_MASK, E500MC, 0, {FRS, RA, RB}}, RA 6184 arch/powerpc/xmon/ppc-opc.c {"divdeo", XO(31,425,1,0), XO_MASK, POWER7|PPCA2, 0, {RT, RA, RB}}, RA 6185 arch/powerpc/xmon/ppc-opc.c {"divdeo.", XO(31,425,1,1), XO_MASK, POWER7|PPCA2, 0, {RT, RA, RB}}, RA 6186 arch/powerpc/xmon/ppc-opc.c {"divweo", XO(31,427,1,0), XO_MASK, POWER7|PPCA2, 0, {RT, RA, RB}}, RA 6187 arch/powerpc/xmon/ppc-opc.c {"divweo.", XO(31,427,1,1), XO_MASK, POWER7|PPCA2, 0, {RT, RA, RB}}, RA 6192 arch/powerpc/xmon/ppc-opc.c {"treclaim.", XRC(31,942,1), XRTRB_MASK, PPCHTM, 0, {RA}}, RA 6194 arch/powerpc/xmon/ppc-opc.c {"tlbrehi", XTLB(31,946,0), XTLB_MASK, PPC403, PPCA2, {RT, RA}}, RA 6195 arch/powerpc/xmon/ppc-opc.c {"tlbrelo", XTLB(31,946,1), XTLB_MASK, PPC403, PPCA2, {RT, RA}}, RA 6200 arch/powerpc/xmon/ppc-opc.c {"icswepx", XRC(31,950,0), X_MASK, PPCA2, 0, {RS, RA, RB}}, RA 6201 arch/powerpc/xmon/ppc-opc.c {"icswepx.", XRC(31,950,1), X_MASK, PPCA2, 0, {RS, RA, RB}}, RA 6203 arch/powerpc/xmon/ppc-opc.c {"stfqux", X(31,951), X_MASK, POWER2, 0, {FRS, RA, RB}}, RA 6205 arch/powerpc/xmon/ppc-opc.c {"sraiq", XRC(31,952,0), X_MASK, M601, 0, {RA, RS, SH}}, RA 6206 arch/powerpc/xmon/ppc-opc.c {"sraiq.", XRC(31,952,1), X_MASK, M601, 0, {RA, RS, SH}}, RA 6208 arch/powerpc/xmon/ppc-opc.c {"extsb", XRC(31,954,0), XRB_MASK, PPC, 0, {RA, RS}}, RA 6209 arch/powerpc/xmon/ppc-opc.c {"extsb.", XRC(31,954,1), XRB_MASK, PPC, 0, {RA, RS}}, RA 6216 arch/powerpc/xmon/ppc-opc.c {"divduo", XO(31,457,1,0), XO_MASK, PPC64, 0, {RT, RA, RB}}, RA 6217 arch/powerpc/xmon/ppc-opc.c {"divduo.", XO(31,457,1,1), XO_MASK, PPC64, 0, {RT, RA, RB}}, RA 6219 arch/powerpc/xmon/ppc-opc.c {"divwuo", XO(31,459,1,0), XO_MASK, PPC, 0, {RT, RA, RB}}, RA 6220 arch/powerpc/xmon/ppc-opc.c {"divwuo.", XO(31,459,1,1), XO_MASK, PPC, 0, {RT, RA, RB}}, RA 6226 arch/powerpc/xmon/ppc-opc.c {"tlbwehi", XTLB(31,978,0), XTLB_MASK, PPC403, 0, {RT, RA}}, RA 6227 arch/powerpc/xmon/ppc-opc.c {"tlbwelo", XTLB(31,978,1), XTLB_MASK, PPC403, 0, {RT, RA}}, RA 6238 arch/powerpc/xmon/ppc-opc.c {"extsw", XRC(31,986,0), XRB_MASK, PPC64, 0, {RA, RS}}, RA 6239 arch/powerpc/xmon/ppc-opc.c {"extsw.", XRC(31,986,1), XRB_MASK, PPC64, 0, {RA, RS}}, RA 6247 arch/powerpc/xmon/ppc-opc.c {"nabso", XO(31,488,1,0), XORB_MASK, M601, 0, {RT, RA}}, RA 6248 arch/powerpc/xmon/ppc-opc.c {"nabso.", XO(31,488,1,1), XORB_MASK, M601, 0, {RT, RA}}, RA 6250 arch/powerpc/xmon/ppc-opc.c {"divdo", XO(31,489,1,0), XO_MASK, PPC64, 0, {RT, RA, RB}}, RA 6251 arch/powerpc/xmon/ppc-opc.c {"divdo.", XO(31,489,1,1), XO_MASK, PPC64, 0, {RT, RA, RB}}, RA 6253 arch/powerpc/xmon/ppc-opc.c {"divwo", XO(31,491,1,0), XO_MASK, PPC, 0, {RT, RA, RB}}, RA 6254 arch/powerpc/xmon/ppc-opc.c {"divwo.", XO(31,491,1,1), XO_MASK, PPC, 0, {RT, RA, RB}}, RA 6275 arch/powerpc/xmon/ppc-opc.c {"dstt", XDSS(31,342,1), XDSS_MASK, PPCVEC, 0, {RA, RB, STRM}}, RA 6276 arch/powerpc/xmon/ppc-opc.c {"dststt", XDSS(31,374,1), XDSS_MASK, PPCVEC, 0, {RA, RB, STRM}}, RA 6339 arch/powerpc/xmon/ppc-opc.c {"psq_l", OP(56), OP_MASK, PPCPS, PPCVLE, {FRT,PSD,RA,PSW,PSQ}}, RA 6345 arch/powerpc/xmon/ppc-opc.c {"psq_lu", OP(57), OP_MASK, PPCPS, PPCVLE, {FRT,PSD,RA,PSW,PSQ}}, RA 6636 arch/powerpc/xmon/ppc-opc.c {"xsiexpdp", X(60,918), XX1_MASK, PPCVSX3, PPCVLE, {XT6, RA, RB}}, RA 6662 arch/powerpc/xmon/ppc-opc.c {"psq_st", OP(60), OP_MASK, PPCPS, PPCVLE, {FRS,PSD,RA,PSW,PSQ}}, RA 6663 arch/powerpc/xmon/ppc-opc.c {"stfq", OP(60), OP_MASK, POWER2, PPCVLE, {FRS, D, RA}}, RA 6670 arch/powerpc/xmon/ppc-opc.c {"psq_stu", OP(61), OP_MASK, PPCPS, PPCVLE, {FRS,PSD,RA,PSW,PSQ}}, RA 6671 arch/powerpc/xmon/ppc-opc.c {"stfqu", OP(61), OP_MASK, POWER2, PPCVLE, {FRS, D, RA}}, RA 7012 arch/powerpc/xmon/ppc-opc.c {"e_cmpi", SCI8BF(6,0,21), SCI8BF_MASK, PPCVLE, 0, {CRD32, RA, SCLSCI8}}, RA 7013 arch/powerpc/xmon/ppc-opc.c {"e_cmpwi", SCI8BF(6,0,21), SCI8BF_MASK, PPCVLE, 0, {CRD32, RA, SCLSCI8}}, RA 7014 arch/powerpc/xmon/ppc-opc.c {"e_cmpli", SCI8BF(6,1,21), SCI8BF_MASK, PPCVLE, 0, {CRD32, RA, SCLSCI8}}, RA 7015 arch/powerpc/xmon/ppc-opc.c {"e_cmplwi", SCI8BF(6,1,21), SCI8BF_MASK, PPCVLE, 0, {CRD32, RA, SCLSCI8}}, RA 7016 arch/powerpc/xmon/ppc-opc.c {"e_addi", SCI8(6,16), SCI8_MASK, PPCVLE, 0, {RT, RA, SCLSCI8}}, RA 7017 arch/powerpc/xmon/ppc-opc.c {"e_subi", SCI8(6,16), SCI8_MASK, PPCVLE, 0, {RT, RA, SCLSCI8N}}, RA 7018 arch/powerpc/xmon/ppc-opc.c {"e_addi.", SCI8(6,17), SCI8_MASK, PPCVLE, 0, {RT, RA, SCLSCI8}}, RA 7019 arch/powerpc/xmon/ppc-opc.c {"e_addic", SCI8(6,18), SCI8_MASK, PPCVLE, 0, {RT, RA, SCLSCI8}}, RA 7020 arch/powerpc/xmon/ppc-opc.c {"e_subic", SCI8(6,18), SCI8_MASK, PPCVLE, 0, {RT, RA, SCLSCI8N}}, RA 7021 arch/powerpc/xmon/ppc-opc.c {"e_addic.", SCI8(6,19), SCI8_MASK, PPCVLE, 0, {RT, RA, SCLSCI8}}, RA 7022 arch/powerpc/xmon/ppc-opc.c {"e_subic.", SCI8(6,19), SCI8_MASK, PPCVLE, 0, {RT, RA, SCLSCI8N}}, RA 7023 arch/powerpc/xmon/ppc-opc.c {"e_mulli", SCI8(6,20), SCI8_MASK, PPCVLE, 0, {RT, RA, SCLSCI8}}, RA 7024 arch/powerpc/xmon/ppc-opc.c {"e_subfic", SCI8(6,22), SCI8_MASK, PPCVLE, 0, {RT, RA, SCLSCI8}}, RA 7025 arch/powerpc/xmon/ppc-opc.c {"e_subfic.", SCI8(6,23), SCI8_MASK, PPCVLE, 0, {RT, RA, SCLSCI8}}, RA 7026 arch/powerpc/xmon/ppc-opc.c {"e_andi", SCI8(6,24), SCI8_MASK, PPCVLE, 0, {RA, RS, SCLSCI8}}, RA 7027 arch/powerpc/xmon/ppc-opc.c {"e_andi.", SCI8(6,25), SCI8_MASK, PPCVLE, 0, {RA, RS, SCLSCI8}}, RA 7029 arch/powerpc/xmon/ppc-opc.c {"e_ori", SCI8(6,26), SCI8_MASK, PPCVLE, 0, {RA, RS, SCLSCI8}}, RA 7030 arch/powerpc/xmon/ppc-opc.c {"e_ori.", SCI8(6,27), SCI8_MASK, PPCVLE, 0, {RA, RS, SCLSCI8}}, RA 7031 arch/powerpc/xmon/ppc-opc.c {"e_xori", SCI8(6,28), SCI8_MASK, PPCVLE, 0, {RA, RS, SCLSCI8}}, RA 7032 arch/powerpc/xmon/ppc-opc.c {"e_xori.", SCI8(6,29), SCI8_MASK, PPCVLE, 0, {RA, RS, SCLSCI8}}, RA 7052 arch/powerpc/xmon/ppc-opc.c {"e_add16i", OP(7), OP_MASK, PPCVLE, 0, {RT, RA, SI}}, RA 7054 arch/powerpc/xmon/ppc-opc.c {"e_sub16i", OP(7), OP_MASK, PPCVLE, 0, {RT, RA, NSI}}, RA 7096 arch/powerpc/xmon/ppc-opc.c {"e_cmphl16i", IA16(28,23), IA16_MASK, PPCVLE, 0, {RA, VLEUIMM}}, RA 7097 arch/powerpc/xmon/ppc-opc.c {"e_cmph16i", IA16(28,22), IA16_MASK, PPCVLE, 0, {RA, VLESIMM}}, RA 7098 arch/powerpc/xmon/ppc-opc.c {"e_cmpl16i", I16A(28,21), I16A_MASK, PPCVLE, 0, {RA, VLEUIMM}}, RA 7099 arch/powerpc/xmon/ppc-opc.c {"e_mull2i", I16A(28,20), I16A_MASK, PPCVLE, 0, {RA, VLESIMM}}, RA 7100 arch/powerpc/xmon/ppc-opc.c {"e_cmp16i", IA16(28,19), IA16_MASK, PPCVLE, 0, {RA, VLESIMM}}, RA 7101 arch/powerpc/xmon/ppc-opc.c {"e_sub2is", I16A(28,18), I16A_MASK, PPCVLE, 0, {RA, VLENSIMM}}, RA 7102 arch/powerpc/xmon/ppc-opc.c {"e_add2is", I16A(28,18), I16A_MASK, PPCVLE, 0, {RA, VLESIMM}}, RA 7103 arch/powerpc/xmon/ppc-opc.c {"e_sub2i.", I16A(28,17), I16A_MASK, PPCVLE, 0, {RA, VLENSIMM}}, RA 7104 arch/powerpc/xmon/ppc-opc.c {"e_add2i.", I16A(28,17), I16A_MASK, PPCVLE, 0, {RA, VLESIMM}}, RA 7106 arch/powerpc/xmon/ppc-opc.c {"e_rlwimi", M(29,0), M_MASK, PPCVLE, 0, {RA, RS, SH, MB, ME}}, RA 7107 arch/powerpc/xmon/ppc-opc.c {"e_rlwinm", M(29,1), M_MASK, PPCVLE, 0, {RA, RT, SH, MBE, ME}}, RA 7146 arch/powerpc/xmon/ppc-opc.c {"e_cmph", X(31,14), X_MASK, PPCVLE, 0, {CRD, RA, RB}}, RA 7147 arch/powerpc/xmon/ppc-opc.c {"e_cmphl", X(31,46), X_MASK, PPCVLE, 0, {CRD, RA, RB}}, RA 7155 arch/powerpc/xmon/ppc-opc.c {"e_slwi", EX(31,112), EX_MASK, PPCVLE, 0, {RA, RS, SH}}, RA 7156 arch/powerpc/xmon/ppc-opc.c {"e_slwi.", EX(31,113), EX_MASK, PPCVLE, 0, {RA, RS, SH}}, RA 7160 arch/powerpc/xmon/ppc-opc.c {"e_rlw", EX(31,560), EX_MASK, PPCVLE, 0, {RA, RS, RB}}, RA 7161 arch/powerpc/xmon/ppc-opc.c {"e_rlw.", EX(31,561), EX_MASK, PPCVLE, 0, {RA, RS, RB}}, RA 7166 arch/powerpc/xmon/ppc-opc.c {"e_rlwi", EX(31,624), EX_MASK, PPCVLE, 0, {RA, RS, SH}}, RA 7167 arch/powerpc/xmon/ppc-opc.c {"e_rlwi.", EX(31,625), EX_MASK, PPCVLE, 0, {RA, RS, SH}}, RA 7176 arch/powerpc/xmon/ppc-opc.c {"e_srwi", EX(31,1136), EX_MASK, PPCVLE, 0, {RA, RS, SH}}, RA 7177 arch/powerpc/xmon/ppc-opc.c {"e_srwi.", EX(31,1137), EX_MASK, PPCVLE, 0, {RA, RS, SH}}, RA 93 drivers/clocksource/timer-atmel-tcb.c writel(0, tcaddr + ATMEL_TC_REG(i, RA)); RA 316 drivers/clocksource/timer-atmel-tcb.c writel(0x0000, tcaddr + ATMEL_TC_REG(0, RA)); RA 91 drivers/media/platform/coda/coda-gdi.c RBC(CA, 15, RA, 0), RA 92 drivers/media/platform/coda/coda-gdi.c RBC(RA, 0, RA, 1), RA 93 drivers/media/platform/coda/coda-gdi.c RBC(RA, 1, RA, 2), RA 94 drivers/media/platform/coda/coda-gdi.c RBC(RA, 2, RA, 3), RA 95 drivers/media/platform/coda/coda-gdi.c RBC(RA, 3, RA, 4), RA 96 drivers/media/platform/coda/coda-gdi.c RBC(RA, 4, RA, 5), RA 97 drivers/media/platform/coda/coda-gdi.c RBC(RA, 5, RA, 6), RA 98 drivers/media/platform/coda/coda-gdi.c RBC(RA, 6, RA, 7), RA 99 drivers/media/platform/coda/coda-gdi.c RBC(RA, 7, RA, 8), RA 100 drivers/media/platform/coda/coda-gdi.c RBC(RA, 8, RA, 9), RA 101 drivers/media/platform/coda/coda-gdi.c RBC(RA, 9, RA, 10), RA 102 drivers/media/platform/coda/coda-gdi.c RBC(RA, 10, RA, 11), RA 103 drivers/media/platform/coda/coda-gdi.c RBC(RA, 11, RA, 12), RA 104 drivers/media/platform/coda/coda-gdi.c RBC(RA, 12, RA, 13), RA 105 drivers/media/platform/coda/coda-gdi.c RBC(RA, 13, RA, 14), RA 106 drivers/media/platform/coda/coda-gdi.c RBC(RA, 14, RA, 15), RA 107 drivers/media/platform/coda/coda-gdi.c RBC(RA, 15, ZERO, 0), RA 1294 drivers/net/ethernet/amd/xgbe/xgbe-dev.c XGMAC_SET_BITS(mdio_sca, MAC_MDIOSCAR, RA, reg); RA 771 drivers/net/ethernet/intel/e1000/e1000_ethtool.c REG_PATTERN_TEST(RA + (((i << 1) + 1) << 2), RA 4290 drivers/net/ethernet/intel/e1000/e1000_hw.c E1000_WRITE_REG_ARRAY(hw, RA, (i << 1), 0); RA 4292 drivers/net/ethernet/intel/e1000/e1000_hw.c E1000_WRITE_REG_ARRAY(hw, RA, ((i << 1) + 1), 0); RA 4378 drivers/net/ethernet/intel/e1000/e1000_hw.c E1000_WRITE_REG_ARRAY(hw, RA, (index << 1), rar_low); RA 4380 drivers/net/ethernet/intel/e1000/e1000_hw.c E1000_WRITE_REG_ARRAY(hw, RA, ((index << 1) + 1), rar_high); RA 2302 drivers/net/ethernet/intel/e1000/e1000_main.c E1000_WRITE_REG_ARRAY(hw, RA, i << 1, 0); RA 2304 drivers/net/ethernet/intel/e1000/e1000_main.c E1000_WRITE_REG_ARRAY(hw, RA, (i << 1) + 1, 0); RA 390 drivers/net/ethernet/intel/ixgb/ixgb_hw.c IXGB_WRITE_REG_ARRAY(hw, RA, ((i << 1) + 1), 0); RA 391 drivers/net/ethernet/intel/ixgb/ixgb_hw.c IXGB_WRITE_REG_ARRAY(hw, RA, (i << 1), 0); RA 427 drivers/net/ethernet/intel/ixgb/ixgb_hw.c IXGB_WRITE_REG_ARRAY(hw, RA, (i << 1), 0); RA 428 drivers/net/ethernet/intel/ixgb/ixgb_hw.c IXGB_WRITE_REG_ARRAY(hw, RA, ((i << 1) + 1), 0); RA 573 drivers/net/ethernet/intel/ixgb/ixgb_hw.c IXGB_WRITE_REG_ARRAY(hw, RA, (index << 1), rar_low); RA 574 drivers/net/ethernet/intel/ixgb/ixgb_hw.c IXGB_WRITE_REG_ARRAY(hw, RA, ((index << 1) + 1), rar_high); RA 109 drivers/pwm/pwm-atmel-tcb.c __raw_readl(regs + ATMEL_TC_REG(group, RA)); RA 269 drivers/pwm/pwm-atmel-tcb.c __raw_writel(tcbpwm->duty, regs + ATMEL_TC_REG(group, RA)); RA 471 drivers/pwm/pwm-atmel-tcb.c chan->ra = readl(base + ATMEL_TC_REG(i, RA)); RA 488 drivers/pwm/pwm-atmel-tcb.c writel(chan->ra, base + ATMEL_TC_REG(i, RA)); RA 22 tools/perf/arch/riscv/util/unwind-libdw.c dwarf_regs[1] = REG(RA); RA 9 tools/testing/selftests/powerpc/include/instructions.h #define __COPY(RA, RB, L) \ RA 10 tools/testing/selftests/powerpc/include/instructions.h (0x7c00060c | (RA) << (31-15) | (RB) << (31-20) | (L) << (31-10)) RA 11 tools/testing/selftests/powerpc/include/instructions.h #define COPY(RA, RB, L) \ RA 12 tools/testing/selftests/powerpc/include/instructions.h .long __COPY((RA), (RB), (L)) RA 33 tools/testing/selftests/powerpc/include/instructions.h #define __PASTE(RA, RB, L, RC) \ RA 34 tools/testing/selftests/powerpc/include/instructions.h (0x7c00070c | (RA) << (31-15) | (RB) << (31-20) | (L) << (31-10) | (RC) << (31-31)) RA 35 tools/testing/selftests/powerpc/include/instructions.h #define PASTE(RA, RB, L, RC) \ RA 36 tools/testing/selftests/powerpc/include/instructions.h .long __PASTE((RA), (RB), (L), (RC))