R300_PPLL_REF_DIV_ACC_MASK  202 drivers/gpu/drm/radeon/radeon_clocks.c 						(tmp & R300_PPLL_REF_DIV_ACC_MASK) >> R300_PPLL_REF_DIV_ACC_SHIFT;
R300_PPLL_REF_DIV_ACC_MASK  967 drivers/gpu/drm/radeon/radeon_legacy_crtc.c 			if (pll_ref_div & R300_PPLL_REF_DIV_ACC_MASK) {
R300_PPLL_REF_DIV_ACC_MASK  978 drivers/gpu/drm/radeon/radeon_legacy_crtc.c 					     ~R300_PPLL_REF_DIV_ACC_MASK);
R300_PPLL_REF_DIV_ACC_MASK 1406 drivers/video/fbdev/aty/radeon_base.c 		if (mode->ppll_ref_div & R300_PPLL_REF_DIV_ACC_MASK) {
R300_PPLL_REF_DIV_ACC_MASK 1415 drivers/video/fbdev/aty/radeon_base.c 				~R300_PPLL_REF_DIV_ACC_MASK);