R128_READ          60 drivers/gpu/drm/r128/r128_cce.c 	return R128_READ(R128_CLOCK_CNTL_DATA);
R128_READ          67 drivers/gpu/drm/r128/r128_cce.c 	       (unsigned int)R128_READ(R128_GUI_STAT));
R128_READ          69 drivers/gpu/drm/r128/r128_cce.c 	       (unsigned int)R128_READ(R128_PM4_STAT));
R128_READ          71 drivers/gpu/drm/r128/r128_cce.c 	       (unsigned int)R128_READ(R128_PM4_BUFFER_DL_WPTR));
R128_READ          73 drivers/gpu/drm/r128/r128_cce.c 	       (unsigned int)R128_READ(R128_PM4_BUFFER_DL_RPTR));
R128_READ          75 drivers/gpu/drm/r128/r128_cce.c 	       (unsigned int)R128_READ(R128_PM4_MICRO_CNTL));
R128_READ          77 drivers/gpu/drm/r128/r128_cce.c 	       (unsigned int)R128_READ(R128_PM4_BUFFER_CNTL));
R128_READ          90 drivers/gpu/drm/r128/r128_cce.c 	tmp = R128_READ(R128_PC_NGUI_CTLSTAT) | R128_PC_FLUSH_ALL;
R128_READ          94 drivers/gpu/drm/r128/r128_cce.c 		if (!(R128_READ(R128_PC_NGUI_CTLSTAT) & R128_PC_BUSY))
R128_READ         110 drivers/gpu/drm/r128/r128_cce.c 		int slots = R128_READ(R128_GUI_STAT) & R128_GUI_FIFOCNT_MASK;
R128_READ         131 drivers/gpu/drm/r128/r128_cce.c 		if (!(R128_READ(R128_GUI_STAT) & R128_GUI_ACTIVE)) {
R128_READ         202 drivers/gpu/drm/r128/r128_cce.c 	tmp = R128_READ(R128_PM4_BUFFER_DL_WPTR) | R128_PM4_BUFFER_DL_DONE;
R128_READ         214 drivers/gpu/drm/r128/r128_cce.c 			int pm4stat = R128_READ(R128_PM4_STAT);
R128_READ         241 drivers/gpu/drm/r128/r128_cce.c 	R128_READ(R128_PM4_BUFFER_ADDR);	/* as per the sample code */
R128_READ         280 drivers/gpu/drm/r128/r128_cce.c 	clock_cntl_index = R128_READ(R128_CLOCK_CNTL_INDEX);
R128_READ         286 drivers/gpu/drm/r128/r128_cce.c 	gen_reset_cntl = R128_READ(R128_GEN_RESET_CNTL);
R128_READ         290 drivers/gpu/drm/r128/r128_cce.c 	R128_READ(R128_GEN_RESET_CNTL);
R128_READ         292 drivers/gpu/drm/r128/r128_cce.c 	R128_READ(R128_GEN_RESET_CNTL);
R128_READ         342 drivers/gpu/drm/r128/r128_cce.c 	R128_READ(R128_PM4_BUFFER_ADDR);
R128_READ         345 drivers/gpu/drm/r128/r128_cce.c 	tmp = R128_READ(R128_BUS_CNTL) & ~R128_BUS_MASTER_DIS;
R128_READ         836 drivers/gpu/drm/r128/r128_cce.c 		u32 done_age = R128_READ(R128_LAST_DISPATCH_REG);
R128_READ          65 drivers/gpu/drm/r128/r128_drv.h #define GET_RING_HEAD(dev_priv)		R128_READ(R128_PM4_BUFFER_DL_RPTR)
R128_READ         532 drivers/gpu/drm/r128/r128_drv.h 	R128_READ(R128_PM4_BUFFER_DL_WPTR);				\
R128_READ          56 drivers/gpu/drm/r128/r128_irq.c 	status = R128_READ(R128_GEN_INT_STATUS);
R128_READ        1236 drivers/gpu/drm/r128/r128_state.c 	dev_priv->crtc_offset = R128_READ(R128_CRTC_OFFSET);
R128_READ        1237 drivers/gpu/drm/r128/r128_state.c 	dev_priv->crtc_offset_cntl = R128_READ(R128_CRTC_OFFSET_CNTL);