AVIVO_D1GRPH_UPDATE  121 drivers/gpu/drm/radeon/rs600.c 	u32 tmp = RREG32(AVIVO_D1GRPH_UPDATE + radeon_crtc->crtc_offset);
AVIVO_D1GRPH_UPDATE  126 drivers/gpu/drm/radeon/rs600.c 	WREG32(AVIVO_D1GRPH_UPDATE + radeon_crtc->crtc_offset, tmp);
AVIVO_D1GRPH_UPDATE  138 drivers/gpu/drm/radeon/rs600.c 		if (RREG32(AVIVO_D1GRPH_UPDATE + radeon_crtc->crtc_offset) & AVIVO_D1GRPH_SURFACE_UPDATE_PENDING)
AVIVO_D1GRPH_UPDATE  146 drivers/gpu/drm/radeon/rs600.c 	WREG32(AVIVO_D1GRPH_UPDATE + radeon_crtc->crtc_offset, tmp);
AVIVO_D1GRPH_UPDATE  154 drivers/gpu/drm/radeon/rs600.c 	return !!(RREG32(AVIVO_D1GRPH_UPDATE + radeon_crtc->crtc_offset) &
AVIVO_D1GRPH_UPDATE  366 drivers/gpu/drm/radeon/rv515.c 			tmp = RREG32(AVIVO_D1GRPH_UPDATE + crtc_offsets[i]);
AVIVO_D1GRPH_UPDATE  369 drivers/gpu/drm/radeon/rv515.c 				WREG32(AVIVO_D1GRPH_UPDATE + crtc_offsets[i], tmp);
AVIVO_D1GRPH_UPDATE  416 drivers/gpu/drm/radeon/rv515.c 			tmp = RREG32(AVIVO_D1GRPH_UPDATE + crtc_offsets[i]);
AVIVO_D1GRPH_UPDATE  419 drivers/gpu/drm/radeon/rv515.c 				WREG32(AVIVO_D1GRPH_UPDATE + crtc_offsets[i], tmp);
AVIVO_D1GRPH_UPDATE  427 drivers/gpu/drm/radeon/rv515.c 				tmp = RREG32(AVIVO_D1GRPH_UPDATE + crtc_offsets[i]);
AVIVO_D1GRPH_UPDATE  811 drivers/gpu/drm/radeon/rv770.c 	u32 tmp = RREG32(AVIVO_D1GRPH_UPDATE + radeon_crtc->crtc_offset);
AVIVO_D1GRPH_UPDATE  816 drivers/gpu/drm/radeon/rv770.c 	WREG32(AVIVO_D1GRPH_UPDATE + radeon_crtc->crtc_offset, tmp);
AVIVO_D1GRPH_UPDATE  835 drivers/gpu/drm/radeon/rv770.c 		if (RREG32(AVIVO_D1GRPH_UPDATE + radeon_crtc->crtc_offset) & AVIVO_D1GRPH_SURFACE_UPDATE_PENDING)
AVIVO_D1GRPH_UPDATE  843 drivers/gpu/drm/radeon/rv770.c 	WREG32(AVIVO_D1GRPH_UPDATE + radeon_crtc->crtc_offset, tmp);
AVIVO_D1GRPH_UPDATE  851 drivers/gpu/drm/radeon/rv770.c 	return !!(RREG32(AVIVO_D1GRPH_UPDATE + radeon_crtc->crtc_offset) &