AVIVO_D1CRTC_CONTROL 1594 drivers/gpu/drm/radeon/r600.c 		if (RREG32(AVIVO_D1CRTC_CONTROL + crtc_offsets[i]) & AVIVO_CRTC_EN) {
AVIVO_D1CRTC_CONTROL  688 drivers/gpu/drm/radeon/radeon_device.c 		reg = RREG32(AVIVO_D1CRTC_CONTROL) |
AVIVO_D1CRTC_CONTROL   97 drivers/gpu/drm/radeon/rs600.c 	if (!(RREG32(AVIVO_D1CRTC_CONTROL + crtc_offsets[crtc]) & AVIVO_CRTC_EN))
AVIVO_D1CRTC_CONTROL  327 drivers/gpu/drm/radeon/rs600.c 			tmp = RREG32(AVIVO_D1CRTC_CONTROL + radeon_crtc->crtc_offset);
AVIVO_D1CRTC_CONTROL  329 drivers/gpu/drm/radeon/rs600.c 			WREG32(AVIVO_D1CRTC_CONTROL + radeon_crtc->crtc_offset, tmp);
AVIVO_D1CRTC_CONTROL  345 drivers/gpu/drm/radeon/rs600.c 			tmp = RREG32(AVIVO_D1CRTC_CONTROL + radeon_crtc->crtc_offset);
AVIVO_D1CRTC_CONTROL  347 drivers/gpu/drm/radeon/rs600.c 			WREG32(AVIVO_D1CRTC_CONTROL + radeon_crtc->crtc_offset, tmp);
AVIVO_D1CRTC_CONTROL  310 drivers/gpu/drm/radeon/rv515.c 		crtc_enabled = RREG32(AVIVO_D1CRTC_CONTROL + crtc_offsets[i]) & AVIVO_CRTC_EN;
AVIVO_D1CRTC_CONTROL  313 drivers/gpu/drm/radeon/rv515.c 			tmp = RREG32(AVIVO_D1CRTC_CONTROL + crtc_offsets[i]);
AVIVO_D1CRTC_CONTROL  318 drivers/gpu/drm/radeon/rv515.c 				WREG32(AVIVO_D1CRTC_CONTROL + crtc_offsets[i], tmp);
AVIVO_D1CRTC_CONTROL  331 drivers/gpu/drm/radeon/rv515.c 			tmp = RREG32(AVIVO_D1CRTC_CONTROL + crtc_offsets[i]);
AVIVO_D1CRTC_CONTROL  333 drivers/gpu/drm/radeon/rv515.c 			WREG32(AVIVO_D1CRTC_CONTROL + crtc_offsets[i], tmp);
AVIVO_D1CRTC_CONTROL  452 drivers/gpu/drm/radeon/rv515.c 			tmp = RREG32(AVIVO_D1CRTC_CONTROL + crtc_offsets[i]);
AVIVO_D1CRTC_CONTROL  454 drivers/gpu/drm/radeon/rv515.c 			WREG32(AVIVO_D1CRTC_CONTROL + crtc_offsets[i], tmp);