AUX_SW_DATA       221 drivers/gpu/drm/amd/display/dc/dce/dce_aux.c 	value = REG_UPDATE_4(AUX_SW_DATA,
AUX_SW_DATA       225 drivers/gpu/drm/amd/display/dc/dce/dce_aux.c 			AUX_SW_DATA, COMPOSE_AUX_SW_DATA_16_20(request->action, request->address));
AUX_SW_DATA       227 drivers/gpu/drm/amd/display/dc/dce/dce_aux.c 	value = REG_SET_2(AUX_SW_DATA, value,
AUX_SW_DATA       229 drivers/gpu/drm/amd/display/dc/dce/dce_aux.c 			AUX_SW_DATA, COMPOSE_AUX_SW_DATA_8_15(request->address));
AUX_SW_DATA       231 drivers/gpu/drm/amd/display/dc/dce/dce_aux.c 	value = REG_SET(AUX_SW_DATA, value,
AUX_SW_DATA       232 drivers/gpu/drm/amd/display/dc/dce/dce_aux.c 			AUX_SW_DATA, COMPOSE_AUX_SW_DATA_0_7(request->address));
AUX_SW_DATA       235 drivers/gpu/drm/amd/display/dc/dce/dce_aux.c 		value = REG_SET(AUX_SW_DATA, value,
AUX_SW_DATA       236 drivers/gpu/drm/amd/display/dc/dce/dce_aux.c 				AUX_SW_DATA, request->length - 1);
AUX_SW_DATA       248 drivers/gpu/drm/amd/display/dc/dce/dce_aux.c 			value = REG_SET(AUX_SW_DATA, value,
AUX_SW_DATA       249 drivers/gpu/drm/amd/display/dc/dce/dce_aux.c 					AUX_SW_DATA, request->data[i]);
AUX_SW_DATA       279 drivers/gpu/drm/amd/display/dc/dce/dce_aux.c 	REG_UPDATE_SEQ_3(AUX_SW_DATA,
AUX_SW_DATA       284 drivers/gpu/drm/amd/display/dc/dce/dce_aux.c 	REG_GET(AUX_SW_DATA, AUX_SW_DATA, &reply_result_32);
AUX_SW_DATA       302 drivers/gpu/drm/amd/display/dc/dce/dce_aux.c 			REG_GET(AUX_SW_DATA, AUX_SW_DATA, &aux_sw_data_val);
AUX_SW_DATA        36 drivers/gpu/drm/amd/display/dc/dce/dce_aux.h 	SRI(AUX_SW_DATA, DP_AUX, id), \
AUX_SW_DATA        45 drivers/gpu/drm/amd/display/dc/dce/dce_aux.h 	SRI(AUX_SW_DATA, DP_AUX, id), \
AUX_SW_DATA        55 drivers/gpu/drm/amd/display/dc/dce/dce_aux.h 	uint32_t AUX_SW_DATA;
AUX_SW_DATA       121 drivers/gpu/drm/radeon/radeon_dp_auxch.c 	WREG32(AUX_SW_DATA + aux_offset[instance],
AUX_SW_DATA       125 drivers/gpu/drm/radeon/radeon_dp_auxch.c 	WREG32(AUX_SW_DATA + aux_offset[instance],
AUX_SW_DATA       129 drivers/gpu/drm/radeon/radeon_dp_auxch.c 	WREG32(AUX_SW_DATA + aux_offset[instance],
AUX_SW_DATA       133 drivers/gpu/drm/radeon/radeon_dp_auxch.c 	WREG32(AUX_SW_DATA + aux_offset[instance],
AUX_SW_DATA       139 drivers/gpu/drm/radeon/radeon_dp_auxch.c 			WREG32(AUX_SW_DATA + aux_offset[instance],
AUX_SW_DATA       179 drivers/gpu/drm/radeon/radeon_dp_auxch.c 		WREG32(AUX_SW_DATA + aux_offset[instance],
AUX_SW_DATA       182 drivers/gpu/drm/radeon/radeon_dp_auxch.c 		tmp = RREG32(AUX_SW_DATA + aux_offset[instance]);
AUX_SW_DATA       186 drivers/gpu/drm/radeon/radeon_dp_auxch.c 			tmp = RREG32(AUX_SW_DATA + aux_offset[instance]);