AUX_SW_CONTROL    216 drivers/gpu/drm/amd/display/dc/dce/dce_aux.c 	REG_UPDATE_2(AUX_SW_CONTROL,
AUX_SW_CONTROL    255 drivers/gpu/drm/amd/display/dc/dce/dce_aux.c 	REG_UPDATE(AUX_SW_CONTROL, AUX_SW_GO, 1);
AUX_SW_CONTROL     37 drivers/gpu/drm/amd/display/dc/dce/dce_aux.h 	SRI(AUX_SW_CONTROL, DP_AUX, id), \
AUX_SW_CONTROL     46 drivers/gpu/drm/amd/display/dc/dce/dce_aux.h 	SRI(AUX_SW_CONTROL, DP_AUX, id), \
AUX_SW_CONTROL     56 drivers/gpu/drm/amd/display/dc/dce/dce_aux.h 	uint32_t AUX_SW_CONTROL;
AUX_SW_CONTROL    113 drivers/gpu/drm/radeon/radeon_dp_auxch.c 	WREG32(AUX_SW_CONTROL + aux_offset[instance],
AUX_SW_CONTROL    115 drivers/gpu/drm/radeon/radeon_dp_auxch.c 	WREG32(AUX_SW_CONTROL + aux_offset[instance],
AUX_SW_CONTROL    148 drivers/gpu/drm/radeon/radeon_dp_auxch.c 	WREG32(AUX_SW_CONTROL + aux_offset[instance],