AUX_CONTROL 99 drivers/gpu/drm/amd/display/dc/dce/dce_aux.c value = REG_READ(AUX_CONTROL); AUX_CONTROL 101 drivers/gpu/drm/amd/display/dc/dce/dce_aux.c AUX_CONTROL, AUX_CONTROL 108 drivers/gpu/drm/amd/display/dc/dce/dce_aux.c AUX_CONTROL, AUX_CONTROL 116 drivers/gpu/drm/amd/display/dc/dce/dce_aux.c AUX_CONTROL, AUX_CONTROL 120 drivers/gpu/drm/amd/display/dc/dce/dce_aux.c REG_WRITE(AUX_CONTROL, value); AUX_CONTROL 125 drivers/gpu/drm/amd/display/dc/dce/dce_aux.c REG_WAIT(AUX_CONTROL, AUX_RESET_DONE, 1, AUX_CONTROL 131 drivers/gpu/drm/amd/display/dc/dce/dce_aux.c AUX_CONTROL, AUX_CONTROL 134 drivers/gpu/drm/amd/display/dc/dce/dce_aux.c REG_WRITE(AUX_CONTROL, value); AUX_CONTROL 136 drivers/gpu/drm/amd/display/dc/dce/dce_aux.c REG_WAIT(AUX_CONTROL, AUX_RESET_DONE, 0, AUX_CONTROL 34 drivers/gpu/drm/amd/display/dc/dce/dce_aux.h SRI(AUX_CONTROL, DP_AUX, id), \ AUX_CONTROL 43 drivers/gpu/drm/amd/display/dc/dce/dce_aux.h SRI(AUX_CONTROL, DP_AUX, id), \ AUX_CONTROL 53 drivers/gpu/drm/amd/display/dc/dce/dce_aux.h uint32_t AUX_CONTROL; AUX_CONTROL 497 drivers/gpu/drm/amd/display/dc/dce/dce_link_encoder.c uint32_t addr = AUX_REG(AUX_CONTROL); AUX_CONTROL 500 drivers/gpu/drm/amd/display/dc/dce/dce_link_encoder.c set_reg_field_value(value, hpd_source, AUX_CONTROL, AUX_HPD_SEL); AUX_CONTROL 501 drivers/gpu/drm/amd/display/dc/dce/dce_link_encoder.c set_reg_field_value(value, 0, AUX_CONTROL, AUX_LS_READ_EN); AUX_CONTROL 40 drivers/gpu/drm/amd/display/dc/dce/dce_link_encoder.h SRI(AUX_CONTROL, DP_AUX, id), \ AUX_CONTROL 108 drivers/gpu/drm/amd/display/dc/dce/dce_link_encoder.h uint32_t AUX_CONTROL; AUX_CONTROL 1393 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_link_encoder.c AUX_REG_UPDATE_2(AUX_CONTROL, AUX_CONTROL 36 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_link_encoder.h SRI(AUX_CONTROL, DP_AUX, id), \ AUX_CONTROL 73 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_link_encoder.h uint32_t AUX_CONTROL; AUX_CONTROL 104 drivers/gpu/drm/radeon/radeon_dp_auxch.c tmp = RREG32(AUX_CONTROL + aux_offset[instance]); AUX_CONTROL 110 drivers/gpu/drm/radeon/radeon_dp_auxch.c WREG32(AUX_CONTROL + aux_offset[instance], tmp);