QE_PIO_PINS 28 drivers/soc/fsl/qe/gpio.c unsigned long pin_flags[QE_PIO_PINS]; QE_PIO_PINS 57 drivers/soc/fsl/qe/gpio.c u32 pin_mask = 1 << (QE_PIO_PINS - 1 - gpio); QE_PIO_PINS 68 drivers/soc/fsl/qe/gpio.c u32 pin_mask = 1 << (QE_PIO_PINS - 1 - gpio); QE_PIO_PINS 98 drivers/soc/fsl/qe/gpio.c qe_gc->cpdata |= (1U << (QE_PIO_PINS - 1 - i)); QE_PIO_PINS 100 drivers/soc/fsl/qe/gpio.c qe_gc->cpdata &= ~(1U << (QE_PIO_PINS - 1 - i)); QE_PIO_PINS 250 drivers/soc/fsl/qe/gpio.c u32 mask1 = 1 << (QE_PIO_PINS - (pin + 1)); QE_PIO_PINS 251 drivers/soc/fsl/qe/gpio.c u32 mask2 = 0x3 << (QE_PIO_PINS - (pin % (QE_PIO_PINS / 2) + 1) * 2); QE_PIO_PINS 252 drivers/soc/fsl/qe/gpio.c bool second_reg = pin > (QE_PIO_PINS / 2) - 1; QE_PIO_PINS 321 drivers/soc/fsl/qe/gpio.c gc->ngpio = QE_PIO_PINS; QE_PIO_PINS 57 drivers/soc/fsl/qe/qe_io.c pin_mask1bit = (u32) (1 << (QE_PIO_PINS - (pin + 1))); QE_PIO_PINS 67 drivers/soc/fsl/qe/qe_io.c tmp_val = (pin > (QE_PIO_PINS / 2) - 1) ? QE_PIO_PINS 72 drivers/soc/fsl/qe/qe_io.c pin_mask2bits = (u32) (0x3 << (QE_PIO_PINS - QE_PIO_PINS 73 drivers/soc/fsl/qe/qe_io.c (pin % (QE_PIO_PINS / 2) + 1) * 2)); QE_PIO_PINS 76 drivers/soc/fsl/qe/qe_io.c new_mask2bits = (u32) (dir << (QE_PIO_PINS - QE_PIO_PINS 77 drivers/soc/fsl/qe/qe_io.c (pin % (QE_PIO_PINS / 2) + 1) * 2)); QE_PIO_PINS 80 drivers/soc/fsl/qe/qe_io.c if (pin > (QE_PIO_PINS / 2) - 1) { QE_PIO_PINS 92 drivers/soc/fsl/qe/qe_io.c tmp_val = (pin > (QE_PIO_PINS / 2) - 1) ? QE_PIO_PINS 96 drivers/soc/fsl/qe/qe_io.c new_mask2bits = (u32) (assignment << (QE_PIO_PINS - QE_PIO_PINS 97 drivers/soc/fsl/qe/qe_io.c (pin % (QE_PIO_PINS / 2) + 1) * 2)); QE_PIO_PINS 99 drivers/soc/fsl/qe/qe_io.c if (pin > (QE_PIO_PINS / 2) - 1) { QE_PIO_PINS 131 drivers/soc/fsl/qe/qe_io.c if (pin >= QE_PIO_PINS) QE_PIO_PINS 134 drivers/soc/fsl/qe/qe_io.c pin_mask = (u32) (1 << (QE_PIO_PINS - 1 - pin));