PXA_CS1_PHYS      189 arch/arm/mach-pxa/cm-x255.c 		.start = PXA_CS1_PHYS,
PXA_CS1_PHYS      190 arch/arm/mach-pxa/cm-x255.c 		.end   = PXA_CS1_PHYS + 11,
PXA_CS1_PHYS       29 arch/arm/mach-pxa/cm-x270.c #define RTC_PHYS_BASE		(PXA_CS1_PHYS + (5 << 22))
PXA_CS1_PHYS       54 arch/arm/mach-pxa/cm-x2xx.c #define CMX255_DM9000_PHYS_BASE (PXA_CS1_PHYS + (8 << 22))
PXA_CS1_PHYS       55 arch/arm/mach-pxa/cm-x2xx.c #define CMX270_DM9000_PHYS_BASE	(PXA_CS1_PHYS + (6 << 22))
PXA_CS1_PHYS      353 arch/arm/mach-pxa/em-x270.c 		.start = PXA_CS1_PHYS,
PXA_CS1_PHYS      354 arch/arm/mach-pxa/em-x270.c 		.end   = PXA_CS1_PHYS + 12,
PXA_CS1_PHYS       26 arch/arm/mach-pxa/idp.h #define IDP_ALT_FLASH_PHYS	(PXA_CS1_PHYS)
PXA_CS1_PHYS       81 arch/arm/mach-pxa/include/mach/palmtx.h #define PALMTX_PHYS_NAND_START	PXA_CS1_PHYS	/* ChipSelect 1 */
PXA_CS1_PHYS       18 arch/arm/mach-pxa/include/mach/trizeps4.h #define TRIZEPS4_DISK_PHYS	(PXA_CS1_PHYS)  /* Disk On Chip region */
PXA_CS1_PHYS      215 arch/arm/mach-pxa/lpd270.c 		.start	= PXA_CS1_PHYS,
PXA_CS1_PHYS      216 arch/arm/mach-pxa/lpd270.c 		.end	= PXA_CS1_PHYS + SZ_64M - 1,
PXA_CS1_PHYS      194 arch/arm/mach-pxa/mainstone.c 		.start	= PXA_CS1_PHYS,
PXA_CS1_PHYS      195 arch/arm/mach-pxa/mainstone.c 		.end	= PXA_CS1_PHYS + SZ_64M - 1,
PXA_CS1_PHYS      284 arch/arm/mach-pxa/palmtx.c 		.start	= PXA_CS1_PHYS,
PXA_CS1_PHYS      285 arch/arm/mach-pxa/palmtx.c 		.end	= PXA_CS1_PHYS + SZ_1M - 1,
PXA_CS1_PHYS       21 arch/arm/mach-pxa/pcm990_baseboard.h #define PCM990_CTRL_PHYS		PXA_CS1_PHYS	/* 16-Bit */
PXA_CS1_PHYS      764 arch/arm/mach-pxa/stargate2.c 	.start = PXA_CS1_PHYS,
PXA_CS1_PHYS      765 arch/arm/mach-pxa/stargate2.c 	.end = PXA_CS1_PHYS + SZ_32M-1,
PXA_CS1_PHYS       22 arch/arm/mach-pxa/viper.h #define VIPER_FLASH_PHYS	PXA_CS1_PHYS
PXA_CS1_PHYS       19 arch/arm/mach-pxa/zeus.h #define ZEUS_ETH0_PHYS		PXA_CS1_PHYS
PXA_CS1_PHYS      159 drivers/mtd/nand/raw/cmx270_nand.c 	cmx270_nand_io = ioremap(PXA_CS1_PHYS, 12);