PXA1928_CLK_UART1  101 drivers/clk/mmp/clk-of-pxa1928.c 	{0, "uart1_mux", uart_parent_names, ARRAY_SIZE(uart_parent_names), CLK_SET_RATE_PARENT, PXA1928_CLK_UART1 * 4, 4, 3, 0, &uart1_lock},
PXA1928_CLK_UART1  124 drivers/clk/mmp/clk-of-pxa1928.c 	{PXA1928_CLK_UART1, "uart1_clk", "uart1_mux", CLK_SET_RATE_PARENT, PXA1928_CLK_UART1 * 4, 0x3, 0x3, 0x0, 0, &uart1_lock},