PXA1928_CLK_UART0  100 drivers/clk/mmp/clk-of-pxa1928.c 	{0, "uart0_mux", uart_parent_names, ARRAY_SIZE(uart_parent_names), CLK_SET_RATE_PARENT, PXA1928_CLK_UART0 * 4, 4, 3, 0, &uart0_lock},
PXA1928_CLK_UART0  123 drivers/clk/mmp/clk-of-pxa1928.c 	{PXA1928_CLK_UART0, "uart0_clk", "uart0_mux", CLK_SET_RATE_PARENT, PXA1928_CLK_UART0 * 4, 0x3, 0x3, 0x0, 0, &uart0_lock},