PTE_T_LOG2         66 arch/mips/include/asm/pgtable-32.h # define PGDIR_SHIFT	(2 * PAGE_SHIFT + PTE_ORDER - PTE_T_LOG2 - 1)
PTE_T_LOG2         68 arch/mips/include/asm/pgtable-32.h # define PGDIR_SHIFT	(2 * PAGE_SHIFT + PTE_ORDER - PTE_T_LOG2)
PTE_T_LOG2         79 arch/mips/include/asm/pgtable-32.h # define __PGD_ORDER	(32 - 3 * PAGE_SHIFT + PGD_T_LOG2 + PTE_T_LOG2 + 1)
PTE_T_LOG2         81 arch/mips/include/asm/pgtable-32.h # define __PGD_ORDER	(32 - 3 * PAGE_SHIFT + PGD_T_LOG2 + PTE_T_LOG2)
PTE_T_LOG2        199 arch/mips/kernel/asm-offsets.c 	DEFINE(_PTE_T_LOG2, PTE_T_LOG2);
PTE_T_LOG2        998 arch/mips/mm/tlbex.c 	unsigned int shift = 4 - (PTE_T_LOG2 + 1) + PAGE_SHIFT - 12;
PTE_T_LOG2        999 arch/mips/mm/tlbex.c 	unsigned int mask = (PTRS_PER_PTE / 2 - 1) << (PTE_T_LOG2 + 1);
PTE_T_LOG2       2069 arch/mips/mm/tlbex.c 	UASM_i_SRL(p, wr.r1, wr.r1, PAGE_SHIFT + PTE_ORDER - PTE_T_LOG2);
PTE_T_LOG2       2070 arch/mips/mm/tlbex.c 	uasm_i_andi(p, wr.r1, wr.r1, (PTRS_PER_PTE - 1) << PTE_T_LOG2);
PTE_T_LOG2       2523 arch/mips/mm/tlbex.c 	pwsize |= ((PTE_T_LOG2 - PGD_T_LOG2) << MIPS_PWSIZE_PTEW_SHIFT)
PTE_T_LOG2        153 arch/powerpc/include/asm/nohash/32/mmu-44x.h #define PPC44x_PTE_ADD_SHIFT	(32 - PGDIR_SHIFT + PTE_SHIFT + PTE_T_LOG2)
PTE_T_LOG2        154 arch/powerpc/include/asm/nohash/32/mmu-44x.h #define PPC44x_PTE_ADD_MASK_BIT	(32 - PTE_T_LOG2 - PTE_SHIFT)
PTE_T_LOG2         27 arch/powerpc/include/asm/page_32.h #define PTE_SHIFT	(PAGE_SHIFT - PTE_T_LOG2 - 2)	/* 1/4 of a page */
PTE_T_LOG2         29 arch/powerpc/include/asm/page_32.h #define PTE_SHIFT	(PAGE_SHIFT - PTE_T_LOG2)	/* full page */
PTE_T_LOG2        733 arch/powerpc/kernel/asm-offsets.c 	DEFINE(PTE_T_LOG2, PTE_T_LOG2);