PT 31 arch/ia64/kernel/entry.h .spillsp rp, PT(CR_IIP)+16+(off); \ PT 32 arch/ia64/kernel/entry.h .spillsp ar.pfs, PT(CR_IFS)+16+(off); \ PT 33 arch/ia64/kernel/entry.h .spillsp ar.unat, PT(AR_UNAT)+16+(off); \ PT 34 arch/ia64/kernel/entry.h .spillsp ar.fpsr, PT(AR_FPSR)+16+(off); \ PT 35 arch/ia64/kernel/entry.h .spillsp pr, PT(PR)+16+(off); PT 944 arch/ia64/kernel/ivt.S #if PT(B6) != 0 PT 86 arch/ia64/kernel/minstate.h adds r16=PT(CR_IPSR),r1; \ PT 96 arch/ia64/kernel/minstate.h adds r16=PT(R8),r1; /* initialize first base pointer */ \ PT 97 arch/ia64/kernel/minstate.h adds r17=PT(R9),r1; /* initialize second base pointer */ \ PT 196 arch/ia64/kernel/minstate.h adds r24=PT(B6)-PT(F7),r3; \ PT 206 arch/ia64/kernel/minstate.h adds r25=PT(B7)-PT(F11),r3; \ PT 288 drivers/gpu/drm/nouveau/nvkm/subdev/mmu/vmm.h #define VMM_MAP_ITER(VMM,PT,PTEI,PTEN,MAP,FILL,BASE,SIZE,NEXT) do { \ PT 289 drivers/gpu/drm/nouveau/nvkm/subdev/mmu/vmm.h nvkm_kmap((PT)->memory); \ PT 304 drivers/gpu/drm/nouveau/nvkm/subdev/mmu/vmm.h FILL(VMM, PT, PTEI, _ptes, MAP, _addr); \ PT 308 drivers/gpu/drm/nouveau/nvkm/subdev/mmu/vmm.h nvkm_done((PT)->memory); \ PT 311 drivers/gpu/drm/nouveau/nvkm/subdev/mmu/vmm.h #define VMM_MAP_ITER_MEM(VMM,PT,PTEI,PTEN,MAP,FILL) \ PT 312 drivers/gpu/drm/nouveau/nvkm/subdev/mmu/vmm.h VMM_MAP_ITER(VMM,PT,PTEI,PTEN,MAP,FILL, \ PT 316 drivers/gpu/drm/nouveau/nvkm/subdev/mmu/vmm.h #define VMM_MAP_ITER_DMA(VMM,PT,PTEI,PTEN,MAP,FILL) \ PT 317 drivers/gpu/drm/nouveau/nvkm/subdev/mmu/vmm.h VMM_MAP_ITER(VMM,PT,PTEI,PTEN,MAP,FILL, \ PT 319 drivers/gpu/drm/nouveau/nvkm/subdev/mmu/vmm.h #define VMM_MAP_ITER_SGL(VMM,PT,PTEI,PTEN,MAP,FILL) \ PT 320 drivers/gpu/drm/nouveau/nvkm/subdev/mmu/vmm.h VMM_MAP_ITER(VMM,PT,PTEI,PTEN,MAP,FILL, \ PT 489 drivers/iio/temperature/mlx90632.c s32 PT, PR, PG, PO; PT 499 drivers/iio/temperature/mlx90632.c ret = mlx90632_read_ee_register(data->regmap, MLX90632_EE_P_T, &PT); PT 515 drivers/iio/temperature/mlx90632.c PT, PR, PG, PO, Gb); PT 591 drivers/net/ethernet/amd/xgbe/xgbe-dev.c XGMAC_SET_BITS(reg_val, MAC_Q0TFCR, PT, 0xffff);