PSB_INT_ENABLE_R  292 drivers/gpu/drm/gma500/cdv_device.c 	regs->cdv.saveIER = REG_READ(PSB_INT_ENABLE_R);
PSB_INT_ENABLE_R  361 drivers/gpu/drm/gma500/cdv_device.c 	REG_WRITE(PSB_INT_ENABLE_R, regs->cdv.saveIER);
PSB_INT_ENABLE_R  359 drivers/gpu/drm/gma500/psb_drv.c 	PSB_WVDC32(0x00000000, PSB_INT_ENABLE_R);
PSB_INT_ENABLE_R  111 drivers/gpu/drm/gma500/psb_irq.c 		PSB_WVDC32(dev_priv->vdc_irq_mask, PSB_INT_ENABLE_R);
PSB_INT_ENABLE_R  123 drivers/gpu/drm/gma500/psb_irq.c 			PSB_WVDC32(dev_priv->vdc_irq_mask, PSB_INT_ENABLE_R);
PSB_INT_ENABLE_R  310 drivers/gpu/drm/gma500/psb_irq.c 		PSB_WVDC32(0x00000000, PSB_INT_ENABLE_R);
PSB_INT_ENABLE_R  349 drivers/gpu/drm/gma500/psb_irq.c 	PSB_WVDC32(dev_priv->vdc_irq_mask, PSB_INT_ENABLE_R);
PSB_INT_ENABLE_R  401 drivers/gpu/drm/gma500/psb_irq.c 	PSB_WVDC32(dev_priv->vdc_irq_mask, PSB_INT_ENABLE_R);
PSB_INT_ENABLE_R  528 drivers/gpu/drm/gma500/psb_irq.c 	PSB_WVDC32(dev_priv->vdc_irq_mask, PSB_INT_ENABLE_R);
PSB_INT_ENABLE_R  554 drivers/gpu/drm/gma500/psb_irq.c 	PSB_WVDC32(dev_priv->vdc_irq_mask, PSB_INT_ENABLE_R);