PP_SMU_NUM_FCLK_DPM_LEVELS  475 drivers/gpu/drm/amd/display/dc/clk_mgr/dcn21/rn_clk_mgr.c 	ASSERT(PP_SMU_NUM_FCLK_DPM_LEVELS <= MAX_NUM_DPM_LVL);
PP_SMU_NUM_FCLK_DPM_LEVELS  477 drivers/gpu/drm/amd/display/dc/clk_mgr/dcn21/rn_clk_mgr.c 	for (i = 0; i < PP_SMU_NUM_FCLK_DPM_LEVELS; i++) {
PP_SMU_NUM_FCLK_DPM_LEVELS  269 drivers/gpu/drm/amd/display/dc/dm_pp_smu.h 	struct dpm_clock FClocks[PP_SMU_NUM_FCLK_DPM_LEVELS];