PP_SEQUENCE_STATE_MASK 2439 drivers/gpu/drm/i915/display/intel_dp.c #define IDLE_ON_MASK		(PP_ON | PP_SEQUENCE_MASK | 0                     | PP_SEQUENCE_STATE_MASK)
PP_SEQUENCE_STATE_MASK 2445 drivers/gpu/drm/i915/display/intel_dp.c #define IDLE_CYCLE_MASK		(PP_ON | PP_SEQUENCE_MASK | PP_CYCLE_DELAY_ACTIVE | PP_SEQUENCE_STATE_MASK)
PP_SEQUENCE_STATE_MASK 4735 drivers/gpu/drm/i915/i915_reg.h #define   PP_SEQUENCE_STATE_OFF_IDLE	REG_FIELD_PREP(PP_SEQUENCE_STATE_MASK, 0x0)
PP_SEQUENCE_STATE_MASK 4736 drivers/gpu/drm/i915/i915_reg.h #define   PP_SEQUENCE_STATE_OFF_S0_1	REG_FIELD_PREP(PP_SEQUENCE_STATE_MASK, 0x1)
PP_SEQUENCE_STATE_MASK 4737 drivers/gpu/drm/i915/i915_reg.h #define   PP_SEQUENCE_STATE_OFF_S0_2	REG_FIELD_PREP(PP_SEQUENCE_STATE_MASK, 0x2)
PP_SEQUENCE_STATE_MASK 4738 drivers/gpu/drm/i915/i915_reg.h #define   PP_SEQUENCE_STATE_OFF_S0_3	REG_FIELD_PREP(PP_SEQUENCE_STATE_MASK, 0x3)
PP_SEQUENCE_STATE_MASK 4739 drivers/gpu/drm/i915/i915_reg.h #define   PP_SEQUENCE_STATE_ON_IDLE	REG_FIELD_PREP(PP_SEQUENCE_STATE_MASK, 0x8)
PP_SEQUENCE_STATE_MASK 4740 drivers/gpu/drm/i915/i915_reg.h #define   PP_SEQUENCE_STATE_ON_S1_1	REG_FIELD_PREP(PP_SEQUENCE_STATE_MASK, 0x9)
PP_SEQUENCE_STATE_MASK 4741 drivers/gpu/drm/i915/i915_reg.h #define   PP_SEQUENCE_STATE_ON_S1_2	REG_FIELD_PREP(PP_SEQUENCE_STATE_MASK, 0xa)
PP_SEQUENCE_STATE_MASK 4742 drivers/gpu/drm/i915/i915_reg.h #define   PP_SEQUENCE_STATE_ON_S1_3	REG_FIELD_PREP(PP_SEQUENCE_STATE_MASK, 0xb)
PP_SEQUENCE_STATE_MASK 4743 drivers/gpu/drm/i915/i915_reg.h #define   PP_SEQUENCE_STATE_RESET	REG_FIELD_PREP(PP_SEQUENCE_STATE_MASK, 0xf)