PP_ON             418 drivers/gpu/drm/gma500/cdv_intel_dp.c 	u32 pp, idle_on_mask = PP_ON | PP_SEQUENCE_NONE;
PP_ON             444 drivers/gpu/drm/gma500/cdv_intel_dp.c 	u32 pp, idle_off_mask = PP_ON ;
PP_ON             200 drivers/gpu/drm/gma500/cdv_intel_lvds.c 		} while ((pp_status & PP_ON) == 0);
PP_ON             211 drivers/gpu/drm/gma500/cdv_intel_lvds.c 		} while (pp_status & PP_ON);
PP_ON              48 drivers/gpu/drm/gma500/oaktrail_lvds.c 		} while ((pp_status & (PP_ON | PP_READY)) == PP_READY);
PP_ON              59 drivers/gpu/drm/gma500/oaktrail_lvds.c 		} while (pp_status & PP_ON);
PP_ON             223 drivers/gpu/drm/gma500/psb_intel_lvds.c 		} while ((pp_status & PP_ON) == 0);
PP_ON             234 drivers/gpu/drm/gma500/psb_intel_lvds.c 		} while (pp_status & PP_ON);
PP_ON             323 drivers/gpu/drm/gma500/psb_intel_lvds.c 		} while ((pp_status & PP_ON) == 0);
PP_ON             329 drivers/gpu/drm/gma500/psb_intel_lvds.c 		} while (pp_status & PP_ON);
PP_ON              31 drivers/gpu/drm/gma500/psb_lid.c 		} while ((pp_status & PP_ON) == 0 &&
PP_ON              34 drivers/gpu/drm/gma500/psb_lid.c 		if (REG_READ(PP_STATUS) & PP_ON) {
PP_ON              47 drivers/gpu/drm/gma500/psb_lid.c 		} while ((pp_status & PP_ON) == 0);
PP_ON            4261 drivers/gpu/drm/i915/display/intel_display_power.c 	I915_STATE_WARN(I915_READ(PP_STATUS(0)) & PP_ON,
PP_ON             906 drivers/gpu/drm/i915/display/intel_dp.c 	return I915_READ(PP_STATUS(pipe)) & PP_ON;
PP_ON            1110 drivers/gpu/drm/i915/display/intel_dp.c 	return (I915_READ(_pp_stat_reg(intel_dp)) & PP_ON) != 0;
PP_ON            2439 drivers/gpu/drm/i915/display/intel_dp.c #define IDLE_ON_MASK		(PP_ON | PP_SEQUENCE_MASK | 0                     | PP_SEQUENCE_STATE_MASK)
PP_ON            2440 drivers/gpu/drm/i915/display/intel_dp.c #define IDLE_ON_VALUE   	(PP_ON | PP_SEQUENCE_NONE | 0                     | PP_SEQUENCE_STATE_ON_IDLE)
PP_ON            2442 drivers/gpu/drm/i915/display/intel_dp.c #define IDLE_OFF_MASK		(PP_ON | PP_SEQUENCE_MASK | 0                     | 0)
PP_ON            2445 drivers/gpu/drm/i915/display/intel_dp.c #define IDLE_CYCLE_MASK		(PP_ON | PP_SEQUENCE_MASK | PP_CYCLE_DELAY_ACTIVE | PP_SEQUENCE_STATE_MASK)
PP_ON             321 drivers/gpu/drm/i915/display/intel_lvds.c 	if (intel_de_wait_for_set(dev_priv, PP_STATUS(0), PP_ON, 5000))
PP_ON             335 drivers/gpu/drm/i915/display/intel_lvds.c 	if (intel_de_wait_for_clear(dev_priv, PP_STATUS(0), PP_ON, 1000))
PP_ON             374 drivers/gpu/drm/i915/gvt/handlers.c 		vgpu_vreg_t(vgpu, PCH_PP_STATUS) |= PP_ON;
PP_ON             381 drivers/gpu/drm/i915/gvt/handlers.c 			~(PP_ON | PP_SEQUENCE_POWER_DOWN