PP_HOST_TO_SMC_UL 33 drivers/gpu/drm/amd/powerplay/inc/pp_endian.h #define CONVERT_FROM_HOST_TO_SMC_UL(X) ((X) = PP_HOST_TO_SMC_UL(X)) PP_HOST_TO_SMC_UL 455 drivers/gpu/drm/amd/powerplay/smumgr/ci_smumgr.c level->MinVddc = PP_HOST_TO_SMC_UL(level->MinVddc * VOLTAGE_SCALE); PP_HOST_TO_SMC_UL 744 drivers/gpu/drm/amd/powerplay/smumgr/ci_smumgr.c dpm_table->BAPM_TEMP_GRADIENT = PP_HOST_TO_SMC_UL(defaults->bapm_temp_gradient); PP_HOST_TO_SMC_UL 1009 drivers/gpu/drm/amd/powerplay/smumgr/ci_smumgr.c table->LinkLevel[i].DownT = PP_HOST_TO_SMC_UL(5); PP_HOST_TO_SMC_UL 1010 drivers/gpu/drm/amd/powerplay/smumgr/ci_smumgr.c table->LinkLevel[i].UpT = PP_HOST_TO_SMC_UL(30); PP_HOST_TO_SMC_UL 1276 drivers/gpu/drm/amd/powerplay/smumgr/ci_smumgr.c memory_level->MinVddc = PP_HOST_TO_SMC_UL(memory_level->MinVddc * VOLTAGE_SCALE); PP_HOST_TO_SMC_UL 1278 drivers/gpu/drm/amd/powerplay/smumgr/ci_smumgr.c memory_level->MinVddci = PP_HOST_TO_SMC_UL(memory_level->MinVddci * VOLTAGE_SCALE); PP_HOST_TO_SMC_UL 1279 drivers/gpu/drm/amd/powerplay/smumgr/ci_smumgr.c memory_level->MinMvdd = PP_HOST_TO_SMC_UL(memory_level->MinMvdd * VOLTAGE_SCALE); PP_HOST_TO_SMC_UL 1393 drivers/gpu/drm/amd/powerplay/smumgr/ci_smumgr.c table->ACPILevel.MinVddc = PP_HOST_TO_SMC_UL(data->acpi_vddc * VOLTAGE_SCALE); PP_HOST_TO_SMC_UL 1395 drivers/gpu/drm/amd/powerplay/smumgr/ci_smumgr.c table->ACPILevel.MinVddc = PP_HOST_TO_SMC_UL(data->min_vddc_in_pptable * VOLTAGE_SCALE); PP_HOST_TO_SMC_UL 1451 drivers/gpu/drm/amd/powerplay/smumgr/ci_smumgr.c table->MemoryACPILevel.MinVddci = PP_HOST_TO_SMC_UL(data->acpi_vddci * VOLTAGE_SCALE); PP_HOST_TO_SMC_UL 1453 drivers/gpu/drm/amd/powerplay/smumgr/ci_smumgr.c table->MemoryACPILevel.MinVddci = PP_HOST_TO_SMC_UL(data->min_vddci_in_pptable * VOLTAGE_SCALE); PP_HOST_TO_SMC_UL 1458 drivers/gpu/drm/amd/powerplay/smumgr/ci_smumgr.c PP_HOST_TO_SMC_UL(voltage_level.Voltage * VOLTAGE_SCALE); PP_HOST_TO_SMC_UL 1481 drivers/gpu/drm/amd/powerplay/smumgr/ci_smumgr.c PP_HOST_TO_SMC_UL(dll_cntl); PP_HOST_TO_SMC_UL 1483 drivers/gpu/drm/amd/powerplay/smumgr/ci_smumgr.c PP_HOST_TO_SMC_UL(mclk_pwrmgt_cntl); PP_HOST_TO_SMC_UL 1485 drivers/gpu/drm/amd/powerplay/smumgr/ci_smumgr.c PP_HOST_TO_SMC_UL(data->clock_registers.vMPLL_AD_FUNC_CNTL); PP_HOST_TO_SMC_UL 1487 drivers/gpu/drm/amd/powerplay/smumgr/ci_smumgr.c PP_HOST_TO_SMC_UL(data->clock_registers.vMPLL_DQ_FUNC_CNTL); PP_HOST_TO_SMC_UL 1489 drivers/gpu/drm/amd/powerplay/smumgr/ci_smumgr.c PP_HOST_TO_SMC_UL(data->clock_registers.vMPLL_FUNC_CNTL); PP_HOST_TO_SMC_UL 1491 drivers/gpu/drm/amd/powerplay/smumgr/ci_smumgr.c PP_HOST_TO_SMC_UL(data->clock_registers.vMPLL_FUNC_CNTL_1); PP_HOST_TO_SMC_UL 1493 drivers/gpu/drm/amd/powerplay/smumgr/ci_smumgr.c PP_HOST_TO_SMC_UL(data->clock_registers.vMPLL_FUNC_CNTL_2); PP_HOST_TO_SMC_UL 1495 drivers/gpu/drm/amd/powerplay/smumgr/ci_smumgr.c PP_HOST_TO_SMC_UL(data->clock_registers.vMPLL_SS1); PP_HOST_TO_SMC_UL 1497 drivers/gpu/drm/amd/powerplay/smumgr/ci_smumgr.c PP_HOST_TO_SMC_UL(data->clock_registers.vMPLL_SS2); PP_HOST_TO_SMC_UL 1641 drivers/gpu/drm/amd/powerplay/smumgr/ci_smumgr.c arb_regs->McArbDramTiming = PP_HOST_TO_SMC_UL(dramTiming); PP_HOST_TO_SMC_UL 1642 drivers/gpu/drm/amd/powerplay/smumgr/ci_smumgr.c arb_regs->McArbDramTiming2 = PP_HOST_TO_SMC_UL(dramTiming2); PP_HOST_TO_SMC_UL 1754 drivers/gpu/drm/amd/powerplay/smumgr/ci_smumgr.c data->value[i] = PP_HOST_TO_SMC_UL(entry->mc_data[j]); PP_HOST_TO_SMC_UL 2792 drivers/gpu/drm/amd/powerplay/smumgr/ci_smumgr.c tmp = PP_HOST_TO_SMC_UL(cgs_read_ind_register(hwmgr->device, CGS_IND_REG__SMC, offset)); PP_HOST_TO_SMC_UL 2794 drivers/gpu/drm/amd/powerplay/smumgr/ci_smumgr.c cgs_write_ind_register(hwmgr->device, CGS_IND_REG__SMC, offset, PP_HOST_TO_SMC_UL(tmp)); PP_HOST_TO_SMC_UL 2806 drivers/gpu/drm/amd/powerplay/smumgr/ci_smumgr.c tmp = PP_HOST_TO_SMC_UL(cgs_read_ind_register(hwmgr->device, CGS_IND_REG__SMC, offset)); PP_HOST_TO_SMC_UL 2809 drivers/gpu/drm/amd/powerplay/smumgr/ci_smumgr.c cgs_write_ind_register(hwmgr->device, CGS_IND_REG__SMC, offset, PP_HOST_TO_SMC_UL(tmp)); PP_HOST_TO_SMC_UL 2827 drivers/gpu/drm/amd/powerplay/smumgr/ci_smumgr.c tmp = PP_HOST_TO_SMC_UL(cgs_read_ind_register(hwmgr->device, CGS_IND_REG__SMC, offset)); PP_HOST_TO_SMC_UL 2829 drivers/gpu/drm/amd/powerplay/smumgr/ci_smumgr.c cgs_write_ind_register(hwmgr->device, CGS_IND_REG__SMC, offset, PP_HOST_TO_SMC_UL(tmp)); PP_HOST_TO_SMC_UL 2841 drivers/gpu/drm/amd/powerplay/smumgr/ci_smumgr.c tmp = PP_HOST_TO_SMC_UL(cgs_read_ind_register(hwmgr->device, CGS_IND_REG__SMC, offset)); PP_HOST_TO_SMC_UL 2844 drivers/gpu/drm/amd/powerplay/smumgr/ci_smumgr.c cgs_write_ind_register(hwmgr->device, CGS_IND_REG__SMC, offset, PP_HOST_TO_SMC_UL(tmp)); PP_HOST_TO_SMC_UL 845 drivers/gpu/drm/amd/powerplay/smumgr/fiji_smumgr.c table->LinkLevel[i].DownThreshold = PP_HOST_TO_SMC_UL(5); PP_HOST_TO_SMC_UL 846 drivers/gpu/drm/amd/powerplay/smumgr/fiji_smumgr.c table->LinkLevel[i].UpThreshold = PP_HOST_TO_SMC_UL(30); PP_HOST_TO_SMC_UL 1405 drivers/gpu/drm/amd/powerplay/smumgr/fiji_smumgr.c PP_HOST_TO_SMC_UL(us_mvdd * VOLTAGE_SCALE); PP_HOST_TO_SMC_UL 1520 drivers/gpu/drm/amd/powerplay/smumgr/fiji_smumgr.c arb_regs->McArbDramTiming = PP_HOST_TO_SMC_UL(dram_timing); PP_HOST_TO_SMC_UL 1521 drivers/gpu/drm/amd/powerplay/smumgr/fiji_smumgr.c arb_regs->McArbDramTiming2 = PP_HOST_TO_SMC_UL(dram_timing2); PP_HOST_TO_SMC_UL 2096 drivers/gpu/drm/amd/powerplay/smumgr/fiji_smumgr.c table->Smio[i] = PP_HOST_TO_SMC_UL(table->Smio[i]); PP_HOST_TO_SMC_UL 2584 drivers/gpu/drm/amd/powerplay/smumgr/fiji_smumgr.c tmp = PP_HOST_TO_SMC_UL(cgs_read_ind_register(hwmgr->device, CGS_IND_REG__SMC, offset)); PP_HOST_TO_SMC_UL 2586 drivers/gpu/drm/amd/powerplay/smumgr/fiji_smumgr.c cgs_write_ind_register(hwmgr->device, CGS_IND_REG__SMC, offset, PP_HOST_TO_SMC_UL(tmp)); PP_HOST_TO_SMC_UL 2598 drivers/gpu/drm/amd/powerplay/smumgr/fiji_smumgr.c tmp = PP_HOST_TO_SMC_UL(cgs_read_ind_register(hwmgr->device, CGS_IND_REG__SMC, offset)); PP_HOST_TO_SMC_UL 2601 drivers/gpu/drm/amd/powerplay/smumgr/fiji_smumgr.c cgs_write_ind_register(hwmgr->device, CGS_IND_REG__SMC, offset, PP_HOST_TO_SMC_UL(tmp)); PP_HOST_TO_SMC_UL 2619 drivers/gpu/drm/amd/powerplay/smumgr/fiji_smumgr.c tmp = PP_HOST_TO_SMC_UL(cgs_read_ind_register(hwmgr->device, CGS_IND_REG__SMC, offset)); PP_HOST_TO_SMC_UL 2621 drivers/gpu/drm/amd/powerplay/smumgr/fiji_smumgr.c cgs_write_ind_register(hwmgr->device, CGS_IND_REG__SMC, offset, PP_HOST_TO_SMC_UL(tmp)); PP_HOST_TO_SMC_UL 2633 drivers/gpu/drm/amd/powerplay/smumgr/fiji_smumgr.c tmp = PP_HOST_TO_SMC_UL(cgs_read_ind_register(hwmgr->device, CGS_IND_REG__SMC, offset)); PP_HOST_TO_SMC_UL 2636 drivers/gpu/drm/amd/powerplay/smumgr/fiji_smumgr.c cgs_write_ind_register(hwmgr->device, CGS_IND_REG__SMC, offset, PP_HOST_TO_SMC_UL(tmp)); PP_HOST_TO_SMC_UL 782 drivers/gpu/drm/amd/powerplay/smumgr/iceland_smumgr.c PP_HOST_TO_SMC_UL(5); PP_HOST_TO_SMC_UL 784 drivers/gpu/drm/amd/powerplay/smumgr/iceland_smumgr.c PP_HOST_TO_SMC_UL(30); PP_HOST_TO_SMC_UL 944 drivers/gpu/drm/amd/powerplay/smumgr/iceland_smumgr.c graphic_level->MinVddc = PP_HOST_TO_SMC_UL(graphic_level->MinVddc * VOLTAGE_SCALE); PP_HOST_TO_SMC_UL 1324 drivers/gpu/drm/amd/powerplay/smumgr/iceland_smumgr.c memory_level->MinVddc = PP_HOST_TO_SMC_UL(memory_level->MinVddc * VOLTAGE_SCALE); PP_HOST_TO_SMC_UL 1326 drivers/gpu/drm/amd/powerplay/smumgr/iceland_smumgr.c memory_level->MinVddci = PP_HOST_TO_SMC_UL(memory_level->MinVddci * VOLTAGE_SCALE); PP_HOST_TO_SMC_UL 1327 drivers/gpu/drm/amd/powerplay/smumgr/iceland_smumgr.c memory_level->MinMvdd = PP_HOST_TO_SMC_UL(memory_level->MinMvdd * VOLTAGE_SCALE); PP_HOST_TO_SMC_UL 1441 drivers/gpu/drm/amd/powerplay/smumgr/iceland_smumgr.c table->ACPILevel.MinVddc = PP_HOST_TO_SMC_UL(data->acpi_vddc * VOLTAGE_SCALE); PP_HOST_TO_SMC_UL 1443 drivers/gpu/drm/amd/powerplay/smumgr/iceland_smumgr.c table->ACPILevel.MinVddc = PP_HOST_TO_SMC_UL(data->min_vddc_in_pptable * VOLTAGE_SCALE); PP_HOST_TO_SMC_UL 1499 drivers/gpu/drm/amd/powerplay/smumgr/iceland_smumgr.c table->MemoryACPILevel.MinVddci = PP_HOST_TO_SMC_UL(data->acpi_vddci * VOLTAGE_SCALE); PP_HOST_TO_SMC_UL 1501 drivers/gpu/drm/amd/powerplay/smumgr/iceland_smumgr.c table->MemoryACPILevel.MinVddci = PP_HOST_TO_SMC_UL(data->min_vddci_in_pptable * VOLTAGE_SCALE); PP_HOST_TO_SMC_UL 1506 drivers/gpu/drm/amd/powerplay/smumgr/iceland_smumgr.c PP_HOST_TO_SMC_UL(voltage_level.Voltage * VOLTAGE_SCALE); PP_HOST_TO_SMC_UL 1529 drivers/gpu/drm/amd/powerplay/smumgr/iceland_smumgr.c PP_HOST_TO_SMC_UL(dll_cntl); PP_HOST_TO_SMC_UL 1531 drivers/gpu/drm/amd/powerplay/smumgr/iceland_smumgr.c PP_HOST_TO_SMC_UL(mclk_pwrmgt_cntl); PP_HOST_TO_SMC_UL 1533 drivers/gpu/drm/amd/powerplay/smumgr/iceland_smumgr.c PP_HOST_TO_SMC_UL(data->clock_registers.vMPLL_AD_FUNC_CNTL); PP_HOST_TO_SMC_UL 1535 drivers/gpu/drm/amd/powerplay/smumgr/iceland_smumgr.c PP_HOST_TO_SMC_UL(data->clock_registers.vMPLL_DQ_FUNC_CNTL); PP_HOST_TO_SMC_UL 1537 drivers/gpu/drm/amd/powerplay/smumgr/iceland_smumgr.c PP_HOST_TO_SMC_UL(data->clock_registers.vMPLL_FUNC_CNTL); PP_HOST_TO_SMC_UL 1539 drivers/gpu/drm/amd/powerplay/smumgr/iceland_smumgr.c PP_HOST_TO_SMC_UL(data->clock_registers.vMPLL_FUNC_CNTL_1); PP_HOST_TO_SMC_UL 1541 drivers/gpu/drm/amd/powerplay/smumgr/iceland_smumgr.c PP_HOST_TO_SMC_UL(data->clock_registers.vMPLL_FUNC_CNTL_2); PP_HOST_TO_SMC_UL 1543 drivers/gpu/drm/amd/powerplay/smumgr/iceland_smumgr.c PP_HOST_TO_SMC_UL(data->clock_registers.vMPLL_SS1); PP_HOST_TO_SMC_UL 1545 drivers/gpu/drm/amd/powerplay/smumgr/iceland_smumgr.c PP_HOST_TO_SMC_UL(data->clock_registers.vMPLL_SS2); PP_HOST_TO_SMC_UL 1604 drivers/gpu/drm/amd/powerplay/smumgr/iceland_smumgr.c arb_regs->McArbDramTiming = PP_HOST_TO_SMC_UL(dramTiming); PP_HOST_TO_SMC_UL 1605 drivers/gpu/drm/amd/powerplay/smumgr/iceland_smumgr.c arb_regs->McArbDramTiming2 = PP_HOST_TO_SMC_UL(dramTiming2); PP_HOST_TO_SMC_UL 1722 drivers/gpu/drm/amd/powerplay/smumgr/iceland_smumgr.c data->value[i] = PP_HOST_TO_SMC_UL(entry->mc_data[j]); PP_HOST_TO_SMC_UL 1889 drivers/gpu/drm/amd/powerplay/smumgr/iceland_smumgr.c dpm_table->BAPM_TEMP_GRADIENT = PP_HOST_TO_SMC_UL(defaults->bapm_temp_gradient); PP_HOST_TO_SMC_UL 667 drivers/gpu/drm/amd/powerplay/smumgr/polaris10_smumgr.c table->MvddLevelCount = (uint32_t) PP_HOST_TO_SMC_UL(count); PP_HOST_TO_SMC_UL 783 drivers/gpu/drm/amd/powerplay/smumgr/polaris10_smumgr.c table->LinkLevel[i].DownThreshold = PP_HOST_TO_SMC_UL(5); PP_HOST_TO_SMC_UL 784 drivers/gpu/drm/amd/powerplay/smumgr/polaris10_smumgr.c table->LinkLevel[i].UpThreshold = PP_HOST_TO_SMC_UL(30); PP_HOST_TO_SMC_UL 1266 drivers/gpu/drm/amd/powerplay/smumgr/polaris10_smumgr.c table->MemoryACPILevel.MinMvdd = PP_HOST_TO_SMC_UL(vol_level.Voltage); PP_HOST_TO_SMC_UL 1355 drivers/gpu/drm/amd/powerplay/smumgr/polaris10_smumgr.c arb_regs->McArbDramTiming = PP_HOST_TO_SMC_UL(dram_timing); PP_HOST_TO_SMC_UL 1356 drivers/gpu/drm/amd/powerplay/smumgr/polaris10_smumgr.c arb_regs->McArbDramTiming2 = PP_HOST_TO_SMC_UL(dram_timing2); PP_HOST_TO_SMC_UL 1718 drivers/gpu/drm/amd/powerplay/smumgr/polaris10_smumgr.c table->BTCGB_VDROOP_TABLE[0].a0 = PP_HOST_TO_SMC_UL(avfs_params.ulGB_VDROOP_TABLE_CKSON_a0); PP_HOST_TO_SMC_UL 1719 drivers/gpu/drm/amd/powerplay/smumgr/polaris10_smumgr.c table->BTCGB_VDROOP_TABLE[0].a1 = PP_HOST_TO_SMC_UL(avfs_params.ulGB_VDROOP_TABLE_CKSON_a1); PP_HOST_TO_SMC_UL 1720 drivers/gpu/drm/amd/powerplay/smumgr/polaris10_smumgr.c table->BTCGB_VDROOP_TABLE[0].a2 = PP_HOST_TO_SMC_UL(avfs_params.ulGB_VDROOP_TABLE_CKSON_a2); PP_HOST_TO_SMC_UL 1721 drivers/gpu/drm/amd/powerplay/smumgr/polaris10_smumgr.c table->BTCGB_VDROOP_TABLE[1].a0 = PP_HOST_TO_SMC_UL(avfs_params.ulGB_VDROOP_TABLE_CKSOFF_a0); PP_HOST_TO_SMC_UL 1722 drivers/gpu/drm/amd/powerplay/smumgr/polaris10_smumgr.c table->BTCGB_VDROOP_TABLE[1].a1 = PP_HOST_TO_SMC_UL(avfs_params.ulGB_VDROOP_TABLE_CKSOFF_a1); PP_HOST_TO_SMC_UL 1723 drivers/gpu/drm/amd/powerplay/smumgr/polaris10_smumgr.c table->BTCGB_VDROOP_TABLE[1].a2 = PP_HOST_TO_SMC_UL(avfs_params.ulGB_VDROOP_TABLE_CKSOFF_a2); PP_HOST_TO_SMC_UL 1724 drivers/gpu/drm/amd/powerplay/smumgr/polaris10_smumgr.c table->AVFSGB_VDROOP_TABLE[0].m1 = PP_HOST_TO_SMC_UL(avfs_params.ulAVFSGB_FUSE_TABLE_CKSON_m1); PP_HOST_TO_SMC_UL 1726 drivers/gpu/drm/amd/powerplay/smumgr/polaris10_smumgr.c table->AVFSGB_VDROOP_TABLE[0].b = PP_HOST_TO_SMC_UL(avfs_params.ulAVFSGB_FUSE_TABLE_CKSON_b); PP_HOST_TO_SMC_UL 1729 drivers/gpu/drm/amd/powerplay/smumgr/polaris10_smumgr.c table->AVFSGB_VDROOP_TABLE[1].m1 = PP_HOST_TO_SMC_UL(avfs_params.ulAVFSGB_FUSE_TABLE_CKSOFF_m1); PP_HOST_TO_SMC_UL 1731 drivers/gpu/drm/amd/powerplay/smumgr/polaris10_smumgr.c table->AVFSGB_VDROOP_TABLE[1].b = PP_HOST_TO_SMC_UL(avfs_params.ulAVFSGB_FUSE_TABLE_CKSOFF_b); PP_HOST_TO_SMC_UL 1735 drivers/gpu/drm/amd/powerplay/smumgr/polaris10_smumgr.c AVFS_meanNsigma.Aconstant[0] = PP_HOST_TO_SMC_UL(avfs_params.ulAVFS_meanNsigma_Acontant0); PP_HOST_TO_SMC_UL 1736 drivers/gpu/drm/amd/powerplay/smumgr/polaris10_smumgr.c AVFS_meanNsigma.Aconstant[1] = PP_HOST_TO_SMC_UL(avfs_params.ulAVFS_meanNsigma_Acontant1); PP_HOST_TO_SMC_UL 1737 drivers/gpu/drm/amd/powerplay/smumgr/polaris10_smumgr.c AVFS_meanNsigma.Aconstant[2] = PP_HOST_TO_SMC_UL(avfs_params.ulAVFS_meanNsigma_Acontant2); PP_HOST_TO_SMC_UL 1999 drivers/gpu/drm/amd/powerplay/smumgr/polaris10_smumgr.c table->Smio[i] = PP_HOST_TO_SMC_UL(table->Smio[i]); PP_HOST_TO_SMC_UL 2497 drivers/gpu/drm/amd/powerplay/smumgr/polaris10_smumgr.c tmp = PP_HOST_TO_SMC_UL(cgs_read_ind_register(hwmgr->device, CGS_IND_REG__SMC, offset)); PP_HOST_TO_SMC_UL 2499 drivers/gpu/drm/amd/powerplay/smumgr/polaris10_smumgr.c cgs_write_ind_register(hwmgr->device, CGS_IND_REG__SMC, offset, PP_HOST_TO_SMC_UL(tmp)); PP_HOST_TO_SMC_UL 2511 drivers/gpu/drm/amd/powerplay/smumgr/polaris10_smumgr.c tmp = PP_HOST_TO_SMC_UL(cgs_read_ind_register(hwmgr->device, CGS_IND_REG__SMC, offset)); PP_HOST_TO_SMC_UL 2514 drivers/gpu/drm/amd/powerplay/smumgr/polaris10_smumgr.c cgs_write_ind_register(hwmgr->device, CGS_IND_REG__SMC, offset, PP_HOST_TO_SMC_UL(tmp)); PP_HOST_TO_SMC_UL 2532 drivers/gpu/drm/amd/powerplay/smumgr/polaris10_smumgr.c tmp = PP_HOST_TO_SMC_UL(cgs_read_ind_register(hwmgr->device, CGS_IND_REG__SMC, offset)); PP_HOST_TO_SMC_UL 2534 drivers/gpu/drm/amd/powerplay/smumgr/polaris10_smumgr.c cgs_write_ind_register(hwmgr->device, CGS_IND_REG__SMC, offset, PP_HOST_TO_SMC_UL(tmp)); PP_HOST_TO_SMC_UL 2546 drivers/gpu/drm/amd/powerplay/smumgr/polaris10_smumgr.c tmp = PP_HOST_TO_SMC_UL(cgs_read_ind_register(hwmgr->device, CGS_IND_REG__SMC, offset)); PP_HOST_TO_SMC_UL 2549 drivers/gpu/drm/amd/powerplay/smumgr/polaris10_smumgr.c cgs_write_ind_register(hwmgr->device, CGS_IND_REG__SMC, offset, PP_HOST_TO_SMC_UL(tmp)); PP_HOST_TO_SMC_UL 525 drivers/gpu/drm/amd/powerplay/smumgr/tonga_smumgr.c PP_HOST_TO_SMC_UL(5); PP_HOST_TO_SMC_UL 527 drivers/gpu/drm/amd/powerplay/smumgr/tonga_smumgr.c PP_HOST_TO_SMC_UL(30); PP_HOST_TO_SMC_UL 1248 drivers/gpu/drm/amd/powerplay/smumgr/tonga_smumgr.c PP_HOST_TO_SMC_UL(voltage_level.Voltage * VOLTAGE_SCALE); PP_HOST_TO_SMC_UL 1271 drivers/gpu/drm/amd/powerplay/smumgr/tonga_smumgr.c PP_HOST_TO_SMC_UL(dll_cntl); PP_HOST_TO_SMC_UL 1273 drivers/gpu/drm/amd/powerplay/smumgr/tonga_smumgr.c PP_HOST_TO_SMC_UL(mclk_pwrmgt_cntl); PP_HOST_TO_SMC_UL 1275 drivers/gpu/drm/amd/powerplay/smumgr/tonga_smumgr.c PP_HOST_TO_SMC_UL(data->clock_registers.vMPLL_AD_FUNC_CNTL); PP_HOST_TO_SMC_UL 1277 drivers/gpu/drm/amd/powerplay/smumgr/tonga_smumgr.c PP_HOST_TO_SMC_UL(data->clock_registers.vMPLL_DQ_FUNC_CNTL); PP_HOST_TO_SMC_UL 1279 drivers/gpu/drm/amd/powerplay/smumgr/tonga_smumgr.c PP_HOST_TO_SMC_UL(data->clock_registers.vMPLL_FUNC_CNTL); PP_HOST_TO_SMC_UL 1281 drivers/gpu/drm/amd/powerplay/smumgr/tonga_smumgr.c PP_HOST_TO_SMC_UL(data->clock_registers.vMPLL_FUNC_CNTL_1); PP_HOST_TO_SMC_UL 1283 drivers/gpu/drm/amd/powerplay/smumgr/tonga_smumgr.c PP_HOST_TO_SMC_UL(data->clock_registers.vMPLL_FUNC_CNTL_2); PP_HOST_TO_SMC_UL 1285 drivers/gpu/drm/amd/powerplay/smumgr/tonga_smumgr.c PP_HOST_TO_SMC_UL(data->clock_registers.vMPLL_SS1); PP_HOST_TO_SMC_UL 1287 drivers/gpu/drm/amd/powerplay/smumgr/tonga_smumgr.c PP_HOST_TO_SMC_UL(data->clock_registers.vMPLL_SS2); PP_HOST_TO_SMC_UL 1479 drivers/gpu/drm/amd/powerplay/smumgr/tonga_smumgr.c arb_regs->McArbDramTiming = PP_HOST_TO_SMC_UL(dramTiming); PP_HOST_TO_SMC_UL 1480 drivers/gpu/drm/amd/powerplay/smumgr/tonga_smumgr.c arb_regs->McArbDramTiming2 = PP_HOST_TO_SMC_UL(dramTiming2); PP_HOST_TO_SMC_UL 1853 drivers/gpu/drm/amd/powerplay/smumgr/tonga_smumgr.c PP_HOST_TO_SMC_UL(defaults->bapm_temp_gradient); PP_HOST_TO_SMC_UL 2100 drivers/gpu/drm/amd/powerplay/smumgr/tonga_smumgr.c data->value[i] = PP_HOST_TO_SMC_UL(entry->mc_data[j]); PP_HOST_TO_SMC_UL 2423 drivers/gpu/drm/amd/powerplay/smumgr/tonga_smumgr.c table->Smio[i] = PP_HOST_TO_SMC_UL(table->Smio[i]); PP_HOST_TO_SMC_UL 3180 drivers/gpu/drm/amd/powerplay/smumgr/tonga_smumgr.c tmp = PP_HOST_TO_SMC_UL(cgs_read_ind_register(hwmgr->device, CGS_IND_REG__SMC, offset)); PP_HOST_TO_SMC_UL 3182 drivers/gpu/drm/amd/powerplay/smumgr/tonga_smumgr.c cgs_write_ind_register(hwmgr->device, CGS_IND_REG__SMC, offset, PP_HOST_TO_SMC_UL(tmp)); PP_HOST_TO_SMC_UL 3194 drivers/gpu/drm/amd/powerplay/smumgr/tonga_smumgr.c tmp = PP_HOST_TO_SMC_UL(cgs_read_ind_register(hwmgr->device, CGS_IND_REG__SMC, offset)); PP_HOST_TO_SMC_UL 3197 drivers/gpu/drm/amd/powerplay/smumgr/tonga_smumgr.c cgs_write_ind_register(hwmgr->device, CGS_IND_REG__SMC, offset, PP_HOST_TO_SMC_UL(tmp)); PP_HOST_TO_SMC_UL 3215 drivers/gpu/drm/amd/powerplay/smumgr/tonga_smumgr.c tmp = PP_HOST_TO_SMC_UL(cgs_read_ind_register(hwmgr->device, CGS_IND_REG__SMC, offset)); PP_HOST_TO_SMC_UL 3217 drivers/gpu/drm/amd/powerplay/smumgr/tonga_smumgr.c cgs_write_ind_register(hwmgr->device, CGS_IND_REG__SMC, offset, PP_HOST_TO_SMC_UL(tmp)); PP_HOST_TO_SMC_UL 3229 drivers/gpu/drm/amd/powerplay/smumgr/tonga_smumgr.c tmp = PP_HOST_TO_SMC_UL(cgs_read_ind_register(hwmgr->device, CGS_IND_REG__SMC, offset)); PP_HOST_TO_SMC_UL 3232 drivers/gpu/drm/amd/powerplay/smumgr/tonga_smumgr.c cgs_write_ind_register(hwmgr->device, CGS_IND_REG__SMC, offset, PP_HOST_TO_SMC_UL(tmp)); PP_HOST_TO_SMC_UL 468 drivers/gpu/drm/amd/powerplay/smumgr/vegam_smumgr.c table->MvddLevelCount = (uint32_t) PP_HOST_TO_SMC_UL(count); PP_HOST_TO_SMC_UL 585 drivers/gpu/drm/amd/powerplay/smumgr/vegam_smumgr.c table->LinkLevel[i].DownThreshold = PP_HOST_TO_SMC_UL(5); PP_HOST_TO_SMC_UL 586 drivers/gpu/drm/amd/powerplay/smumgr/vegam_smumgr.c table->LinkLevel[i].UpThreshold = PP_HOST_TO_SMC_UL(30); PP_HOST_TO_SMC_UL 1183 drivers/gpu/drm/amd/powerplay/smumgr/vegam_smumgr.c table->MemoryACPILevel.MinMvdd = PP_HOST_TO_SMC_UL(vol_level.Voltage); PP_HOST_TO_SMC_UL 1277 drivers/gpu/drm/amd/powerplay/smumgr/vegam_smumgr.c arb_regs->McArbDramTiming = PP_HOST_TO_SMC_UL(dram_timing); PP_HOST_TO_SMC_UL 1278 drivers/gpu/drm/amd/powerplay/smumgr/vegam_smumgr.c arb_regs->McArbDramTiming2 = PP_HOST_TO_SMC_UL(dram_timing2); PP_HOST_TO_SMC_UL 1279 drivers/gpu/drm/amd/powerplay/smumgr/vegam_smumgr.c arb_regs->McArbBurstTime = PP_HOST_TO_SMC_UL(burst_time); PP_HOST_TO_SMC_UL 1280 drivers/gpu/drm/amd/powerplay/smumgr/vegam_smumgr.c arb_regs->McArbRfshRate = PP_HOST_TO_SMC_UL(rfsh_rate); PP_HOST_TO_SMC_UL 1281 drivers/gpu/drm/amd/powerplay/smumgr/vegam_smumgr.c arb_regs->McArbMisc3 = PP_HOST_TO_SMC_UL(misc3); PP_HOST_TO_SMC_UL 1592 drivers/gpu/drm/amd/powerplay/smumgr/vegam_smumgr.c PP_HOST_TO_SMC_UL(avfs_params.ulGB_VDROOP_TABLE_CKSON_a0); PP_HOST_TO_SMC_UL 1594 drivers/gpu/drm/amd/powerplay/smumgr/vegam_smumgr.c PP_HOST_TO_SMC_UL(avfs_params.ulGB_VDROOP_TABLE_CKSON_a1); PP_HOST_TO_SMC_UL 1596 drivers/gpu/drm/amd/powerplay/smumgr/vegam_smumgr.c PP_HOST_TO_SMC_UL(avfs_params.ulGB_VDROOP_TABLE_CKSON_a2); PP_HOST_TO_SMC_UL 1598 drivers/gpu/drm/amd/powerplay/smumgr/vegam_smumgr.c PP_HOST_TO_SMC_UL(avfs_params.ulGB_VDROOP_TABLE_CKSOFF_a0); PP_HOST_TO_SMC_UL 1600 drivers/gpu/drm/amd/powerplay/smumgr/vegam_smumgr.c PP_HOST_TO_SMC_UL(avfs_params.ulGB_VDROOP_TABLE_CKSOFF_a1); PP_HOST_TO_SMC_UL 1602 drivers/gpu/drm/amd/powerplay/smumgr/vegam_smumgr.c PP_HOST_TO_SMC_UL(avfs_params.ulGB_VDROOP_TABLE_CKSOFF_a2); PP_HOST_TO_SMC_UL 1604 drivers/gpu/drm/amd/powerplay/smumgr/vegam_smumgr.c PP_HOST_TO_SMC_UL(avfs_params.ulAVFSGB_FUSE_TABLE_CKSON_m1); PP_HOST_TO_SMC_UL 1608 drivers/gpu/drm/amd/powerplay/smumgr/vegam_smumgr.c PP_HOST_TO_SMC_UL(avfs_params.ulAVFSGB_FUSE_TABLE_CKSON_b); PP_HOST_TO_SMC_UL 1612 drivers/gpu/drm/amd/powerplay/smumgr/vegam_smumgr.c PP_HOST_TO_SMC_UL(avfs_params.ulAVFSGB_FUSE_TABLE_CKSOFF_m1); PP_HOST_TO_SMC_UL 1616 drivers/gpu/drm/amd/powerplay/smumgr/vegam_smumgr.c PP_HOST_TO_SMC_UL(avfs_params.ulAVFSGB_FUSE_TABLE_CKSOFF_b); PP_HOST_TO_SMC_UL 1621 drivers/gpu/drm/amd/powerplay/smumgr/vegam_smumgr.c PP_HOST_TO_SMC_UL(avfs_params.ulAVFS_meanNsigma_Acontant0); PP_HOST_TO_SMC_UL 1623 drivers/gpu/drm/amd/powerplay/smumgr/vegam_smumgr.c PP_HOST_TO_SMC_UL(avfs_params.ulAVFS_meanNsigma_Acontant1); PP_HOST_TO_SMC_UL 1625 drivers/gpu/drm/amd/powerplay/smumgr/vegam_smumgr.c PP_HOST_TO_SMC_UL(avfs_params.ulAVFS_meanNsigma_Acontant2); PP_HOST_TO_SMC_UL 2125 drivers/gpu/drm/amd/powerplay/smumgr/vegam_smumgr.c table->Smio[i] = PP_HOST_TO_SMC_UL(table->Smio[i]);