PP_CONTROL 278 drivers/gpu/drm/gma500/cdv_device.c regs->cdv.savePP_CONTROL = REG_READ(PP_CONTROL); PP_CONTROL 357 drivers/gpu/drm/gma500/cdv_device.c REG_WRITE(PP_CONTROL, regs->cdv.savePP_CONTROL); PP_CONTROL 391 drivers/gpu/drm/gma500/cdv_intel_dp.c pp = REG_READ(PP_CONTROL); PP_CONTROL 394 drivers/gpu/drm/gma500/cdv_intel_dp.c REG_WRITE(PP_CONTROL, pp); PP_CONTROL 395 drivers/gpu/drm/gma500/cdv_intel_dp.c REG_READ(PP_CONTROL); PP_CONTROL 405 drivers/gpu/drm/gma500/cdv_intel_dp.c pp = REG_READ(PP_CONTROL); PP_CONTROL 408 drivers/gpu/drm/gma500/cdv_intel_dp.c REG_WRITE(PP_CONTROL, pp); PP_CONTROL 409 drivers/gpu/drm/gma500/cdv_intel_dp.c REG_READ(PP_CONTROL); PP_CONTROL 424 drivers/gpu/drm/gma500/cdv_intel_dp.c pp = REG_READ(PP_CONTROL); PP_CONTROL 428 drivers/gpu/drm/gma500/cdv_intel_dp.c REG_WRITE(PP_CONTROL, pp); PP_CONTROL 429 drivers/gpu/drm/gma500/cdv_intel_dp.c REG_READ(PP_CONTROL); PP_CONTROL 449 drivers/gpu/drm/gma500/cdv_intel_dp.c pp = REG_READ(PP_CONTROL); PP_CONTROL 461 drivers/gpu/drm/gma500/cdv_intel_dp.c REG_WRITE(PP_CONTROL, pp); PP_CONTROL 462 drivers/gpu/drm/gma500/cdv_intel_dp.c REG_READ(PP_CONTROL); PP_CONTROL 486 drivers/gpu/drm/gma500/cdv_intel_dp.c pp = REG_READ(PP_CONTROL); PP_CONTROL 489 drivers/gpu/drm/gma500/cdv_intel_dp.c REG_WRITE(PP_CONTROL, pp); PP_CONTROL 502 drivers/gpu/drm/gma500/cdv_intel_dp.c pp = REG_READ(PP_CONTROL); PP_CONTROL 505 drivers/gpu/drm/gma500/cdv_intel_dp.c REG_WRITE(PP_CONTROL, pp); PP_CONTROL 2070 drivers/gpu/drm/gma500/cdv_intel_dp.c pp_on = REG_READ(PP_CONTROL); PP_CONTROL 2074 drivers/gpu/drm/gma500/cdv_intel_dp.c REG_WRITE(PP_CONTROL, pp_on); PP_CONTROL 196 drivers/gpu/drm/gma500/cdv_intel_lvds.c REG_WRITE(PP_CONTROL, REG_READ(PP_CONTROL) | PP_CONTROL 207 drivers/gpu/drm/gma500/cdv_intel_lvds.c REG_WRITE(PP_CONTROL, REG_READ(PP_CONTROL) & PP_CONTROL 233 drivers/gpu/drm/gma500/oaktrail_device.c regs->psb.savePP_CONTROL = PSB_RVDC32(PP_CONTROL); PP_CONTROL 262 drivers/gpu/drm/gma500/oaktrail_device.c PSB_WVDC32(0, PP_CONTROL); PP_CONTROL 370 drivers/gpu/drm/gma500/oaktrail_device.c PSB_WVDC32(regs->psb.savePP_CONTROL, PP_CONTROL); PP_CONTROL 44 drivers/gpu/drm/gma500/oaktrail_lvds.c REG_WRITE(PP_CONTROL, REG_READ(PP_CONTROL) | PP_CONTROL 55 drivers/gpu/drm/gma500/oaktrail_lvds.c REG_WRITE(PP_CONTROL, REG_READ(PP_CONTROL) & PP_CONTROL 219 drivers/gpu/drm/gma500/psb_intel_lvds.c REG_WRITE(PP_CONTROL, REG_READ(PP_CONTROL) | PP_CONTROL 230 drivers/gpu/drm/gma500/psb_intel_lvds.c REG_WRITE(PP_CONTROL, REG_READ(PP_CONTROL) & PP_CONTROL 264 drivers/gpu/drm/gma500/psb_intel_lvds.c lvds_priv->savePP_CONTROL = REG_READ(PP_CONTROL); PP_CONTROL 315 drivers/gpu/drm/gma500/psb_intel_lvds.c REG_WRITE(PP_CONTROL, lvds_priv->savePP_CONTROL); PP_CONTROL 319 drivers/gpu/drm/gma500/psb_intel_lvds.c REG_WRITE(PP_CONTROL, REG_READ(PP_CONTROL) | PP_CONTROL 325 drivers/gpu/drm/gma500/psb_intel_lvds.c REG_WRITE(PP_CONTROL, REG_READ(PP_CONTROL) & PP_CONTROL 28 drivers/gpu/drm/gma500/psb_lid.c REG_WRITE(PP_CONTROL, REG_READ(PP_CONTROL) | POWER_TARGET_ON); PP_CONTROL 44 drivers/gpu/drm/gma500/psb_lid.c REG_WRITE(PP_CONTROL, REG_READ(PP_CONTROL) & ~POWER_TARGET_ON); PP_CONTROL 1198 drivers/gpu/drm/i915/display/intel_display.c pp_reg = PP_CONTROL(0); PP_CONTROL 1220 drivers/gpu/drm/i915/display/intel_display.c pp_reg = PP_CONTROL(pipe); PP_CONTROL 1225 drivers/gpu/drm/i915/display/intel_display.c pp_reg = PP_CONTROL(0); PP_CONTROL 15296 drivers/gpu/drm/i915/display/intel_display.c u32 val = I915_READ(PP_CONTROL(pps_idx)); PP_CONTROL 15299 drivers/gpu/drm/i915/display/intel_display.c I915_WRITE(PP_CONTROL(pps_idx), val); PP_CONTROL 912 drivers/gpu/drm/i915/display/intel_dp.c return I915_READ(PP_CONTROL(pipe)) & EDP_FORCE_VDD; PP_CONTROL 1034 drivers/gpu/drm/i915/display/intel_dp.c regs->pp_ctrl = PP_CONTROL(pps_idx); PP_CONTROL 1085 drivers/gpu/drm/i915/display/intel_dp.c pp_ctrl_reg = PP_CONTROL(pipe); PP_CONTROL 159 drivers/gpu/drm/i915/display/intel_lvds.c pps->powerdown_on_reset = I915_READ(PP_CONTROL(0)) & PANEL_POWER_RESET; PP_CONTROL 206 drivers/gpu/drm/i915/display/intel_lvds.c val = I915_READ(PP_CONTROL(0)); PP_CONTROL 210 drivers/gpu/drm/i915/display/intel_lvds.c I915_WRITE(PP_CONTROL(0), val); PP_CONTROL 318 drivers/gpu/drm/i915/display/intel_lvds.c I915_WRITE(PP_CONTROL(0), I915_READ(PP_CONTROL(0)) | PANEL_POWER_ON); PP_CONTROL 334 drivers/gpu/drm/i915/display/intel_lvds.c I915_WRITE(PP_CONTROL(0), I915_READ(PP_CONTROL(0)) & ~PANEL_POWER_ON);