PP_ASSERT_WITH_CODE 375 drivers/gpu/drm/amd/powerplay/hwmgr/hardwaremanager.c PP_ASSERT_WITH_CODE((NULL != state), "Invalid Input!", return -EINVAL); PP_ASSERT_WITH_CODE 376 drivers/gpu/drm/amd/powerplay/hwmgr/hardwaremanager.c PP_ASSERT_WITH_CODE((NULL != pclock_info), "Invalid Input!", return -EINVAL); PP_ASSERT_WITH_CODE 380 drivers/gpu/drm/amd/powerplay/hwmgr/hardwaremanager.c PP_ASSERT_WITH_CODE((0 == result), "Failed to retrieve minimum clocks.", return result); PP_ASSERT_WITH_CODE 391 drivers/gpu/drm/amd/powerplay/hwmgr/hardwaremanager.c PP_ASSERT_WITH_CODE((0 == result), "Failed to retrieve maximum clocks.", return result); PP_ASSERT_WITH_CODE 87 drivers/gpu/drm/amd/powerplay/hwmgr/ppatomctrl.c PP_ASSERT_WITH_CODE((*(uint32_t *)reg_data == END_OF_REG_DATA_BLOCK), PP_ASSERT_WITH_CODE 112 drivers/gpu/drm/amd/powerplay/hwmgr/ppatomctrl.c PP_ASSERT_WITH_CODE((num_entries <= VBIOS_MC_REGISTER_ARRAY_SIZE), PP_ASSERT_WITH_CODE 516 drivers/gpu/drm/amd/powerplay/hwmgr/ppatomctrl.c PP_ASSERT_WITH_CODE((NULL != voltage_info), PP_ASSERT_WITH_CODE 536 drivers/gpu/drm/amd/powerplay/hwmgr/ppatomctrl.c PP_ASSERT_WITH_CODE((NULL != voltage_info), PP_ASSERT_WITH_CODE 545 drivers/gpu/drm/amd/powerplay/hwmgr/ppatomctrl.c PP_ASSERT_WITH_CODE( PP_ASSERT_WITH_CODE 613 drivers/gpu/drm/amd/powerplay/hwmgr/ppatomctrl.c PP_ASSERT_WITH_CODE((NULL != table_address), PP_ASSERT_WITH_CODE 631 drivers/gpu/drm/amd/powerplay/hwmgr/ppatomctrl.c PP_ASSERT_WITH_CODE((NULL != gpio_lookup_table), PP_ASSERT_WITH_CODE 1440 drivers/gpu/drm/amd/powerplay/hwmgr/ppatomctrl.c PP_ASSERT_WITH_CODE((NULL != voltage_info), PP_ASSERT_WITH_CODE 64 drivers/gpu/drm/amd/powerplay/hwmgr/ppatomfwctrl.c PP_ASSERT_WITH_CODE(table_address, PP_ASSERT_WITH_CODE 85 drivers/gpu/drm/amd/powerplay/hwmgr/ppatomfwctrl.c PP_ASSERT_WITH_CODE(voltage_info, PP_ASSERT_WITH_CODE 106 drivers/gpu/drm/amd/powerplay/hwmgr/ppatomfwctrl.c PP_ASSERT_WITH_CODE(voltage_info, PP_ASSERT_WITH_CODE 118 drivers/gpu/drm/amd/powerplay/hwmgr/ppatomfwctrl.c PP_ASSERT_WITH_CODE( PP_ASSERT_WITH_CODE 154 drivers/gpu/drm/amd/powerplay/hwmgr/ppatomfwctrl.c PP_ASSERT_WITH_CODE(false, PP_ASSERT_WITH_CODE 171 drivers/gpu/drm/amd/powerplay/hwmgr/ppatomfwctrl.c PP_ASSERT_WITH_CODE(table_address, PP_ASSERT_WITH_CODE 217 drivers/gpu/drm/amd/powerplay/hwmgr/ppatomfwctrl.c PP_ASSERT_WITH_CODE(gpio_lookup_table, PP_ASSERT_WITH_CODE 57 drivers/gpu/drm/amd/powerplay/hwmgr/process_pptables_v1_0.c PP_ASSERT_WITH_CODE((~powerplay_caps & ____RETIRE16____), PP_ASSERT_WITH_CODE 59 drivers/gpu/drm/amd/powerplay/hwmgr/process_pptables_v1_0.c PP_ASSERT_WITH_CODE((~powerplay_caps & ____RETIRE64____), PP_ASSERT_WITH_CODE 61 drivers/gpu/drm/amd/powerplay/hwmgr/process_pptables_v1_0.c PP_ASSERT_WITH_CODE((~powerplay_caps & ____RETIRE512____), PP_ASSERT_WITH_CODE 63 drivers/gpu/drm/amd/powerplay/hwmgr/process_pptables_v1_0.c PP_ASSERT_WITH_CODE((~powerplay_caps & ____RETIRE1024____), PP_ASSERT_WITH_CODE 65 drivers/gpu/drm/amd/powerplay/hwmgr/process_pptables_v1_0.c PP_ASSERT_WITH_CODE((~powerplay_caps & ____RETIRE2048____), PP_ASSERT_WITH_CODE 165 drivers/gpu/drm/amd/powerplay/hwmgr/process_pptables_v1_0.c PP_ASSERT_WITH_CODE((0 != vddc_lookup_pp_tables->ucNumEntries), PP_ASSERT_WITH_CODE 325 drivers/gpu/drm/amd/powerplay/hwmgr/process_pptables_v1_0.c PP_ASSERT_WITH_CODE((0 != clk_volt_pp_table->count), PP_ASSERT_WITH_CODE 355 drivers/gpu/drm/amd/powerplay/hwmgr/process_pptables_v1_0.c PP_ASSERT_WITH_CODE((0 != limitable->ucNumEntries), "Invalid PowerPlay Table!", return -1); PP_ASSERT_WITH_CODE 378 drivers/gpu/drm/amd/powerplay/hwmgr/process_pptables_v1_0.c PP_ASSERT_WITH_CODE((0 != mclk_dep_table->ucNumEntries), PP_ASSERT_WITH_CODE 425 drivers/gpu/drm/amd/powerplay/hwmgr/process_pptables_v1_0.c PP_ASSERT_WITH_CODE((0 != tonga_table->ucNumEntries), PP_ASSERT_WITH_CODE 457 drivers/gpu/drm/amd/powerplay/hwmgr/process_pptables_v1_0.c PP_ASSERT_WITH_CODE((0 != polaris_table->ucNumEntries), PP_ASSERT_WITH_CODE 507 drivers/gpu/drm/amd/powerplay/hwmgr/process_pptables_v1_0.c PP_ASSERT_WITH_CODE((atom_pcie_table->ucNumEntries != 0), PP_ASSERT_WITH_CODE 546 drivers/gpu/drm/amd/powerplay/hwmgr/process_pptables_v1_0.c PP_ASSERT_WITH_CODE((atom_pcie_table->ucNumEntries != 0), PP_ASSERT_WITH_CODE 698 drivers/gpu/drm/amd/powerplay/hwmgr/process_pptables_v1_0.c PP_ASSERT_WITH_CODE((0 != mm_dependency_table->ucNumEntries), PP_ASSERT_WITH_CODE 747 drivers/gpu/drm/amd/powerplay/hwmgr/process_pptables_v1_0.c PP_ASSERT_WITH_CODE(false, PP_ASSERT_WITH_CODE 894 drivers/gpu/drm/amd/powerplay/hwmgr/process_pptables_v1_0.c PP_ASSERT_WITH_CODE((0 != powerplay_table->usThermalControllerOffset), PP_ASSERT_WITH_CODE 928 drivers/gpu/drm/amd/powerplay/hwmgr/process_pptables_v1_0.c PP_ASSERT_WITH_CODE((0 != powerplay_table->usFanTableOffset), PP_ASSERT_WITH_CODE 930 drivers/gpu/drm/amd/powerplay/hwmgr/process_pptables_v1_0.c PP_ASSERT_WITH_CODE((0 < fan_table->ucRevId), PP_ASSERT_WITH_CODE 1047 drivers/gpu/drm/amd/powerplay/hwmgr/process_pptables_v1_0.c PP_ASSERT_WITH_CODE((ATOM_Tonga_TABLE_REVISION_TONGA <= PP_ASSERT_WITH_CODE 1050 drivers/gpu/drm/amd/powerplay/hwmgr/process_pptables_v1_0.c PP_ASSERT_WITH_CODE((0 != powerplay_table->usStateArrayOffset), PP_ASSERT_WITH_CODE 1052 drivers/gpu/drm/amd/powerplay/hwmgr/process_pptables_v1_0.c PP_ASSERT_WITH_CODE((0 < powerplay_table->sHeader.usStructureSize), PP_ASSERT_WITH_CODE 1054 drivers/gpu/drm/amd/powerplay/hwmgr/process_pptables_v1_0.c PP_ASSERT_WITH_CODE((0 < state_arrays->ucNumEntries), PP_ASSERT_WITH_CODE 1067 drivers/gpu/drm/amd/powerplay/hwmgr/process_pptables_v1_0.c PP_ASSERT_WITH_CODE((NULL != hwmgr->pptable), PP_ASSERT_WITH_CODE 1072 drivers/gpu/drm/amd/powerplay/hwmgr/process_pptables_v1_0.c PP_ASSERT_WITH_CODE((NULL != powerplay_table), PP_ASSERT_WITH_CODE 1077 drivers/gpu/drm/amd/powerplay/hwmgr/process_pptables_v1_0.c PP_ASSERT_WITH_CODE((result == 0), PP_ASSERT_WITH_CODE 1083 drivers/gpu/drm/amd/powerplay/hwmgr/process_pptables_v1_0.c PP_ASSERT_WITH_CODE((result == 0), PP_ASSERT_WITH_CODE 1088 drivers/gpu/drm/amd/powerplay/hwmgr/process_pptables_v1_0.c PP_ASSERT_WITH_CODE((result == 0), PP_ASSERT_WITH_CODE 1093 drivers/gpu/drm/amd/powerplay/hwmgr/process_pptables_v1_0.c PP_ASSERT_WITH_CODE((result == 0), PP_ASSERT_WITH_CODE 1098 drivers/gpu/drm/amd/powerplay/hwmgr/process_pptables_v1_0.c PP_ASSERT_WITH_CODE((result == 0), PP_ASSERT_WITH_CODE 1103 drivers/gpu/drm/amd/powerplay/hwmgr/process_pptables_v1_0.c PP_ASSERT_WITH_CODE((result == 0), PP_ASSERT_WITH_CODE 1166 drivers/gpu/drm/amd/powerplay/hwmgr/process_pptables_v1_0.c PP_ASSERT_WITH_CODE((NULL != pp_table), PP_ASSERT_WITH_CODE 1168 drivers/gpu/drm/amd/powerplay/hwmgr/process_pptables_v1_0.c PP_ASSERT_WITH_CODE((pp_table->sHeader.ucTableFormatRevision >= PP_ASSERT_WITH_CODE 1242 drivers/gpu/drm/amd/powerplay/hwmgr/process_pptables_v1_0.c PP_ASSERT_WITH_CODE((i < vce_state_table->ucNumEntries), PP_ASSERT_WITH_CODE 1298 drivers/gpu/drm/amd/powerplay/hwmgr/process_pptables_v1_0.c PP_ASSERT_WITH_CODE((NULL != pp_table), "Missing PowerPlay Table!", return -1;); PP_ASSERT_WITH_CODE 1306 drivers/gpu/drm/amd/powerplay/hwmgr/process_pptables_v1_0.c PP_ASSERT_WITH_CODE((0 < pp_table->usStateArrayOffset), PP_ASSERT_WITH_CODE 1308 drivers/gpu/drm/amd/powerplay/hwmgr/process_pptables_v1_0.c PP_ASSERT_WITH_CODE((0 < state_arrays->ucNumEntries), PP_ASSERT_WITH_CODE 1310 drivers/gpu/drm/amd/powerplay/hwmgr/process_pptables_v1_0.c PP_ASSERT_WITH_CODE((entry_index <= state_arrays->ucNumEntries), PP_ASSERT_WITH_CODE 856 drivers/gpu/drm/amd/powerplay/hwmgr/processpptables.c PP_ASSERT_WITH_CODE(NULL != powerplay_tab, PP_ASSERT_WITH_CODE 1633 drivers/gpu/drm/amd/powerplay/hwmgr/processpptables.c PP_ASSERT_WITH_CODE((result == 0), PP_ASSERT_WITH_CODE 1639 drivers/gpu/drm/amd/powerplay/hwmgr/processpptables.c PP_ASSERT_WITH_CODE((result == 0), PP_ASSERT_WITH_CODE 1644 drivers/gpu/drm/amd/powerplay/hwmgr/processpptables.c PP_ASSERT_WITH_CODE((result == 0), PP_ASSERT_WITH_CODE 1649 drivers/gpu/drm/amd/powerplay/hwmgr/processpptables.c PP_ASSERT_WITH_CODE((result == 0), PP_ASSERT_WITH_CODE 1655 drivers/gpu/drm/amd/powerplay/hwmgr/processpptables.c PP_ASSERT_WITH_CODE((result == 0), PP_ASSERT_WITH_CODE 1660 drivers/gpu/drm/amd/powerplay/hwmgr/processpptables.c PP_ASSERT_WITH_CODE((result == 0), PP_ASSERT_WITH_CODE 1665 drivers/gpu/drm/amd/powerplay/hwmgr/processpptables.c PP_ASSERT_WITH_CODE((result == 0), PP_ASSERT_WITH_CODE 202 drivers/gpu/drm/amd/powerplay/hwmgr/smu10_hwmgr.c PP_ASSERT_WITH_CODE(!smu10_display_clock_voltage_request(hwmgr, &clock_req), PP_ASSERT_WITH_CODE 446 drivers/gpu/drm/amd/powerplay/hwmgr/smu10_hwmgr.c PP_ASSERT_WITH_CODE((0 == result), PP_ASSERT_WITH_CODE 115 drivers/gpu/drm/amd/powerplay/hwmgr/smu7_hwmgr.c PP_ASSERT_WITH_CODE((PhwVIslands_Magic == hw_ps->magic), PP_ASSERT_WITH_CODE 125 drivers/gpu/drm/amd/powerplay/hwmgr/smu7_hwmgr.c PP_ASSERT_WITH_CODE((PhwVIslands_Magic == hw_ps->magic), PP_ASSERT_WITH_CODE 166 drivers/gpu/drm/amd/powerplay/hwmgr/smu7_hwmgr.c PP_ASSERT_WITH_CODE((7 >= link_width), PP_ASSERT_WITH_CODE 227 drivers/gpu/drm/amd/powerplay/hwmgr/smu7_hwmgr.c PP_ASSERT_WITH_CODE((NULL != voltage_table), PP_ASSERT_WITH_CODE 262 drivers/gpu/drm/amd/powerplay/hwmgr/smu7_hwmgr.c PP_ASSERT_WITH_CODE((0 == result), PP_ASSERT_WITH_CODE 273 drivers/gpu/drm/amd/powerplay/hwmgr/smu7_hwmgr.c PP_ASSERT_WITH_CODE((0 == result), PP_ASSERT_WITH_CODE 282 drivers/gpu/drm/amd/powerplay/hwmgr/smu7_hwmgr.c PP_ASSERT_WITH_CODE((0 == result), PP_ASSERT_WITH_CODE 292 drivers/gpu/drm/amd/powerplay/hwmgr/smu7_hwmgr.c PP_ASSERT_WITH_CODE((0 == result), PP_ASSERT_WITH_CODE 301 drivers/gpu/drm/amd/powerplay/hwmgr/smu7_hwmgr.c PP_ASSERT_WITH_CODE((0 == result), PP_ASSERT_WITH_CODE 310 drivers/gpu/drm/amd/powerplay/hwmgr/smu7_hwmgr.c PP_ASSERT_WITH_CODE((0 == result), PP_ASSERT_WITH_CODE 321 drivers/gpu/drm/amd/powerplay/hwmgr/smu7_hwmgr.c PP_ASSERT_WITH_CODE((0 == result), PP_ASSERT_WITH_CODE 326 drivers/gpu/drm/amd/powerplay/hwmgr/smu7_hwmgr.c PP_ASSERT_WITH_CODE( PP_ASSERT_WITH_CODE 333 drivers/gpu/drm/amd/powerplay/hwmgr/smu7_hwmgr.c PP_ASSERT_WITH_CODE( PP_ASSERT_WITH_CODE 340 drivers/gpu/drm/amd/powerplay/hwmgr/smu7_hwmgr.c PP_ASSERT_WITH_CODE( PP_ASSERT_WITH_CODE 347 drivers/gpu/drm/amd/powerplay/hwmgr/smu7_hwmgr.c PP_ASSERT_WITH_CODE( PP_ASSERT_WITH_CODE 537 drivers/gpu/drm/amd/powerplay/hwmgr/smu7_hwmgr.c PP_ASSERT_WITH_CODE((data->use_pcie_performance_levels || PP_ASSERT_WITH_CODE 679 drivers/gpu/drm/amd/powerplay/hwmgr/smu7_hwmgr.c PP_ASSERT_WITH_CODE(allowed_vdd_sclk_table != NULL, PP_ASSERT_WITH_CODE 681 drivers/gpu/drm/amd/powerplay/hwmgr/smu7_hwmgr.c PP_ASSERT_WITH_CODE(allowed_vdd_sclk_table->count >= 1, PP_ASSERT_WITH_CODE 684 drivers/gpu/drm/amd/powerplay/hwmgr/smu7_hwmgr.c PP_ASSERT_WITH_CODE(allowed_vdd_mclk_table != NULL, PP_ASSERT_WITH_CODE 686 drivers/gpu/drm/amd/powerplay/hwmgr/smu7_hwmgr.c PP_ASSERT_WITH_CODE(allowed_vdd_mclk_table->count >= 1, PP_ASSERT_WITH_CODE 703 drivers/gpu/drm/amd/powerplay/hwmgr/smu7_hwmgr.c PP_ASSERT_WITH_CODE(allowed_vdd_mclk_table != NULL, PP_ASSERT_WITH_CODE 770 drivers/gpu/drm/amd/powerplay/hwmgr/smu7_hwmgr.c PP_ASSERT_WITH_CODE(dep_sclk_table != NULL, PP_ASSERT_WITH_CODE 773 drivers/gpu/drm/amd/powerplay/hwmgr/smu7_hwmgr.c PP_ASSERT_WITH_CODE(dep_sclk_table->count >= 1, PP_ASSERT_WITH_CODE 777 drivers/gpu/drm/amd/powerplay/hwmgr/smu7_hwmgr.c PP_ASSERT_WITH_CODE(dep_mclk_table != NULL, PP_ASSERT_WITH_CODE 780 drivers/gpu/drm/amd/powerplay/hwmgr/smu7_hwmgr.c PP_ASSERT_WITH_CODE(dep_mclk_table->count >= 1, PP_ASSERT_WITH_CODE 1018 drivers/gpu/drm/amd/powerplay/hwmgr/smu7_hwmgr.c PP_ASSERT_WITH_CODE(false, PP_ASSERT_WITH_CODE 1024 drivers/gpu/drm/amd/powerplay/hwmgr/smu7_hwmgr.c PP_ASSERT_WITH_CODE(false, PP_ASSERT_WITH_CODE 1039 drivers/gpu/drm/amd/powerplay/hwmgr/smu7_hwmgr.c PP_ASSERT_WITH_CODE(false, PP_ASSERT_WITH_CODE 1090 drivers/gpu/drm/amd/powerplay/hwmgr/smu7_hwmgr.c PP_ASSERT_WITH_CODE( PP_ASSERT_WITH_CODE 1101 drivers/gpu/drm/amd/powerplay/hwmgr/smu7_hwmgr.c PP_ASSERT_WITH_CODE( PP_ASSERT_WITH_CODE 1172 drivers/gpu/drm/amd/powerplay/hwmgr/smu7_hwmgr.c PP_ASSERT_WITH_CODE( PP_ASSERT_WITH_CODE 1181 drivers/gpu/drm/amd/powerplay/hwmgr/smu7_hwmgr.c PP_ASSERT_WITH_CODE((0 == smum_send_msg_to_smc(hwmgr, PP_ASSERT_WITH_CODE 1196 drivers/gpu/drm/amd/powerplay/hwmgr/smu7_hwmgr.c PP_ASSERT_WITH_CODE(true == smum_is_dpm_running(hwmgr), PP_ASSERT_WITH_CODE 1204 drivers/gpu/drm/amd/powerplay/hwmgr/smu7_hwmgr.c PP_ASSERT_WITH_CODE(true == smum_is_dpm_running(hwmgr), PP_ASSERT_WITH_CODE 1226 drivers/gpu/drm/amd/powerplay/hwmgr/smu7_hwmgr.c PP_ASSERT_WITH_CODE( PP_ASSERT_WITH_CODE 1235 drivers/gpu/drm/amd/powerplay/hwmgr/smu7_hwmgr.c PP_ASSERT_WITH_CODE(true == smum_is_dpm_running(hwmgr), PP_ASSERT_WITH_CODE 1333 drivers/gpu/drm/amd/powerplay/hwmgr/smu7_hwmgr.c PP_ASSERT_WITH_CODE(tmp_result == 0, PP_ASSERT_WITH_CODE 1338 drivers/gpu/drm/amd/powerplay/hwmgr/smu7_hwmgr.c PP_ASSERT_WITH_CODE((0 == tmp_result), PP_ASSERT_WITH_CODE 1355 drivers/gpu/drm/amd/powerplay/hwmgr/smu7_hwmgr.c PP_ASSERT_WITH_CODE((0 == tmp_result), PP_ASSERT_WITH_CODE 1360 drivers/gpu/drm/amd/powerplay/hwmgr/smu7_hwmgr.c PP_ASSERT_WITH_CODE((0 == tmp_result), PP_ASSERT_WITH_CODE 1364 drivers/gpu/drm/amd/powerplay/hwmgr/smu7_hwmgr.c PP_ASSERT_WITH_CODE((0 == tmp_result), PP_ASSERT_WITH_CODE 1368 drivers/gpu/drm/amd/powerplay/hwmgr/smu7_hwmgr.c PP_ASSERT_WITH_CODE((0 == tmp_result), PP_ASSERT_WITH_CODE 1373 drivers/gpu/drm/amd/powerplay/hwmgr/smu7_hwmgr.c PP_ASSERT_WITH_CODE((0 == tmp_result), PP_ASSERT_WITH_CODE 1379 drivers/gpu/drm/amd/powerplay/hwmgr/smu7_hwmgr.c PP_ASSERT_WITH_CODE(0 == result, PP_ASSERT_WITH_CODE 1383 drivers/gpu/drm/amd/powerplay/hwmgr/smu7_hwmgr.c PP_ASSERT_WITH_CODE((0 == tmp_result), PP_ASSERT_WITH_CODE 1387 drivers/gpu/drm/amd/powerplay/hwmgr/smu7_hwmgr.c PP_ASSERT_WITH_CODE((0 == tmp_result), PP_ASSERT_WITH_CODE 1393 drivers/gpu/drm/amd/powerplay/hwmgr/smu7_hwmgr.c PP_ASSERT_WITH_CODE((0 == tmp_result), PP_ASSERT_WITH_CODE 1397 drivers/gpu/drm/amd/powerplay/hwmgr/smu7_hwmgr.c PP_ASSERT_WITH_CODE((0 == tmp_result), PP_ASSERT_WITH_CODE 1401 drivers/gpu/drm/amd/powerplay/hwmgr/smu7_hwmgr.c PP_ASSERT_WITH_CODE((0 == tmp_result), PP_ASSERT_WITH_CODE 1405 drivers/gpu/drm/amd/powerplay/hwmgr/smu7_hwmgr.c PP_ASSERT_WITH_CODE((0 == tmp_result), PP_ASSERT_WITH_CODE 1409 drivers/gpu/drm/amd/powerplay/hwmgr/smu7_hwmgr.c PP_ASSERT_WITH_CODE((tmp_result == 0), PP_ASSERT_WITH_CODE 1413 drivers/gpu/drm/amd/powerplay/hwmgr/smu7_hwmgr.c PP_ASSERT_WITH_CODE((0 == tmp_result), PP_ASSERT_WITH_CODE 1417 drivers/gpu/drm/amd/powerplay/hwmgr/smu7_hwmgr.c PP_ASSERT_WITH_CODE((0 == tmp_result), PP_ASSERT_WITH_CODE 1421 drivers/gpu/drm/amd/powerplay/hwmgr/smu7_hwmgr.c PP_ASSERT_WITH_CODE((0 == tmp_result), PP_ASSERT_WITH_CODE 1425 drivers/gpu/drm/amd/powerplay/hwmgr/smu7_hwmgr.c PP_ASSERT_WITH_CODE((0 == tmp_result), PP_ASSERT_WITH_CODE 1429 drivers/gpu/drm/amd/powerplay/hwmgr/smu7_hwmgr.c PP_ASSERT_WITH_CODE((0 == tmp_result), PP_ASSERT_WITH_CODE 1433 drivers/gpu/drm/amd/powerplay/hwmgr/smu7_hwmgr.c PP_ASSERT_WITH_CODE((0 == tmp_result), PP_ASSERT_WITH_CODE 1447 drivers/gpu/drm/amd/powerplay/hwmgr/smu7_hwmgr.c PP_ASSERT_WITH_CODE(!smum_send_msg_to_smc( PP_ASSERT_WITH_CODE 1454 drivers/gpu/drm/amd/powerplay/hwmgr/smu7_hwmgr.c PP_ASSERT_WITH_CODE(!smum_send_msg_to_smc( PP_ASSERT_WITH_CODE 1492 drivers/gpu/drm/amd/powerplay/hwmgr/smu7_hwmgr.c PP_ASSERT_WITH_CODE((tmp_result == 0), PP_ASSERT_WITH_CODE 1496 drivers/gpu/drm/amd/powerplay/hwmgr/smu7_hwmgr.c PP_ASSERT_WITH_CODE((tmp_result == 0), PP_ASSERT_WITH_CODE 1500 drivers/gpu/drm/amd/powerplay/hwmgr/smu7_hwmgr.c PP_ASSERT_WITH_CODE((tmp_result == 0), PP_ASSERT_WITH_CODE 1509 drivers/gpu/drm/amd/powerplay/hwmgr/smu7_hwmgr.c PP_ASSERT_WITH_CODE((tmp_result == 0), PP_ASSERT_WITH_CODE 1513 drivers/gpu/drm/amd/powerplay/hwmgr/smu7_hwmgr.c PP_ASSERT_WITH_CODE((tmp_result == 0), PP_ASSERT_WITH_CODE 1517 drivers/gpu/drm/amd/powerplay/hwmgr/smu7_hwmgr.c PP_ASSERT_WITH_CODE((tmp_result == 0), PP_ASSERT_WITH_CODE 1521 drivers/gpu/drm/amd/powerplay/hwmgr/smu7_hwmgr.c PP_ASSERT_WITH_CODE((tmp_result == 0), PP_ASSERT_WITH_CODE 1525 drivers/gpu/drm/amd/powerplay/hwmgr/smu7_hwmgr.c PP_ASSERT_WITH_CODE((tmp_result == 0), PP_ASSERT_WITH_CODE 1529 drivers/gpu/drm/amd/powerplay/hwmgr/smu7_hwmgr.c PP_ASSERT_WITH_CODE((tmp_result == 0), PP_ASSERT_WITH_CODE 1533 drivers/gpu/drm/amd/powerplay/hwmgr/smu7_hwmgr.c PP_ASSERT_WITH_CODE((tmp_result == 0), PP_ASSERT_WITH_CODE 1537 drivers/gpu/drm/amd/powerplay/hwmgr/smu7_hwmgr.c PP_ASSERT_WITH_CODE((tmp_result == 0), PP_ASSERT_WITH_CODE 1729 drivers/gpu/drm/amd/powerplay/hwmgr/smu7_hwmgr.c PP_ASSERT_WITH_CODE((vddgfx < 2000 && vddgfx != 0), "Invalid VDDGFX value!", return -EINVAL); PP_ASSERT_WITH_CODE 1894 drivers/gpu/drm/amd/powerplay/hwmgr/smu7_hwmgr.c PP_ASSERT_WITH_CODE((NULL != look_up_table), PP_ASSERT_WITH_CODE 1896 drivers/gpu/drm/amd/powerplay/hwmgr/smu7_hwmgr.c PP_ASSERT_WITH_CODE((0 != look_up_table->count), PP_ASSERT_WITH_CODE 1900 drivers/gpu/drm/amd/powerplay/hwmgr/smu7_hwmgr.c PP_ASSERT_WITH_CODE((i >= look_up_table->count), PP_ASSERT_WITH_CODE 2000 drivers/gpu/drm/amd/powerplay/hwmgr/smu7_hwmgr.c PP_ASSERT_WITH_CODE(0 != lookup_table->count, PP_ASSERT_WITH_CODE 2080 drivers/gpu/drm/amd/powerplay/hwmgr/smu7_hwmgr.c PP_ASSERT_WITH_CODE(allowed_sclk_vdd_table != NULL, PP_ASSERT_WITH_CODE 2083 drivers/gpu/drm/amd/powerplay/hwmgr/smu7_hwmgr.c PP_ASSERT_WITH_CODE(allowed_sclk_vdd_table->count >= 1, PP_ASSERT_WITH_CODE 2087 drivers/gpu/drm/amd/powerplay/hwmgr/smu7_hwmgr.c PP_ASSERT_WITH_CODE(allowed_mclk_vdd_table != NULL, PP_ASSERT_WITH_CODE 2090 drivers/gpu/drm/amd/powerplay/hwmgr/smu7_hwmgr.c PP_ASSERT_WITH_CODE(allowed_mclk_vdd_table->count >= 1, PP_ASSERT_WITH_CODE 2462 drivers/gpu/drm/amd/powerplay/hwmgr/smu7_hwmgr.c PP_ASSERT_WITH_CODE(allowed_sclk_vddc_table != NULL, PP_ASSERT_WITH_CODE 2465 drivers/gpu/drm/amd/powerplay/hwmgr/smu7_hwmgr.c PP_ASSERT_WITH_CODE(allowed_sclk_vddc_table->count >= 1, PP_ASSERT_WITH_CODE 2469 drivers/gpu/drm/amd/powerplay/hwmgr/smu7_hwmgr.c PP_ASSERT_WITH_CODE(allowed_mclk_vddc_table != NULL, PP_ASSERT_WITH_CODE 2472 drivers/gpu/drm/amd/powerplay/hwmgr/smu7_hwmgr.c PP_ASSERT_WITH_CODE(allowed_mclk_vddc_table->count >= 1, PP_ASSERT_WITH_CODE 2906 drivers/gpu/drm/amd/powerplay/hwmgr/smu7_hwmgr.c PP_ASSERT_WITH_CODE(smu7_ps->performance_level_count == 2, PP_ASSERT_WITH_CODE 3171 drivers/gpu/drm/amd/powerplay/hwmgr/smu7_hwmgr.c PP_ASSERT_WITH_CODE( PP_ASSERT_WITH_CODE 3176 drivers/gpu/drm/amd/powerplay/hwmgr/smu7_hwmgr.c PP_ASSERT_WITH_CODE( PP_ASSERT_WITH_CODE 3335 drivers/gpu/drm/amd/powerplay/hwmgr/smu7_hwmgr.c PP_ASSERT_WITH_CODE( PP_ASSERT_WITH_CODE 3340 drivers/gpu/drm/amd/powerplay/hwmgr/smu7_hwmgr.c PP_ASSERT_WITH_CODE( PP_ASSERT_WITH_CODE 3730 drivers/gpu/drm/amd/powerplay/hwmgr/smu7_hwmgr.c PP_ASSERT_WITH_CODE(true == smum_is_dpm_running(hwmgr), PP_ASSERT_WITH_CODE 3733 drivers/gpu/drm/amd/powerplay/hwmgr/smu7_hwmgr.c PP_ASSERT_WITH_CODE(0 == smum_send_msg_to_smc(hwmgr, PP_ASSERT_WITH_CODE 3742 drivers/gpu/drm/amd/powerplay/hwmgr/smu7_hwmgr.c PP_ASSERT_WITH_CODE(true == smum_is_dpm_running(hwmgr), PP_ASSERT_WITH_CODE 3745 drivers/gpu/drm/amd/powerplay/hwmgr/smu7_hwmgr.c PP_ASSERT_WITH_CODE(0 == smum_send_msg_to_smc(hwmgr, PP_ASSERT_WITH_CODE 3785 drivers/gpu/drm/amd/powerplay/hwmgr/smu7_hwmgr.c PP_ASSERT_WITH_CODE((0 == result), PP_ASSERT_WITH_CODE 3794 drivers/gpu/drm/amd/powerplay/hwmgr/smu7_hwmgr.c PP_ASSERT_WITH_CODE((0 == result), PP_ASSERT_WITH_CODE 3829 drivers/gpu/drm/amd/powerplay/hwmgr/smu7_hwmgr.c PP_ASSERT_WITH_CODE((smu7_ps->performance_level_count >= 1), PP_ASSERT_WITH_CODE 3884 drivers/gpu/drm/amd/powerplay/hwmgr/smu7_hwmgr.c PP_ASSERT_WITH_CODE(true == smum_is_dpm_running(hwmgr), PP_ASSERT_WITH_CODE 3887 drivers/gpu/drm/amd/powerplay/hwmgr/smu7_hwmgr.c PP_ASSERT_WITH_CODE(0 == smum_send_msg_to_smc(hwmgr, PP_ASSERT_WITH_CODE 3896 drivers/gpu/drm/amd/powerplay/hwmgr/smu7_hwmgr.c PP_ASSERT_WITH_CODE(true == smum_is_dpm_running(hwmgr), PP_ASSERT_WITH_CODE 3899 drivers/gpu/drm/amd/powerplay/hwmgr/smu7_hwmgr.c PP_ASSERT_WITH_CODE(0 == smum_send_msg_to_smc(hwmgr, PP_ASSERT_WITH_CODE 3967 drivers/gpu/drm/amd/powerplay/hwmgr/smu7_hwmgr.c PP_ASSERT_WITH_CODE((0 == tmp_result), PP_ASSERT_WITH_CODE 3975 drivers/gpu/drm/amd/powerplay/hwmgr/smu7_hwmgr.c PP_ASSERT_WITH_CODE((0 == tmp_result), PP_ASSERT_WITH_CODE 3981 drivers/gpu/drm/amd/powerplay/hwmgr/smu7_hwmgr.c PP_ASSERT_WITH_CODE((0 == tmp_result), PP_ASSERT_WITH_CODE 3985 drivers/gpu/drm/amd/powerplay/hwmgr/smu7_hwmgr.c PP_ASSERT_WITH_CODE((0 == tmp_result), PP_ASSERT_WITH_CODE 3990 drivers/gpu/drm/amd/powerplay/hwmgr/smu7_hwmgr.c PP_ASSERT_WITH_CODE((0 == tmp_result), PP_ASSERT_WITH_CODE 3995 drivers/gpu/drm/amd/powerplay/hwmgr/smu7_hwmgr.c PP_ASSERT_WITH_CODE((0 == tmp_result), PP_ASSERT_WITH_CODE 4000 drivers/gpu/drm/amd/powerplay/hwmgr/smu7_hwmgr.c PP_ASSERT_WITH_CODE((0 == tmp_result), PP_ASSERT_WITH_CODE 4005 drivers/gpu/drm/amd/powerplay/hwmgr/smu7_hwmgr.c PP_ASSERT_WITH_CODE((0 == tmp_result), PP_ASSERT_WITH_CODE 4010 drivers/gpu/drm/amd/powerplay/hwmgr/smu7_hwmgr.c PP_ASSERT_WITH_CODE((0 == tmp_result), PP_ASSERT_WITH_CODE 4015 drivers/gpu/drm/amd/powerplay/hwmgr/smu7_hwmgr.c PP_ASSERT_WITH_CODE((0 == tmp_result), PP_ASSERT_WITH_CODE 4023 drivers/gpu/drm/amd/powerplay/hwmgr/smu7_hwmgr.c PP_ASSERT_WITH_CODE((0 == tmp_result), PP_ASSERT_WITH_CODE 4373 drivers/gpu/drm/amd/powerplay/hwmgr/smu7_hwmgr.c PP_ASSERT_WITH_CODE((0 == tmp_result), PP_ASSERT_WITH_CODE 4377 drivers/gpu/drm/amd/powerplay/hwmgr/smu7_hwmgr.c PP_ASSERT_WITH_CODE((0 == tmp_result), PP_ASSERT_WITH_CODE 4381 drivers/gpu/drm/amd/powerplay/hwmgr/smu7_hwmgr.c PP_ASSERT_WITH_CODE((0 == tmp_result), PP_ASSERT_WITH_CODE 4385 drivers/gpu/drm/amd/powerplay/hwmgr/smu7_hwmgr.c PP_ASSERT_WITH_CODE((0 == tmp_result), PP_ASSERT_WITH_CODE 4389 drivers/gpu/drm/amd/powerplay/hwmgr/smu7_hwmgr.c PP_ASSERT_WITH_CODE((0 == tmp_result), PP_ASSERT_WITH_CODE 4393 drivers/gpu/drm/amd/powerplay/hwmgr/smu7_hwmgr.c PP_ASSERT_WITH_CODE((0 == tmp_result), PP_ASSERT_WITH_CODE 4861 drivers/gpu/drm/amd/powerplay/hwmgr/smu7_hwmgr.c PP_ASSERT_WITH_CODE(input, "NULL user input for clock and voltage", PP_ASSERT_WITH_CODE 4872 drivers/gpu/drm/amd/powerplay/hwmgr/smu7_hwmgr.c PP_ASSERT_WITH_CODE((podn_dpm_table_in_backend && podn_vdd_dep_in_backend), PP_ASSERT_WITH_CODE 4879 drivers/gpu/drm/amd/powerplay/hwmgr/smu7_hwmgr.c PP_ASSERT_WITH_CODE((podn_dpm_table_in_backend && podn_vdd_dep_in_backend), PP_ASSERT_WITH_CODE 5100 drivers/gpu/drm/amd/powerplay/hwmgr/smu7_hwmgr.c PP_ASSERT_WITH_CODE((0 == result), PP_ASSERT_WITH_CODE 5174 drivers/gpu/drm/amd/powerplay/hwmgr/smu7_hwmgr.c PP_ASSERT_WITH_CODE((clock >= min), "Engine clock can't satisfy stutter requirement!", return 0); PP_ASSERT_WITH_CODE 902 drivers/gpu/drm/amd/powerplay/hwmgr/smu7_powertune.c PP_ASSERT_WITH_CODE((config_regs != NULL), "Invalid config register table.", return -EINVAL); PP_ASSERT_WITH_CODE 982 drivers/gpu/drm/amd/powerplay/hwmgr/smu7_powertune.c PP_ASSERT_WITH_CODE((result == 0), "DIDT Config failed.", goto error); PP_ASSERT_WITH_CODE 984 drivers/gpu/drm/amd/powerplay/hwmgr/smu7_powertune.c PP_ASSERT_WITH_CODE((result == 0), "DIDT Config failed.", goto error); PP_ASSERT_WITH_CODE 987 drivers/gpu/drm/amd/powerplay/hwmgr/smu7_powertune.c PP_ASSERT_WITH_CODE((result == 0), "DIDT Config failed.", goto error); PP_ASSERT_WITH_CODE 992 drivers/gpu/drm/amd/powerplay/hwmgr/smu7_powertune.c PP_ASSERT_WITH_CODE((result == 0), "DIDT Config failed.", goto error); PP_ASSERT_WITH_CODE 995 drivers/gpu/drm/amd/powerplay/hwmgr/smu7_powertune.c PP_ASSERT_WITH_CODE((result == 0), "DIDT Config failed.", goto error); PP_ASSERT_WITH_CODE 997 drivers/gpu/drm/amd/powerplay/hwmgr/smu7_powertune.c PP_ASSERT_WITH_CODE((result == 0), "DIDT Config failed.", goto error); PP_ASSERT_WITH_CODE 1000 drivers/gpu/drm/amd/powerplay/hwmgr/smu7_powertune.c PP_ASSERT_WITH_CODE((result == 0), "DIDT Config failed.", goto error); PP_ASSERT_WITH_CODE 1002 drivers/gpu/drm/amd/powerplay/hwmgr/smu7_powertune.c PP_ASSERT_WITH_CODE((result == 0), "DIDT Config failed.", goto error); PP_ASSERT_WITH_CODE 1008 drivers/gpu/drm/amd/powerplay/hwmgr/smu7_powertune.c PP_ASSERT_WITH_CODE((result == 0), "EnableDiDt failed.", goto error); PP_ASSERT_WITH_CODE 1013 drivers/gpu/drm/amd/powerplay/hwmgr/smu7_powertune.c PP_ASSERT_WITH_CODE((0 == result), PP_ASSERT_WITH_CODE 1040 drivers/gpu/drm/amd/powerplay/hwmgr/smu7_powertune.c PP_ASSERT_WITH_CODE((result == 0), PP_ASSERT_WITH_CODE 1046 drivers/gpu/drm/amd/powerplay/hwmgr/smu7_powertune.c PP_ASSERT_WITH_CODE((0 == result), PP_ASSERT_WITH_CODE 1067 drivers/gpu/drm/amd/powerplay/hwmgr/smu7_powertune.c PP_ASSERT_WITH_CODE((0 == smc_result), PP_ASSERT_WITH_CODE 1083 drivers/gpu/drm/amd/powerplay/hwmgr/smu7_powertune.c PP_ASSERT_WITH_CODE((smc_result == 0), PP_ASSERT_WITH_CODE 1128 drivers/gpu/drm/amd/powerplay/hwmgr/smu7_powertune.c PP_ASSERT_WITH_CODE((0 == smc_result), PP_ASSERT_WITH_CODE 1138 drivers/gpu/drm/amd/powerplay/hwmgr/smu7_powertune.c PP_ASSERT_WITH_CODE((0 == smc_result), PP_ASSERT_WITH_CODE 1167 drivers/gpu/drm/amd/powerplay/hwmgr/smu7_powertune.c PP_ASSERT_WITH_CODE((smc_result == 0), PP_ASSERT_WITH_CODE 1176 drivers/gpu/drm/amd/powerplay/hwmgr/smu7_powertune.c PP_ASSERT_WITH_CODE((smc_result == 0), PP_ASSERT_WITH_CODE 1185 drivers/gpu/drm/amd/powerplay/hwmgr/smu7_powertune.c PP_ASSERT_WITH_CODE((smc_result == 0), PP_ASSERT_WITH_CODE 457 drivers/gpu/drm/amd/powerplay/hwmgr/smu8_hwmgr.c PP_ASSERT_WITH_CODE((0 == ret && NULL != table), PP_ASSERT_WITH_CODE 463 drivers/gpu/drm/amd/powerplay/hwmgr/smu8_hwmgr.c PP_ASSERT_WITH_CODE((vddc_table->count <= SMU8_MAX_HARDWARE_POWERLEVELS), PP_ASSERT_WITH_CODE 465 drivers/gpu/drm/amd/powerplay/hwmgr/smu8_hwmgr.c PP_ASSERT_WITH_CODE((vdd_gfx_table->count <= SMU8_MAX_HARDWARE_POWERLEVELS), PP_ASSERT_WITH_CODE 467 drivers/gpu/drm/amd/powerplay/hwmgr/smu8_hwmgr.c PP_ASSERT_WITH_CODE((acp_table->count <= SMU8_MAX_HARDWARE_POWERLEVELS), PP_ASSERT_WITH_CODE 469 drivers/gpu/drm/amd/powerplay/hwmgr/smu8_hwmgr.c PP_ASSERT_WITH_CODE((uvd_table->count <= SMU8_MAX_HARDWARE_POWERLEVELS), PP_ASSERT_WITH_CODE 471 drivers/gpu/drm/amd/powerplay/hwmgr/smu8_hwmgr.c PP_ASSERT_WITH_CODE((vce_table->count <= SMU8_MAX_HARDWARE_POWERLEVELS), PP_ASSERT_WITH_CODE 210 drivers/gpu/drm/amd/powerplay/hwmgr/smu_helper.c PP_ASSERT_WITH_CODE((NULL != vol_table), PP_ASSERT_WITH_CODE 253 drivers/gpu/drm/amd/powerplay/hwmgr/smu_helper.c PP_ASSERT_WITH_CODE((0 != dep_table->count), PP_ASSERT_WITH_CODE 256 drivers/gpu/drm/amd/powerplay/hwmgr/smu_helper.c PP_ASSERT_WITH_CODE((NULL != vol_table), PP_ASSERT_WITH_CODE 269 drivers/gpu/drm/amd/powerplay/hwmgr/smu_helper.c PP_ASSERT_WITH_CODE((0 == result), PP_ASSERT_WITH_CODE 281 drivers/gpu/drm/amd/powerplay/hwmgr/smu_helper.c PP_ASSERT_WITH_CODE((0 != dep_table->count), PP_ASSERT_WITH_CODE 284 drivers/gpu/drm/amd/powerplay/hwmgr/smu_helper.c PP_ASSERT_WITH_CODE((NULL != vol_table), PP_ASSERT_WITH_CODE 297 drivers/gpu/drm/amd/powerplay/hwmgr/smu_helper.c PP_ASSERT_WITH_CODE((0 == result), PP_ASSERT_WITH_CODE 308 drivers/gpu/drm/amd/powerplay/hwmgr/smu_helper.c PP_ASSERT_WITH_CODE((0 != lookup_table->count), PP_ASSERT_WITH_CODE 311 drivers/gpu/drm/amd/powerplay/hwmgr/smu_helper.c PP_ASSERT_WITH_CODE((NULL != vol_table), PP_ASSERT_WITH_CODE 394 drivers/gpu/drm/amd/powerplay/hwmgr/smu_helper.c PP_ASSERT_WITH_CODE((NULL != lookup_table), PP_ASSERT_WITH_CODE 396 drivers/gpu/drm/amd/powerplay/hwmgr/smu_helper.c PP_ASSERT_WITH_CODE((0 != count), PP_ASSERT_WITH_CODE 414 drivers/gpu/drm/amd/powerplay/hwmgr/smu_helper.c PP_ASSERT_WITH_CODE((NULL != voltage_table), PP_ASSERT_WITH_CODE 416 drivers/gpu/drm/amd/powerplay/hwmgr/smu_helper.c PP_ASSERT_WITH_CODE((0 != count), PP_ASSERT_WITH_CODE 468 drivers/gpu/drm/amd/powerplay/hwmgr/smu_helper.c PP_ASSERT_WITH_CODE(lookup_table->count != 0, "Lookup table is empty", return -EINVAL); PP_ASSERT_WITH_CODE 683 drivers/gpu/drm/amd/powerplay/hwmgr/smu_helper.c PP_ASSERT_WITH_CODE((0 != allowed_dep_table->count), PP_ASSERT_WITH_CODE 96 drivers/gpu/drm/amd/powerplay/hwmgr/vega10_hwmgr.c PP_ASSERT_WITH_CODE((PhwVega10_Magic == hw_ps->magic), PP_ASSERT_WITH_CODE 106 drivers/gpu/drm/amd/powerplay/hwmgr/vega10_hwmgr.c PP_ASSERT_WITH_CODE((PhwVega10_Magic == hw_ps->magic), PP_ASSERT_WITH_CODE 524 drivers/gpu/drm/amd/powerplay/hwmgr/vega10_hwmgr.c PP_ASSERT_WITH_CODE(lookup_table->count != 0, PP_ASSERT_WITH_CODE 535 drivers/gpu/drm/amd/powerplay/hwmgr/vega10_hwmgr.c PP_ASSERT_WITH_CODE(entry_id < table_info->vdd_dep_on_socclk->count, PP_ASSERT_WITH_CODE 579 drivers/gpu/drm/amd/powerplay/hwmgr/vega10_hwmgr.c PP_ASSERT_WITH_CODE(!atomctrl_get_voltage_evv_on_sclk_ai(hwmgr, PP_ASSERT_WITH_CODE 586 drivers/gpu/drm/amd/powerplay/hwmgr/vega10_hwmgr.c PP_ASSERT_WITH_CODE((vddc < 2000 && vddc != 0), PP_ASSERT_WITH_CODE 717 drivers/gpu/drm/amd/powerplay/hwmgr/vega10_hwmgr.c PP_ASSERT_WITH_CODE(lookup_table && lookup_table->count, PP_ASSERT_WITH_CODE 777 drivers/gpu/drm/amd/powerplay/hwmgr/vega10_hwmgr.c PP_ASSERT_WITH_CODE(allowed_sclk_vdd_table, PP_ASSERT_WITH_CODE 779 drivers/gpu/drm/amd/powerplay/hwmgr/vega10_hwmgr.c PP_ASSERT_WITH_CODE(allowed_sclk_vdd_table->count >= 1, PP_ASSERT_WITH_CODE 782 drivers/gpu/drm/amd/powerplay/hwmgr/vega10_hwmgr.c PP_ASSERT_WITH_CODE(allowed_mclk_vdd_table, PP_ASSERT_WITH_CODE 784 drivers/gpu/drm/amd/powerplay/hwmgr/vega10_hwmgr.c PP_ASSERT_WITH_CODE(allowed_mclk_vdd_table->count >= 1, PP_ASSERT_WITH_CODE 858 drivers/gpu/drm/amd/powerplay/hwmgr/vega10_hwmgr.c PP_ASSERT_WITH_CODE(false, PP_ASSERT_WITH_CODE 891 drivers/gpu/drm/amd/powerplay/hwmgr/vega10_hwmgr.c PP_ASSERT_WITH_CODE(!vega10_get_evv_voltages(hwmgr), PP_ASSERT_WITH_CODE 934 drivers/gpu/drm/amd/powerplay/hwmgr/vega10_hwmgr.c PP_ASSERT_WITH_CODE(data->mem_channels < ARRAY_SIZE(channel_number), PP_ASSERT_WITH_CODE 984 drivers/gpu/drm/amd/powerplay/hwmgr/vega10_hwmgr.c PP_ASSERT_WITH_CODE(!vega10_init_sclk_threshold(hwmgr), PP_ASSERT_WITH_CODE 988 drivers/gpu/drm/amd/powerplay/hwmgr/vega10_hwmgr.c PP_ASSERT_WITH_CODE(!vega10_setup_dpm_led_config(hwmgr), PP_ASSERT_WITH_CODE 1013 drivers/gpu/drm/amd/powerplay/hwmgr/vega10_hwmgr.c PP_ASSERT_WITH_CODE(vol_table, PP_ASSERT_WITH_CODE 1055 drivers/gpu/drm/amd/powerplay/hwmgr/vega10_hwmgr.c PP_ASSERT_WITH_CODE(dep_table->count, PP_ASSERT_WITH_CODE 1068 drivers/gpu/drm/amd/powerplay/hwmgr/vega10_hwmgr.c PP_ASSERT_WITH_CODE(!vega10_trim_voltage_table(hwmgr, PP_ASSERT_WITH_CODE 1082 drivers/gpu/drm/amd/powerplay/hwmgr/vega10_hwmgr.c PP_ASSERT_WITH_CODE(dep_table->count, PP_ASSERT_WITH_CODE 1095 drivers/gpu/drm/amd/powerplay/hwmgr/vega10_hwmgr.c PP_ASSERT_WITH_CODE(!vega10_trim_voltage_table(hwmgr, vol_table), PP_ASSERT_WITH_CODE 1108 drivers/gpu/drm/amd/powerplay/hwmgr/vega10_hwmgr.c PP_ASSERT_WITH_CODE(dep_table->count, PP_ASSERT_WITH_CODE 1165 drivers/gpu/drm/amd/powerplay/hwmgr/vega10_hwmgr.c PP_ASSERT_WITH_CODE(!result, PP_ASSERT_WITH_CODE 1174 drivers/gpu/drm/amd/powerplay/hwmgr/vega10_hwmgr.c PP_ASSERT_WITH_CODE(!result, PP_ASSERT_WITH_CODE 1184 drivers/gpu/drm/amd/powerplay/hwmgr/vega10_hwmgr.c PP_ASSERT_WITH_CODE(!result, PP_ASSERT_WITH_CODE 1189 drivers/gpu/drm/amd/powerplay/hwmgr/vega10_hwmgr.c PP_ASSERT_WITH_CODE(data->vddc_voltage_table.count <= 16, PP_ASSERT_WITH_CODE 1194 drivers/gpu/drm/amd/powerplay/hwmgr/vega10_hwmgr.c PP_ASSERT_WITH_CODE(data->vddci_voltage_table.count <= 16, PP_ASSERT_WITH_CODE 1199 drivers/gpu/drm/amd/powerplay/hwmgr/vega10_hwmgr.c PP_ASSERT_WITH_CODE(data->mvdd_voltage_table.count <= 16, PP_ASSERT_WITH_CODE 1251 drivers/gpu/drm/amd/powerplay/hwmgr/vega10_hwmgr.c PP_ASSERT_WITH_CODE(bios_pcie_table->count, PP_ASSERT_WITH_CODE 1315 drivers/gpu/drm/amd/powerplay/hwmgr/vega10_hwmgr.c PP_ASSERT_WITH_CODE(dep_soc_table, PP_ASSERT_WITH_CODE 1318 drivers/gpu/drm/amd/powerplay/hwmgr/vega10_hwmgr.c PP_ASSERT_WITH_CODE(dep_soc_table->count >= 1, PP_ASSERT_WITH_CODE 1322 drivers/gpu/drm/amd/powerplay/hwmgr/vega10_hwmgr.c PP_ASSERT_WITH_CODE(dep_gfx_table, PP_ASSERT_WITH_CODE 1325 drivers/gpu/drm/amd/powerplay/hwmgr/vega10_hwmgr.c PP_ASSERT_WITH_CODE(dep_gfx_table->count >= 1, PP_ASSERT_WITH_CODE 1329 drivers/gpu/drm/amd/powerplay/hwmgr/vega10_hwmgr.c PP_ASSERT_WITH_CODE(dep_mclk_table, PP_ASSERT_WITH_CODE 1332 drivers/gpu/drm/amd/powerplay/hwmgr/vega10_hwmgr.c PP_ASSERT_WITH_CODE(dep_mclk_table->count >= 1, PP_ASSERT_WITH_CODE 1491 drivers/gpu/drm/amd/powerplay/hwmgr/vega10_hwmgr.c PP_ASSERT_WITH_CODE(!pp_atomfwctrl_get_gpu_pll_dividers_vega10( PP_ASSERT_WITH_CODE 1568 drivers/gpu/drm/amd/powerplay/hwmgr/vega10_hwmgr.c PP_ASSERT_WITH_CODE(dep_on_sclk, PP_ASSERT_WITH_CODE 1579 drivers/gpu/drm/amd/powerplay/hwmgr/vega10_hwmgr.c PP_ASSERT_WITH_CODE(dep_on_sclk->count > i, PP_ASSERT_WITH_CODE 1584 drivers/gpu/drm/amd/powerplay/hwmgr/vega10_hwmgr.c PP_ASSERT_WITH_CODE(!pp_atomfwctrl_get_gpu_pll_dividers_vega10(hwmgr, PP_ASSERT_WITH_CODE 1640 drivers/gpu/drm/amd/powerplay/hwmgr/vega10_hwmgr.c PP_ASSERT_WITH_CODE(dep_on_soc->count > i, PP_ASSERT_WITH_CODE 1644 drivers/gpu/drm/amd/powerplay/hwmgr/vega10_hwmgr.c PP_ASSERT_WITH_CODE(!pp_atomfwctrl_get_gpu_pll_dividers_vega10(hwmgr, PP_ASSERT_WITH_CODE 1769 drivers/gpu/drm/amd/powerplay/hwmgr/vega10_hwmgr.c PP_ASSERT_WITH_CODE(dep_on_mclk, PP_ASSERT_WITH_CODE 1780 drivers/gpu/drm/amd/powerplay/hwmgr/vega10_hwmgr.c PP_ASSERT_WITH_CODE(dep_on_mclk->count > i, PP_ASSERT_WITH_CODE 1785 drivers/gpu/drm/amd/powerplay/hwmgr/vega10_hwmgr.c PP_ASSERT_WITH_CODE(!pp_atomfwctrl_get_gpu_pll_dividers_vega10( PP_ASSERT_WITH_CODE 1797 drivers/gpu/drm/amd/powerplay/hwmgr/vega10_hwmgr.c PP_ASSERT_WITH_CODE(current_memclk_level->Did >= 1, PP_ASSERT_WITH_CODE 1882 drivers/gpu/drm/amd/powerplay/hwmgr/vega10_hwmgr.c PP_ASSERT_WITH_CODE(dep_table->count <= NUM_DSPCLK_LEVELS, PP_ASSERT_WITH_CODE 1913 drivers/gpu/drm/amd/powerplay/hwmgr/vega10_hwmgr.c PP_ASSERT_WITH_CODE(!vega10_populate_single_display_type(hwmgr, i), PP_ASSERT_WITH_CODE 1932 drivers/gpu/drm/amd/powerplay/hwmgr/vega10_hwmgr.c PP_ASSERT_WITH_CODE(!pp_atomfwctrl_get_gpu_pll_dividers_vega10(hwmgr, PP_ASSERT_WITH_CODE 1984 drivers/gpu/drm/amd/powerplay/hwmgr/vega10_hwmgr.c PP_ASSERT_WITH_CODE(!pp_atomfwctrl_get_gpu_pll_dividers_vega10(hwmgr, PP_ASSERT_WITH_CODE 2000 drivers/gpu/drm/amd/powerplay/hwmgr/vega10_hwmgr.c PP_ASSERT_WITH_CODE(!pp_atomfwctrl_get_gpu_pll_dividers_vega10(hwmgr, PP_ASSERT_WITH_CODE 2382 drivers/gpu/drm/amd/powerplay/hwmgr/vega10_hwmgr.c PP_ASSERT_WITH_CODE(!vega10_enable_smc_features(hwmgr, PP_ASSERT_WITH_CODE 2389 drivers/gpu/drm/amd/powerplay/hwmgr/vega10_hwmgr.c PP_ASSERT_WITH_CODE(!vega10_enable_smc_features(hwmgr, PP_ASSERT_WITH_CODE 2448 drivers/gpu/drm/amd/powerplay/hwmgr/vega10_hwmgr.c PP_ASSERT_WITH_CODE(!result, PP_ASSERT_WITH_CODE 2504 drivers/gpu/drm/amd/powerplay/hwmgr/vega10_hwmgr.c PP_ASSERT_WITH_CODE(!result, PP_ASSERT_WITH_CODE 2544 drivers/gpu/drm/amd/powerplay/hwmgr/vega10_hwmgr.c PP_ASSERT_WITH_CODE(!result, PP_ASSERT_WITH_CODE 2550 drivers/gpu/drm/amd/powerplay/hwmgr/vega10_hwmgr.c PP_ASSERT_WITH_CODE(!result, PP_ASSERT_WITH_CODE 2555 drivers/gpu/drm/amd/powerplay/hwmgr/vega10_hwmgr.c PP_ASSERT_WITH_CODE(!result, PP_ASSERT_WITH_CODE 2560 drivers/gpu/drm/amd/powerplay/hwmgr/vega10_hwmgr.c PP_ASSERT_WITH_CODE(!result, PP_ASSERT_WITH_CODE 2567 drivers/gpu/drm/amd/powerplay/hwmgr/vega10_hwmgr.c PP_ASSERT_WITH_CODE(!result, PP_ASSERT_WITH_CODE 2572 drivers/gpu/drm/amd/powerplay/hwmgr/vega10_hwmgr.c PP_ASSERT_WITH_CODE(!result, PP_ASSERT_WITH_CODE 2577 drivers/gpu/drm/amd/powerplay/hwmgr/vega10_hwmgr.c PP_ASSERT_WITH_CODE(!result, PP_ASSERT_WITH_CODE 2583 drivers/gpu/drm/amd/powerplay/hwmgr/vega10_hwmgr.c PP_ASSERT_WITH_CODE(!result, PP_ASSERT_WITH_CODE 2617 drivers/gpu/drm/amd/powerplay/hwmgr/vega10_hwmgr.c PP_ASSERT_WITH_CODE(!result, PP_ASSERT_WITH_CODE 2622 drivers/gpu/drm/amd/powerplay/hwmgr/vega10_hwmgr.c PP_ASSERT_WITH_CODE(!result, PP_ASSERT_WITH_CODE 2639 drivers/gpu/drm/amd/powerplay/hwmgr/vega10_hwmgr.c PP_ASSERT_WITH_CODE(!result, PP_ASSERT_WITH_CODE 2643 drivers/gpu/drm/amd/powerplay/hwmgr/vega10_hwmgr.c PP_ASSERT_WITH_CODE(!result, "Attempt to enable AVFS feature Failed!", PP_ASSERT_WITH_CODE 2658 drivers/gpu/drm/amd/powerplay/hwmgr/vega10_hwmgr.c PP_ASSERT_WITH_CODE( PP_ASSERT_WITH_CODE 2678 drivers/gpu/drm/amd/powerplay/hwmgr/vega10_hwmgr.c PP_ASSERT_WITH_CODE( PP_ASSERT_WITH_CODE 2696 drivers/gpu/drm/amd/powerplay/hwmgr/vega10_hwmgr.c PP_ASSERT_WITH_CODE( PP_ASSERT_WITH_CODE 2705 drivers/gpu/drm/amd/powerplay/hwmgr/vega10_hwmgr.c PP_ASSERT_WITH_CODE( PP_ASSERT_WITH_CODE 2723 drivers/gpu/drm/amd/powerplay/hwmgr/vega10_hwmgr.c PP_ASSERT_WITH_CODE(!vega10_enable_smc_features(hwmgr, PP_ASSERT_WITH_CODE 2738 drivers/gpu/drm/amd/powerplay/hwmgr/vega10_hwmgr.c PP_ASSERT_WITH_CODE(!vega10_enable_smc_features(hwmgr, PP_ASSERT_WITH_CODE 2753 drivers/gpu/drm/amd/powerplay/hwmgr/vega10_hwmgr.c PP_ASSERT_WITH_CODE(!vega10_enable_smc_features(hwmgr, PP_ASSERT_WITH_CODE 2761 drivers/gpu/drm/amd/powerplay/hwmgr/vega10_hwmgr.c PP_ASSERT_WITH_CODE(!vega10_enable_smc_features(hwmgr, PP_ASSERT_WITH_CODE 2769 drivers/gpu/drm/amd/powerplay/hwmgr/vega10_hwmgr.c PP_ASSERT_WITH_CODE(!vega10_enable_smc_features(hwmgr, PP_ASSERT_WITH_CODE 2777 drivers/gpu/drm/amd/powerplay/hwmgr/vega10_hwmgr.c PP_ASSERT_WITH_CODE(!vega10_enable_smc_features(hwmgr, PP_ASSERT_WITH_CODE 2792 drivers/gpu/drm/amd/powerplay/hwmgr/vega10_hwmgr.c PP_ASSERT_WITH_CODE(!vega10_enable_smc_features(hwmgr, PP_ASSERT_WITH_CODE 2800 drivers/gpu/drm/amd/powerplay/hwmgr/vega10_hwmgr.c PP_ASSERT_WITH_CODE(!vega10_enable_smc_features(hwmgr, PP_ASSERT_WITH_CODE 2808 drivers/gpu/drm/amd/powerplay/hwmgr/vega10_hwmgr.c PP_ASSERT_WITH_CODE(!vega10_enable_smc_features(hwmgr, PP_ASSERT_WITH_CODE 2816 drivers/gpu/drm/amd/powerplay/hwmgr/vega10_hwmgr.c PP_ASSERT_WITH_CODE(!vega10_enable_smc_features(hwmgr, PP_ASSERT_WITH_CODE 2833 drivers/gpu/drm/amd/powerplay/hwmgr/vega10_hwmgr.c PP_ASSERT_WITH_CODE(!vega10_enable_smc_features(hwmgr, PP_ASSERT_WITH_CODE 2890 drivers/gpu/drm/amd/powerplay/hwmgr/vega10_hwmgr.c PP_ASSERT_WITH_CODE(!vega10_enable_smc_features(hwmgr, PP_ASSERT_WITH_CODE 2904 drivers/gpu/drm/amd/powerplay/hwmgr/vega10_hwmgr.c PP_ASSERT_WITH_CODE(!vega10_enable_smc_features(hwmgr, PP_ASSERT_WITH_CODE 2922 drivers/gpu/drm/amd/powerplay/hwmgr/vega10_hwmgr.c PP_ASSERT_WITH_CODE(!vega10_enable_smc_features(hwmgr, PP_ASSERT_WITH_CODE 2943 drivers/gpu/drm/amd/powerplay/hwmgr/vega10_hwmgr.c PP_ASSERT_WITH_CODE(!tmp_result, PP_ASSERT_WITH_CODE 2948 drivers/gpu/drm/amd/powerplay/hwmgr/vega10_hwmgr.c PP_ASSERT_WITH_CODE(!tmp_result, PP_ASSERT_WITH_CODE 2954 drivers/gpu/drm/amd/powerplay/hwmgr/vega10_hwmgr.c PP_ASSERT_WITH_CODE(!tmp_result, PP_ASSERT_WITH_CODE 2960 drivers/gpu/drm/amd/powerplay/hwmgr/vega10_hwmgr.c PP_ASSERT_WITH_CODE(!tmp_result, PP_ASSERT_WITH_CODE 2965 drivers/gpu/drm/amd/powerplay/hwmgr/vega10_hwmgr.c PP_ASSERT_WITH_CODE(!tmp_result, PP_ASSERT_WITH_CODE 2970 drivers/gpu/drm/amd/powerplay/hwmgr/vega10_hwmgr.c PP_ASSERT_WITH_CODE(!tmp_result, PP_ASSERT_WITH_CODE 2979 drivers/gpu/drm/amd/powerplay/hwmgr/vega10_hwmgr.c PP_ASSERT_WITH_CODE(!tmp_result, PP_ASSERT_WITH_CODE 2984 drivers/gpu/drm/amd/powerplay/hwmgr/vega10_hwmgr.c PP_ASSERT_WITH_CODE(!tmp_result, PP_ASSERT_WITH_CODE 2989 drivers/gpu/drm/amd/powerplay/hwmgr/vega10_hwmgr.c PP_ASSERT_WITH_CODE(!tmp_result, PP_ASSERT_WITH_CODE 3059 drivers/gpu/drm/amd/powerplay/hwmgr/vega10_hwmgr.c PP_ASSERT_WITH_CODE( PP_ASSERT_WITH_CODE 3065 drivers/gpu/drm/amd/powerplay/hwmgr/vega10_hwmgr.c PP_ASSERT_WITH_CODE( PP_ASSERT_WITH_CODE 3185 drivers/gpu/drm/amd/powerplay/hwmgr/vega10_hwmgr.c PP_ASSERT_WITH_CODE( PP_ASSERT_WITH_CODE 3355 drivers/gpu/drm/amd/powerplay/hwmgr/vega10_hwmgr.c PP_ASSERT_WITH_CODE((0 == result), PP_ASSERT_WITH_CODE 3363 drivers/gpu/drm/amd/powerplay/hwmgr/vega10_hwmgr.c PP_ASSERT_WITH_CODE((0 == result), PP_ASSERT_WITH_CODE 3414 drivers/gpu/drm/amd/powerplay/hwmgr/vega10_hwmgr.c PP_ASSERT_WITH_CODE((vega10_ps->performance_level_count >= 1), PP_ASSERT_WITH_CODE 3589 drivers/gpu/drm/amd/powerplay/hwmgr/vega10_hwmgr.c PP_ASSERT_WITH_CODE(!vega10_trim_dpm_states(hwmgr, vega10_ps), PP_ASSERT_WITH_CODE 3606 drivers/gpu/drm/amd/powerplay/hwmgr/vega10_hwmgr.c PP_ASSERT_WITH_CODE(!vega10_upload_dpm_bootup_level(hwmgr), PP_ASSERT_WITH_CODE 3609 drivers/gpu/drm/amd/powerplay/hwmgr/vega10_hwmgr.c PP_ASSERT_WITH_CODE(!vega10_upload_dpm_max_level(hwmgr), PP_ASSERT_WITH_CODE 3630 drivers/gpu/drm/amd/powerplay/hwmgr/vega10_hwmgr.c PP_ASSERT_WITH_CODE(!vega10_enable_smc_features(hwmgr, PP_ASSERT_WITH_CODE 3671 drivers/gpu/drm/amd/powerplay/hwmgr/vega10_hwmgr.c PP_ASSERT_WITH_CODE(!tmp_result, PP_ASSERT_WITH_CODE 3676 drivers/gpu/drm/amd/powerplay/hwmgr/vega10_hwmgr.c PP_ASSERT_WITH_CODE(!tmp_result, PP_ASSERT_WITH_CODE 3681 drivers/gpu/drm/amd/powerplay/hwmgr/vega10_hwmgr.c PP_ASSERT_WITH_CODE(!tmp_result, PP_ASSERT_WITH_CODE 3686 drivers/gpu/drm/amd/powerplay/hwmgr/vega10_hwmgr.c PP_ASSERT_WITH_CODE(!tmp_result, PP_ASSERT_WITH_CODE 3691 drivers/gpu/drm/amd/powerplay/hwmgr/vega10_hwmgr.c PP_ASSERT_WITH_CODE(!result, PP_ASSERT_WITH_CODE 3974 drivers/gpu/drm/amd/powerplay/hwmgr/vega10_hwmgr.c PP_ASSERT_WITH_CODE(!vega10_upload_dpm_bootup_level(hwmgr), PP_ASSERT_WITH_CODE 3978 drivers/gpu/drm/amd/powerplay/hwmgr/vega10_hwmgr.c PP_ASSERT_WITH_CODE(!vega10_upload_dpm_max_level(hwmgr), PP_ASSERT_WITH_CODE 3996 drivers/gpu/drm/amd/powerplay/hwmgr/vega10_hwmgr.c PP_ASSERT_WITH_CODE(!vega10_upload_dpm_bootup_level(hwmgr), PP_ASSERT_WITH_CODE 4000 drivers/gpu/drm/amd/powerplay/hwmgr/vega10_hwmgr.c PP_ASSERT_WITH_CODE(!vega10_upload_dpm_max_level(hwmgr), PP_ASSERT_WITH_CODE 4021 drivers/gpu/drm/amd/powerplay/hwmgr/vega10_hwmgr.c PP_ASSERT_WITH_CODE(!vega10_upload_dpm_bootup_level(hwmgr), PP_ASSERT_WITH_CODE 4025 drivers/gpu/drm/amd/powerplay/hwmgr/vega10_hwmgr.c PP_ASSERT_WITH_CODE(!vega10_upload_dpm_max_level(hwmgr), PP_ASSERT_WITH_CODE 4088 drivers/gpu/drm/amd/powerplay/hwmgr/vega10_hwmgr.c PP_ASSERT_WITH_CODE(!vega10_upload_dpm_bootup_level(hwmgr), PP_ASSERT_WITH_CODE 4092 drivers/gpu/drm/amd/powerplay/hwmgr/vega10_hwmgr.c PP_ASSERT_WITH_CODE(!vega10_upload_dpm_max_level(hwmgr), PP_ASSERT_WITH_CODE 4101 drivers/gpu/drm/amd/powerplay/hwmgr/vega10_hwmgr.c PP_ASSERT_WITH_CODE(!vega10_upload_dpm_bootup_level(hwmgr), PP_ASSERT_WITH_CODE 4105 drivers/gpu/drm/amd/powerplay/hwmgr/vega10_hwmgr.c PP_ASSERT_WITH_CODE(!vega10_upload_dpm_max_level(hwmgr), PP_ASSERT_WITH_CODE 4115 drivers/gpu/drm/amd/powerplay/hwmgr/vega10_hwmgr.c PP_ASSERT_WITH_CODE(!vega10_upload_dpm_bootup_level(hwmgr), PP_ASSERT_WITH_CODE 4119 drivers/gpu/drm/amd/powerplay/hwmgr/vega10_hwmgr.c PP_ASSERT_WITH_CODE(!vega10_upload_dpm_max_level(hwmgr), PP_ASSERT_WITH_CODE 4411 drivers/gpu/drm/amd/powerplay/hwmgr/vega10_hwmgr.c PP_ASSERT_WITH_CODE(!ret, PP_ASSERT_WITH_CODE 4591 drivers/gpu/drm/amd/powerplay/hwmgr/vega10_hwmgr.c PP_ASSERT_WITH_CODE(result, "Failed to update WMTABLE!", return EINVAL); PP_ASSERT_WITH_CODE 4608 drivers/gpu/drm/amd/powerplay/hwmgr/vega10_hwmgr.c PP_ASSERT_WITH_CODE(!vega10_enable_smc_features(hwmgr, PP_ASSERT_WITH_CODE 4703 drivers/gpu/drm/amd/powerplay/hwmgr/vega10_hwmgr.c PP_ASSERT_WITH_CODE((tmp_result == 0), PP_ASSERT_WITH_CODE 4707 drivers/gpu/drm/amd/powerplay/hwmgr/vega10_hwmgr.c PP_ASSERT_WITH_CODE((tmp_result == 0), PP_ASSERT_WITH_CODE 4711 drivers/gpu/drm/amd/powerplay/hwmgr/vega10_hwmgr.c PP_ASSERT_WITH_CODE((tmp_result == 0), PP_ASSERT_WITH_CODE 4715 drivers/gpu/drm/amd/powerplay/hwmgr/vega10_hwmgr.c PP_ASSERT_WITH_CODE((tmp_result == 0), PP_ASSERT_WITH_CODE 4719 drivers/gpu/drm/amd/powerplay/hwmgr/vega10_hwmgr.c PP_ASSERT_WITH_CODE((tmp_result == 0), PP_ASSERT_WITH_CODE 4723 drivers/gpu/drm/amd/powerplay/hwmgr/vega10_hwmgr.c PP_ASSERT_WITH_CODE((tmp_result == 0), PP_ASSERT_WITH_CODE 4727 drivers/gpu/drm/amd/powerplay/hwmgr/vega10_hwmgr.c PP_ASSERT_WITH_CODE((tmp_result == 0), PP_ASSERT_WITH_CODE 4740 drivers/gpu/drm/amd/powerplay/hwmgr/vega10_hwmgr.c PP_ASSERT_WITH_CODE((0 == result), PP_ASSERT_WITH_CODE 5168 drivers/gpu/drm/amd/powerplay/hwmgr/vega10_hwmgr.c PP_ASSERT_WITH_CODE(input, "NULL user input for clock and voltage", PP_ASSERT_WITH_CODE 5238 drivers/gpu/drm/amd/powerplay/hwmgr/vega10_hwmgr.c PP_ASSERT_WITH_CODE((ret = smum_send_msg_to_smc(hwmgr, msg)) == 0, PP_ASSERT_WITH_CODE 803 drivers/gpu/drm/amd/powerplay/hwmgr/vega10_powertune.c PP_ASSERT_WITH_CODE((config_regs != NULL), "[vega10_program_didt_config_registers] Invalid config register table!", return -EINVAL); PP_ASSERT_WITH_CODE 1186 drivers/gpu/drm/amd/powerplay/hwmgr/vega10_powertune.c PP_ASSERT_WITH_CODE((0 == result), "[DisableDiDtConfig] Pre DIDT disable clock gating failed!", return result); PP_ASSERT_WITH_CODE 1203 drivers/gpu/drm/amd/powerplay/hwmgr/vega10_powertune.c PP_ASSERT_WITH_CODE((0 == result), "[EnableDiDt] Attempt to enable DiDt Mode 0 Failed!", return result); PP_ASSERT_WITH_CODE 1207 drivers/gpu/drm/amd/powerplay/hwmgr/vega10_powertune.c PP_ASSERT_WITH_CODE((0 == result), "[EnableDiDt] Attempt to enable DiDt Mode 2 Failed!", return result); PP_ASSERT_WITH_CODE 1211 drivers/gpu/drm/amd/powerplay/hwmgr/vega10_powertune.c PP_ASSERT_WITH_CODE((0 == result), "[EnableDiDt] Attempt to enable DiDt Mode 3 Failed!", return result); PP_ASSERT_WITH_CODE 1217 drivers/gpu/drm/amd/powerplay/hwmgr/vega10_powertune.c PP_ASSERT_WITH_CODE((0 == result), "[EnableDiDt] Attempt to enable DiDt Mode 5 Failed!", return result); PP_ASSERT_WITH_CODE 1221 drivers/gpu/drm/amd/powerplay/hwmgr/vega10_powertune.c PP_ASSERT_WITH_CODE((0 == result), "[EnableDiDt] Attempt to enable DiDt Mode 6 Failed!", return result); PP_ASSERT_WITH_CODE 1230 drivers/gpu/drm/amd/powerplay/hwmgr/vega10_powertune.c PP_ASSERT_WITH_CODE((0 == result), "[EnableDiDtConfig] Attempt to Enable DiDt feature Failed!", return result); PP_ASSERT_WITH_CODE 1250 drivers/gpu/drm/amd/powerplay/hwmgr/vega10_powertune.c PP_ASSERT_WITH_CODE((0 == result), "[DisableDiDt] Attempt to disable DiDt Mode 0 Failed!", return result); PP_ASSERT_WITH_CODE 1254 drivers/gpu/drm/amd/powerplay/hwmgr/vega10_powertune.c PP_ASSERT_WITH_CODE((0 == result), "[DisableDiDt] Attempt to disable DiDt Mode 2 Failed!", return result); PP_ASSERT_WITH_CODE 1258 drivers/gpu/drm/amd/powerplay/hwmgr/vega10_powertune.c PP_ASSERT_WITH_CODE((0 == result), "[DisableDiDt] Attempt to disable DiDt Mode 3 Failed!", return result); PP_ASSERT_WITH_CODE 1264 drivers/gpu/drm/amd/powerplay/hwmgr/vega10_powertune.c PP_ASSERT_WITH_CODE((0 == result), "[DisableDiDt] Attempt to disable DiDt Mode 5 Failed!", return result); PP_ASSERT_WITH_CODE 1268 drivers/gpu/drm/amd/powerplay/hwmgr/vega10_powertune.c PP_ASSERT_WITH_CODE((0 == result), "[DisableDiDt] Attempt to disable DiDt Mode 6 Failed!", return result); PP_ASSERT_WITH_CODE 1277 drivers/gpu/drm/amd/powerplay/hwmgr/vega10_powertune.c PP_ASSERT_WITH_CODE((0 == result), "[DisableDiDtConfig] Attempt to Disable DiDt feature Failed!", return result); PP_ASSERT_WITH_CODE 1348 drivers/gpu/drm/amd/powerplay/hwmgr/vega10_powertune.c PP_ASSERT_WITH_CODE(!vega10_enable_smc_features(hwmgr, PP_ASSERT_WITH_CODE 1354 drivers/gpu/drm/amd/powerplay/hwmgr/vega10_powertune.c PP_ASSERT_WITH_CODE(!vega10_enable_smc_features(hwmgr, PP_ASSERT_WITH_CODE 1360 drivers/gpu/drm/amd/powerplay/hwmgr/vega10_powertune.c PP_ASSERT_WITH_CODE(!result, PP_ASSERT_WITH_CODE 1374 drivers/gpu/drm/amd/powerplay/hwmgr/vega10_powertune.c PP_ASSERT_WITH_CODE(!vega10_enable_smc_features(hwmgr, PP_ASSERT_WITH_CODE 1380 drivers/gpu/drm/amd/powerplay/hwmgr/vega10_powertune.c PP_ASSERT_WITH_CODE(!vega10_enable_smc_features(hwmgr, PP_ASSERT_WITH_CODE 76 drivers/gpu/drm/amd/powerplay/hwmgr/vega10_processpptables.c PP_ASSERT_WITH_CODE((powerplay_table->sHeader.format_revision >= PP_ASSERT_WITH_CODE 79 drivers/gpu/drm/amd/powerplay/hwmgr/vega10_processpptables.c PP_ASSERT_WITH_CODE(powerplay_table->usStateArrayOffset, PP_ASSERT_WITH_CODE 81 drivers/gpu/drm/amd/powerplay/hwmgr/vega10_processpptables.c PP_ASSERT_WITH_CODE(powerplay_table->sHeader.structuresize > 0, PP_ASSERT_WITH_CODE 83 drivers/gpu/drm/amd/powerplay/hwmgr/vega10_processpptables.c PP_ASSERT_WITH_CODE(state_arrays->ucNumEntries > 0, PP_ASSERT_WITH_CODE 133 drivers/gpu/drm/amd/powerplay/hwmgr/vega10_processpptables.c PP_ASSERT_WITH_CODE((powerplay_table->usThermalControllerOffset != 0), PP_ASSERT_WITH_CODE 171 drivers/gpu/drm/amd/powerplay/hwmgr/vega10_processpptables.c PP_ASSERT_WITH_CODE((fan_table_v1->ucRevId >= 8), PP_ASSERT_WITH_CODE 351 drivers/gpu/drm/amd/powerplay/hwmgr/vega10_processpptables.c PP_ASSERT_WITH_CODE((mm_dependency_table->ucNumEntries != 0), PP_ASSERT_WITH_CODE 577 drivers/gpu/drm/amd/powerplay/hwmgr/vega10_processpptables.c PP_ASSERT_WITH_CODE(clk_dep_table->ucNumEntries, PP_ASSERT_WITH_CODE 611 drivers/gpu/drm/amd/powerplay/hwmgr/vega10_processpptables.c PP_ASSERT_WITH_CODE(mclk_dep_table->ucNumEntries, PP_ASSERT_WITH_CODE 652 drivers/gpu/drm/amd/powerplay/hwmgr/vega10_processpptables.c PP_ASSERT_WITH_CODE((clk_dep_table->ucNumEntries != 0), PP_ASSERT_WITH_CODE 698 drivers/gpu/drm/amd/powerplay/hwmgr/vega10_processpptables.c PP_ASSERT_WITH_CODE(false, PP_ASSERT_WITH_CODE 718 drivers/gpu/drm/amd/powerplay/hwmgr/vega10_processpptables.c PP_ASSERT_WITH_CODE((clk_dep_table->ucNumEntries != 0), PP_ASSERT_WITH_CODE 758 drivers/gpu/drm/amd/powerplay/hwmgr/vega10_processpptables.c PP_ASSERT_WITH_CODE((clk_dep_table->ucNumEntries != 0), PP_ASSERT_WITH_CODE 817 drivers/gpu/drm/amd/powerplay/hwmgr/vega10_processpptables.c PP_ASSERT_WITH_CODE(atom_pcie_table->ucNumEntries, PP_ASSERT_WITH_CODE 859 drivers/gpu/drm/amd/powerplay/hwmgr/vega10_processpptables.c PP_ASSERT_WITH_CODE(limit_table->ucNumEntries, PP_ASSERT_WITH_CODE 881 drivers/gpu/drm/amd/powerplay/hwmgr/vega10_processpptables.c PP_ASSERT_WITH_CODE(clk_volt_pp_table->count, PP_ASSERT_WITH_CODE 1072 drivers/gpu/drm/amd/powerplay/hwmgr/vega10_processpptables.c PP_ASSERT_WITH_CODE((vddc_lookup_pp_tables->ucNumEntries != 0), PP_ASSERT_WITH_CODE 1189 drivers/gpu/drm/amd/powerplay/hwmgr/vega10_processpptables.c PP_ASSERT_WITH_CODE((hwmgr->pptable != NULL), PP_ASSERT_WITH_CODE 1194 drivers/gpu/drm/amd/powerplay/hwmgr/vega10_processpptables.c PP_ASSERT_WITH_CODE((powerplay_table != NULL), PP_ASSERT_WITH_CODE 1199 drivers/gpu/drm/amd/powerplay/hwmgr/vega10_processpptables.c PP_ASSERT_WITH_CODE((result == 0), PP_ASSERT_WITH_CODE 1205 drivers/gpu/drm/amd/powerplay/hwmgr/vega10_processpptables.c PP_ASSERT_WITH_CODE((result == 0), PP_ASSERT_WITH_CODE 1210 drivers/gpu/drm/amd/powerplay/hwmgr/vega10_processpptables.c PP_ASSERT_WITH_CODE((result == 0), PP_ASSERT_WITH_CODE 1215 drivers/gpu/drm/amd/powerplay/hwmgr/vega10_processpptables.c PP_ASSERT_WITH_CODE((result == 0), PP_ASSERT_WITH_CODE 1220 drivers/gpu/drm/amd/powerplay/hwmgr/vega10_processpptables.c PP_ASSERT_WITH_CODE((result == 0), PP_ASSERT_WITH_CODE 1225 drivers/gpu/drm/amd/powerplay/hwmgr/vega10_processpptables.c PP_ASSERT_WITH_CODE((result == 0), PP_ASSERT_WITH_CODE 1288 drivers/gpu/drm/amd/powerplay/hwmgr/vega10_processpptables.c PP_ASSERT_WITH_CODE((pp_table != NULL), PP_ASSERT_WITH_CODE 1290 drivers/gpu/drm/amd/powerplay/hwmgr/vega10_processpptables.c PP_ASSERT_WITH_CODE((pp_table->sHeader.format_revision >= PP_ASSERT_WITH_CODE 1340 drivers/gpu/drm/amd/powerplay/hwmgr/vega10_processpptables.c PP_ASSERT_WITH_CODE(pp_table, "Missing PowerPlay Table!", PP_ASSERT_WITH_CODE 1350 drivers/gpu/drm/amd/powerplay/hwmgr/vega10_processpptables.c PP_ASSERT_WITH_CODE(pp_table->usStateArrayOffset > 0, PP_ASSERT_WITH_CODE 1353 drivers/gpu/drm/amd/powerplay/hwmgr/vega10_processpptables.c PP_ASSERT_WITH_CODE(state_arrays->ucNumEntries > 0, PP_ASSERT_WITH_CODE 1356 drivers/gpu/drm/amd/powerplay/hwmgr/vega10_processpptables.c PP_ASSERT_WITH_CODE((entry_index <= state_arrays->ucNumEntries), PP_ASSERT_WITH_CODE 1384 drivers/gpu/drm/amd/powerplay/hwmgr/vega10_processpptables.c PP_ASSERT_WITH_CODE((powerplay_table != NULL), PP_ASSERT_WITH_CODE 1389 drivers/gpu/drm/amd/powerplay/hwmgr/vega10_processpptables.c PP_ASSERT_WITH_CODE((result == 0), PP_ASSERT_WITH_CODE 188 drivers/gpu/drm/amd/powerplay/hwmgr/vega10_thermal.c PP_ASSERT_WITH_CODE(!vega10_enable_smc_features( PP_ASSERT_WITH_CODE 205 drivers/gpu/drm/amd/powerplay/hwmgr/vega10_thermal.c PP_ASSERT_WITH_CODE(!vega10_enable_smc_features( PP_ASSERT_WITH_CODE 222 drivers/gpu/drm/amd/powerplay/hwmgr/vega10_thermal.c PP_ASSERT_WITH_CODE(!vega10_enable_fan_control_feature(hwmgr), PP_ASSERT_WITH_CODE 238 drivers/gpu/drm/amd/powerplay/hwmgr/vega10_thermal.c PP_ASSERT_WITH_CODE(!vega10_disable_fan_control_feature(hwmgr), PP_ASSERT_WITH_CODE 435 drivers/gpu/drm/amd/powerplay/hwmgr/vega10_thermal.c PP_ASSERT_WITH_CODE(!vega10_enable_smc_features(hwmgr, PP_ASSERT_WITH_CODE 466 drivers/gpu/drm/amd/powerplay/hwmgr/vega10_thermal.c PP_ASSERT_WITH_CODE(!vega10_enable_smc_features(hwmgr, PP_ASSERT_WITH_CODE 457 drivers/gpu/drm/amd/powerplay/hwmgr/vega12_hwmgr.c PP_ASSERT_WITH_CODE(!vega12_init_sclk_threshold(hwmgr), PP_ASSERT_WITH_CODE 487 drivers/gpu/drm/amd/powerplay/hwmgr/vega12_hwmgr.c PP_ASSERT_WITH_CODE(!ret, PP_ASSERT_WITH_CODE 492 drivers/gpu/drm/amd/powerplay/hwmgr/vega12_hwmgr.c PP_ASSERT_WITH_CODE(*num_of_levels > 0, PP_ASSERT_WITH_CODE 508 drivers/gpu/drm/amd/powerplay/hwmgr/vega12_hwmgr.c PP_ASSERT_WITH_CODE(smum_send_msg_to_smc_with_parameter(hwmgr, PP_ASSERT_WITH_CODE 525 drivers/gpu/drm/amd/powerplay/hwmgr/vega12_hwmgr.c PP_ASSERT_WITH_CODE(!ret, PP_ASSERT_WITH_CODE 533 drivers/gpu/drm/amd/powerplay/hwmgr/vega12_hwmgr.c PP_ASSERT_WITH_CODE(!ret, PP_ASSERT_WITH_CODE 565 drivers/gpu/drm/amd/powerplay/hwmgr/vega12_hwmgr.c PP_ASSERT_WITH_CODE(!ret, PP_ASSERT_WITH_CODE 578 drivers/gpu/drm/amd/powerplay/hwmgr/vega12_hwmgr.c PP_ASSERT_WITH_CODE(!ret, PP_ASSERT_WITH_CODE 591 drivers/gpu/drm/amd/powerplay/hwmgr/vega12_hwmgr.c PP_ASSERT_WITH_CODE(!ret, PP_ASSERT_WITH_CODE 604 drivers/gpu/drm/amd/powerplay/hwmgr/vega12_hwmgr.c PP_ASSERT_WITH_CODE(!ret, PP_ASSERT_WITH_CODE 617 drivers/gpu/drm/amd/powerplay/hwmgr/vega12_hwmgr.c PP_ASSERT_WITH_CODE(!ret, PP_ASSERT_WITH_CODE 630 drivers/gpu/drm/amd/powerplay/hwmgr/vega12_hwmgr.c PP_ASSERT_WITH_CODE(!ret, PP_ASSERT_WITH_CODE 643 drivers/gpu/drm/amd/powerplay/hwmgr/vega12_hwmgr.c PP_ASSERT_WITH_CODE(!ret, PP_ASSERT_WITH_CODE 656 drivers/gpu/drm/amd/powerplay/hwmgr/vega12_hwmgr.c PP_ASSERT_WITH_CODE(!ret, PP_ASSERT_WITH_CODE 667 drivers/gpu/drm/amd/powerplay/hwmgr/vega12_hwmgr.c PP_ASSERT_WITH_CODE(!ret, PP_ASSERT_WITH_CODE 678 drivers/gpu/drm/amd/powerplay/hwmgr/vega12_hwmgr.c PP_ASSERT_WITH_CODE(!ret, PP_ASSERT_WITH_CODE 761 drivers/gpu/drm/amd/powerplay/hwmgr/vega12_hwmgr.c PP_ASSERT_WITH_CODE(!result, PP_ASSERT_WITH_CODE 771 drivers/gpu/drm/amd/powerplay/hwmgr/vega12_hwmgr.c PP_ASSERT_WITH_CODE( PP_ASSERT_WITH_CODE 777 drivers/gpu/drm/amd/powerplay/hwmgr/vega12_hwmgr.c PP_ASSERT_WITH_CODE(result == 1, PP_ASSERT_WITH_CODE 796 drivers/gpu/drm/amd/powerplay/hwmgr/vega12_hwmgr.c PP_ASSERT_WITH_CODE( PP_ASSERT_WITH_CODE 801 drivers/gpu/drm/amd/powerplay/hwmgr/vega12_hwmgr.c PP_ASSERT_WITH_CODE( PP_ASSERT_WITH_CODE 832 drivers/gpu/drm/amd/powerplay/hwmgr/vega12_hwmgr.c PP_ASSERT_WITH_CODE( PP_ASSERT_WITH_CODE 858 drivers/gpu/drm/amd/powerplay/hwmgr/vega12_hwmgr.c PP_ASSERT_WITH_CODE( PP_ASSERT_WITH_CODE 906 drivers/gpu/drm/amd/powerplay/hwmgr/vega12_hwmgr.c PP_ASSERT_WITH_CODE( PP_ASSERT_WITH_CODE 913 drivers/gpu/drm/amd/powerplay/hwmgr/vega12_hwmgr.c PP_ASSERT_WITH_CODE( PP_ASSERT_WITH_CODE 920 drivers/gpu/drm/amd/powerplay/hwmgr/vega12_hwmgr.c PP_ASSERT_WITH_CODE( PP_ASSERT_WITH_CODE 936 drivers/gpu/drm/amd/powerplay/hwmgr/vega12_hwmgr.c PP_ASSERT_WITH_CODE(!vega12_get_all_clock_ranges_helper(hwmgr, PP_ASSERT_WITH_CODE 952 drivers/gpu/drm/amd/powerplay/hwmgr/vega12_hwmgr.c PP_ASSERT_WITH_CODE(result == 0, PP_ASSERT_WITH_CODE 957 drivers/gpu/drm/amd/powerplay/hwmgr/vega12_hwmgr.c PP_ASSERT_WITH_CODE(!tmp_result, PP_ASSERT_WITH_CODE 962 drivers/gpu/drm/amd/powerplay/hwmgr/vega12_hwmgr.c PP_ASSERT_WITH_CODE(!tmp_result, PP_ASSERT_WITH_CODE 967 drivers/gpu/drm/amd/powerplay/hwmgr/vega12_hwmgr.c PP_ASSERT_WITH_CODE(!result, PP_ASSERT_WITH_CODE 972 drivers/gpu/drm/amd/powerplay/hwmgr/vega12_hwmgr.c PP_ASSERT_WITH_CODE(!tmp_result, PP_ASSERT_WITH_CODE 977 drivers/gpu/drm/amd/powerplay/hwmgr/vega12_hwmgr.c PP_ASSERT_WITH_CODE(!result, PP_ASSERT_WITH_CODE 982 drivers/gpu/drm/amd/powerplay/hwmgr/vega12_hwmgr.c PP_ASSERT_WITH_CODE(!result, PP_ASSERT_WITH_CODE 987 drivers/gpu/drm/amd/powerplay/hwmgr/vega12_hwmgr.c PP_ASSERT_WITH_CODE(!result, PP_ASSERT_WITH_CODE 1021 drivers/gpu/drm/amd/powerplay/hwmgr/vega12_hwmgr.c PP_ASSERT_WITH_CODE(table->count <= MAX_REGULAR_DPM_NUMBER, PP_ASSERT_WITH_CODE 1046 drivers/gpu/drm/amd/powerplay/hwmgr/vega12_hwmgr.c PP_ASSERT_WITH_CODE(!(ret = smum_send_msg_to_smc_with_parameter( PP_ASSERT_WITH_CODE 1055 drivers/gpu/drm/amd/powerplay/hwmgr/vega12_hwmgr.c PP_ASSERT_WITH_CODE(!(ret = smum_send_msg_to_smc_with_parameter( PP_ASSERT_WITH_CODE 1062 drivers/gpu/drm/amd/powerplay/hwmgr/vega12_hwmgr.c PP_ASSERT_WITH_CODE(!(ret = smum_send_msg_to_smc_with_parameter( PP_ASSERT_WITH_CODE 1072 drivers/gpu/drm/amd/powerplay/hwmgr/vega12_hwmgr.c PP_ASSERT_WITH_CODE(!(ret = smum_send_msg_to_smc_with_parameter( PP_ASSERT_WITH_CODE 1080 drivers/gpu/drm/amd/powerplay/hwmgr/vega12_hwmgr.c PP_ASSERT_WITH_CODE(!(ret = smum_send_msg_to_smc_with_parameter( PP_ASSERT_WITH_CODE 1090 drivers/gpu/drm/amd/powerplay/hwmgr/vega12_hwmgr.c PP_ASSERT_WITH_CODE(!(ret = smum_send_msg_to_smc_with_parameter( PP_ASSERT_WITH_CODE 1100 drivers/gpu/drm/amd/powerplay/hwmgr/vega12_hwmgr.c PP_ASSERT_WITH_CODE(!(ret = smum_send_msg_to_smc_with_parameter( PP_ASSERT_WITH_CODE 1110 drivers/gpu/drm/amd/powerplay/hwmgr/vega12_hwmgr.c PP_ASSERT_WITH_CODE(!(ret = smum_send_msg_to_smc_with_parameter( PP_ASSERT_WITH_CODE 1130 drivers/gpu/drm/amd/powerplay/hwmgr/vega12_hwmgr.c PP_ASSERT_WITH_CODE(!(ret = smum_send_msg_to_smc_with_parameter( PP_ASSERT_WITH_CODE 1140 drivers/gpu/drm/amd/powerplay/hwmgr/vega12_hwmgr.c PP_ASSERT_WITH_CODE(!(ret = smum_send_msg_to_smc_with_parameter( PP_ASSERT_WITH_CODE 1150 drivers/gpu/drm/amd/powerplay/hwmgr/vega12_hwmgr.c PP_ASSERT_WITH_CODE(!(ret = smum_send_msg_to_smc_with_parameter( PP_ASSERT_WITH_CODE 1157 drivers/gpu/drm/amd/powerplay/hwmgr/vega12_hwmgr.c PP_ASSERT_WITH_CODE(!(ret = smum_send_msg_to_smc_with_parameter( PP_ASSERT_WITH_CODE 1167 drivers/gpu/drm/amd/powerplay/hwmgr/vega12_hwmgr.c PP_ASSERT_WITH_CODE(!(ret = smum_send_msg_to_smc_with_parameter( PP_ASSERT_WITH_CODE 1177 drivers/gpu/drm/amd/powerplay/hwmgr/vega12_hwmgr.c PP_ASSERT_WITH_CODE(!(ret = smum_send_msg_to_smc_with_parameter( PP_ASSERT_WITH_CODE 1193 drivers/gpu/drm/amd/powerplay/hwmgr/vega12_hwmgr.c PP_ASSERT_WITH_CODE(!vega12_enable_smc_features(hwmgr, PP_ASSERT_WITH_CODE 1214 drivers/gpu/drm/amd/powerplay/hwmgr/vega12_hwmgr.c PP_ASSERT_WITH_CODE( PP_ASSERT_WITH_CODE 1219 drivers/gpu/drm/amd/powerplay/hwmgr/vega12_hwmgr.c PP_ASSERT_WITH_CODE( PP_ASSERT_WITH_CODE 1237 drivers/gpu/drm/amd/powerplay/hwmgr/vega12_hwmgr.c PP_ASSERT_WITH_CODE( PP_ASSERT_WITH_CODE 1242 drivers/gpu/drm/amd/powerplay/hwmgr/vega12_hwmgr.c PP_ASSERT_WITH_CODE( PP_ASSERT_WITH_CODE 1291 drivers/gpu/drm/amd/powerplay/hwmgr/vega12_hwmgr.c PP_ASSERT_WITH_CODE(smum_send_msg_to_smc_with_parameter(hwmgr, PP_ASSERT_WITH_CODE 1308 drivers/gpu/drm/amd/powerplay/hwmgr/vega12_hwmgr.c PP_ASSERT_WITH_CODE( PP_ASSERT_WITH_CODE 1495 drivers/gpu/drm/amd/powerplay/hwmgr/vega12_hwmgr.c PP_ASSERT_WITH_CODE( PP_ASSERT_WITH_CODE 1528 drivers/gpu/drm/amd/powerplay/hwmgr/vega12_hwmgr.c PP_ASSERT_WITH_CODE(!vega12_upload_dpm_min_level(hwmgr), PP_ASSERT_WITH_CODE 1532 drivers/gpu/drm/amd/powerplay/hwmgr/vega12_hwmgr.c PP_ASSERT_WITH_CODE(!vega12_upload_dpm_max_level(hwmgr), PP_ASSERT_WITH_CODE 1557 drivers/gpu/drm/amd/powerplay/hwmgr/vega12_hwmgr.c PP_ASSERT_WITH_CODE(!vega12_upload_dpm_min_level(hwmgr), PP_ASSERT_WITH_CODE 1561 drivers/gpu/drm/amd/powerplay/hwmgr/vega12_hwmgr.c PP_ASSERT_WITH_CODE(!vega12_upload_dpm_max_level(hwmgr), PP_ASSERT_WITH_CODE 1571 drivers/gpu/drm/amd/powerplay/hwmgr/vega12_hwmgr.c PP_ASSERT_WITH_CODE(!vega12_upload_dpm_min_level(hwmgr), PP_ASSERT_WITH_CODE 1575 drivers/gpu/drm/amd/powerplay/hwmgr/vega12_hwmgr.c PP_ASSERT_WITH_CODE(!vega12_upload_dpm_max_level(hwmgr), PP_ASSERT_WITH_CODE 1898 drivers/gpu/drm/amd/powerplay/hwmgr/vega12_hwmgr.c PP_ASSERT_WITH_CODE(!ret, PP_ASSERT_WITH_CODE 1903 drivers/gpu/drm/amd/powerplay/hwmgr/vega12_hwmgr.c PP_ASSERT_WITH_CODE(!ret, PP_ASSERT_WITH_CODE 1918 drivers/gpu/drm/amd/powerplay/hwmgr/vega12_hwmgr.c PP_ASSERT_WITH_CODE(!ret, PP_ASSERT_WITH_CODE 1923 drivers/gpu/drm/amd/powerplay/hwmgr/vega12_hwmgr.c PP_ASSERT_WITH_CODE(!ret, PP_ASSERT_WITH_CODE 1946 drivers/gpu/drm/amd/powerplay/hwmgr/vega12_hwmgr.c PP_ASSERT_WITH_CODE(!ret, PP_ASSERT_WITH_CODE 1951 drivers/gpu/drm/amd/powerplay/hwmgr/vega12_hwmgr.c PP_ASSERT_WITH_CODE(!ret, PP_ASSERT_WITH_CODE 1971 drivers/gpu/drm/amd/powerplay/hwmgr/vega12_hwmgr.c PP_ASSERT_WITH_CODE(!ret, PP_ASSERT_WITH_CODE 2031 drivers/gpu/drm/amd/powerplay/hwmgr/vega12_hwmgr.c PP_ASSERT_WITH_CODE(!ret, PP_ASSERT_WITH_CODE 2095 drivers/gpu/drm/amd/powerplay/hwmgr/vega12_hwmgr.c PP_ASSERT_WITH_CODE( PP_ASSERT_WITH_CODE 2100 drivers/gpu/drm/amd/powerplay/hwmgr/vega12_hwmgr.c PP_ASSERT_WITH_CODE( PP_ASSERT_WITH_CODE 2111 drivers/gpu/drm/amd/powerplay/hwmgr/vega12_hwmgr.c PP_ASSERT_WITH_CODE( PP_ASSERT_WITH_CODE 2116 drivers/gpu/drm/amd/powerplay/hwmgr/vega12_hwmgr.c PP_ASSERT_WITH_CODE( PP_ASSERT_WITH_CODE 2127 drivers/gpu/drm/amd/powerplay/hwmgr/vega12_hwmgr.c PP_ASSERT_WITH_CODE( PP_ASSERT_WITH_CODE 2134 drivers/gpu/drm/amd/powerplay/hwmgr/vega12_hwmgr.c PP_ASSERT_WITH_CODE( PP_ASSERT_WITH_CODE 2145 drivers/gpu/drm/amd/powerplay/hwmgr/vega12_hwmgr.c PP_ASSERT_WITH_CODE( PP_ASSERT_WITH_CODE 2152 drivers/gpu/drm/amd/powerplay/hwmgr/vega12_hwmgr.c PP_ASSERT_WITH_CODE( PP_ASSERT_WITH_CODE 2338 drivers/gpu/drm/amd/powerplay/hwmgr/vega12_hwmgr.c PP_ASSERT_WITH_CODE(dpm_table->count > 0, PP_ASSERT_WITH_CODE 2341 drivers/gpu/drm/amd/powerplay/hwmgr/vega12_hwmgr.c PP_ASSERT_WITH_CODE(dpm_table->count <= NUM_UCLK_DPM_LEVELS, PP_ASSERT_WITH_CODE 2346 drivers/gpu/drm/amd/powerplay/hwmgr/vega12_hwmgr.c PP_ASSERT_WITH_CODE(!(ret = smum_send_msg_to_smc_with_parameter(hwmgr, PP_ASSERT_WITH_CODE 2380 drivers/gpu/drm/amd/powerplay/hwmgr/vega12_hwmgr.c PP_ASSERT_WITH_CODE(result, "Failed to update WMTABLE!", return EINVAL); PP_ASSERT_WITH_CODE 2399 drivers/gpu/drm/amd/powerplay/hwmgr/vega12_hwmgr.c PP_ASSERT_WITH_CODE(!vega12_enable_smc_features(hwmgr, PP_ASSERT_WITH_CODE 2454 drivers/gpu/drm/amd/powerplay/hwmgr/vega12_hwmgr.c PP_ASSERT_WITH_CODE((tmp_result == 0), PP_ASSERT_WITH_CODE 2466 drivers/gpu/drm/amd/powerplay/hwmgr/vega12_hwmgr.c PP_ASSERT_WITH_CODE((0 == result), PP_ASSERT_WITH_CODE 2659 drivers/gpu/drm/amd/powerplay/hwmgr/vega12_hwmgr.c PP_ASSERT_WITH_CODE((ret = smum_send_msg_to_smc(hwmgr, msg)) == 0, PP_ASSERT_WITH_CODE 68 drivers/gpu/drm/amd/powerplay/hwmgr/vega12_processpptables.c PP_ASSERT_WITH_CODE((powerplay_table->sHeader.format_revision >= PP_ASSERT_WITH_CODE 71 drivers/gpu/drm/amd/powerplay/hwmgr/vega12_processpptables.c PP_ASSERT_WITH_CODE(powerplay_table->sHeader.structuresize > 0, PP_ASSERT_WITH_CODE 106 drivers/gpu/drm/amd/powerplay/hwmgr/vega12_processpptables.c PP_ASSERT_WITH_CODE( PP_ASSERT_WITH_CODE 272 drivers/gpu/drm/amd/powerplay/hwmgr/vega12_processpptables.c PP_ASSERT_WITH_CODE((hwmgr->pptable != NULL), PP_ASSERT_WITH_CODE 276 drivers/gpu/drm/amd/powerplay/hwmgr/vega12_processpptables.c PP_ASSERT_WITH_CODE((powerplay_table != NULL), PP_ASSERT_WITH_CODE 280 drivers/gpu/drm/amd/powerplay/hwmgr/vega12_processpptables.c PP_ASSERT_WITH_CODE((result == 0), PP_ASSERT_WITH_CODE 285 drivers/gpu/drm/amd/powerplay/hwmgr/vega12_processpptables.c PP_ASSERT_WITH_CODE((result == 0), PP_ASSERT_WITH_CODE 289 drivers/gpu/drm/amd/powerplay/hwmgr/vega12_processpptables.c PP_ASSERT_WITH_CODE((result == 0), PP_ASSERT_WITH_CODE 367 drivers/gpu/drm/amd/powerplay/hwmgr/vega12_processpptables.c PP_ASSERT_WITH_CODE(pp_table, "Missing PowerPlay Table!", PP_ASSERT_WITH_CODE 377 drivers/gpu/drm/amd/powerplay/hwmgr/vega12_processpptables.c PP_ASSERT_WITH_CODE(pp_table->usStateArrayOffset > 0, PP_ASSERT_WITH_CODE 380 drivers/gpu/drm/amd/powerplay/hwmgr/vega12_processpptables.c PP_ASSERT_WITH_CODE(state_arrays->ucNumEntries > 0, PP_ASSERT_WITH_CODE 383 drivers/gpu/drm/amd/powerplay/hwmgr/vega12_processpptables.c PP_ASSERT_WITH_CODE((entry_index <= state_arrays->ucNumEntries), PP_ASSERT_WITH_CODE 34 drivers/gpu/drm/amd/powerplay/hwmgr/vega12_thermal.c PP_ASSERT_WITH_CODE(!smum_send_msg_to_smc(hwmgr, PP_ASSERT_WITH_CODE 75 drivers/gpu/drm/amd/powerplay/hwmgr/vega12_thermal.c PP_ASSERT_WITH_CODE(!vega12_enable_smc_features( PP_ASSERT_WITH_CODE 93 drivers/gpu/drm/amd/powerplay/hwmgr/vega12_thermal.c PP_ASSERT_WITH_CODE(!vega12_enable_smc_features( PP_ASSERT_WITH_CODE 110 drivers/gpu/drm/amd/powerplay/hwmgr/vega12_thermal.c PP_ASSERT_WITH_CODE( PP_ASSERT_WITH_CODE 124 drivers/gpu/drm/amd/powerplay/hwmgr/vega12_thermal.c PP_ASSERT_WITH_CODE(!vega12_disable_fan_control_feature(hwmgr), PP_ASSERT_WITH_CODE 489 drivers/gpu/drm/amd/powerplay/hwmgr/vega20_hwmgr.c PP_ASSERT_WITH_CODE(!ret, PP_ASSERT_WITH_CODE 527 drivers/gpu/drm/amd/powerplay/hwmgr/vega20_hwmgr.c PP_ASSERT_WITH_CODE(!ret, PP_ASSERT_WITH_CODE 532 drivers/gpu/drm/amd/powerplay/hwmgr/vega20_hwmgr.c PP_ASSERT_WITH_CODE(*num_of_levels > 0, PP_ASSERT_WITH_CODE 547 drivers/gpu/drm/amd/powerplay/hwmgr/vega20_hwmgr.c PP_ASSERT_WITH_CODE(!ret, PP_ASSERT_WITH_CODE 552 drivers/gpu/drm/amd/powerplay/hwmgr/vega20_hwmgr.c PP_ASSERT_WITH_CODE(*clk, PP_ASSERT_WITH_CODE 566 drivers/gpu/drm/amd/powerplay/hwmgr/vega20_hwmgr.c PP_ASSERT_WITH_CODE(!ret, PP_ASSERT_WITH_CODE 574 drivers/gpu/drm/amd/powerplay/hwmgr/vega20_hwmgr.c PP_ASSERT_WITH_CODE(!ret, PP_ASSERT_WITH_CODE 594 drivers/gpu/drm/amd/powerplay/hwmgr/vega20_hwmgr.c PP_ASSERT_WITH_CODE(!ret, PP_ASSERT_WITH_CODE 615 drivers/gpu/drm/amd/powerplay/hwmgr/vega20_hwmgr.c PP_ASSERT_WITH_CODE(!ret, PP_ASSERT_WITH_CODE 647 drivers/gpu/drm/amd/powerplay/hwmgr/vega20_hwmgr.c PP_ASSERT_WITH_CODE(!ret, PP_ASSERT_WITH_CODE 674 drivers/gpu/drm/amd/powerplay/hwmgr/vega20_hwmgr.c PP_ASSERT_WITH_CODE(!ret, PP_ASSERT_WITH_CODE 687 drivers/gpu/drm/amd/powerplay/hwmgr/vega20_hwmgr.c PP_ASSERT_WITH_CODE(!ret, PP_ASSERT_WITH_CODE 700 drivers/gpu/drm/amd/powerplay/hwmgr/vega20_hwmgr.c PP_ASSERT_WITH_CODE(!ret, PP_ASSERT_WITH_CODE 713 drivers/gpu/drm/amd/powerplay/hwmgr/vega20_hwmgr.c PP_ASSERT_WITH_CODE(!ret, PP_ASSERT_WITH_CODE 726 drivers/gpu/drm/amd/powerplay/hwmgr/vega20_hwmgr.c PP_ASSERT_WITH_CODE(!ret, PP_ASSERT_WITH_CODE 737 drivers/gpu/drm/amd/powerplay/hwmgr/vega20_hwmgr.c PP_ASSERT_WITH_CODE(!ret, PP_ASSERT_WITH_CODE 748 drivers/gpu/drm/amd/powerplay/hwmgr/vega20_hwmgr.c PP_ASSERT_WITH_CODE(!ret, PP_ASSERT_WITH_CODE 759 drivers/gpu/drm/amd/powerplay/hwmgr/vega20_hwmgr.c PP_ASSERT_WITH_CODE(!ret, PP_ASSERT_WITH_CODE 793 drivers/gpu/drm/amd/powerplay/hwmgr/vega20_hwmgr.c PP_ASSERT_WITH_CODE(!result, PP_ASSERT_WITH_CODE 818 drivers/gpu/drm/amd/powerplay/hwmgr/vega20_hwmgr.c PP_ASSERT_WITH_CODE(!result, PP_ASSERT_WITH_CODE 868 drivers/gpu/drm/amd/powerplay/hwmgr/vega20_hwmgr.c PP_ASSERT_WITH_CODE(!ret, PP_ASSERT_WITH_CODE 899 drivers/gpu/drm/amd/powerplay/hwmgr/vega20_hwmgr.c PP_ASSERT_WITH_CODE(!ret, PP_ASSERT_WITH_CODE 905 drivers/gpu/drm/amd/powerplay/hwmgr/vega20_hwmgr.c PP_ASSERT_WITH_CODE(!ret, PP_ASSERT_WITH_CODE 931 drivers/gpu/drm/amd/powerplay/hwmgr/vega20_hwmgr.c PP_ASSERT_WITH_CODE((ret = smum_send_msg_to_smc(hwmgr, PP_ASSERT_WITH_CODE 937 drivers/gpu/drm/amd/powerplay/hwmgr/vega20_hwmgr.c PP_ASSERT_WITH_CODE(!ret, PP_ASSERT_WITH_CODE 989 drivers/gpu/drm/amd/powerplay/hwmgr/vega20_hwmgr.c PP_ASSERT_WITH_CODE((ret = smum_send_msg_to_smc(hwmgr, PP_ASSERT_WITH_CODE 995 drivers/gpu/drm/amd/powerplay/hwmgr/vega20_hwmgr.c PP_ASSERT_WITH_CODE(!ret, PP_ASSERT_WITH_CODE 1199 drivers/gpu/drm/amd/powerplay/hwmgr/vega20_hwmgr.c PP_ASSERT_WITH_CODE(!ret, PP_ASSERT_WITH_CODE 1227 drivers/gpu/drm/amd/powerplay/hwmgr/vega20_hwmgr.c PP_ASSERT_WITH_CODE(!ret, PP_ASSERT_WITH_CODE 1256 drivers/gpu/drm/amd/powerplay/hwmgr/vega20_hwmgr.c PP_ASSERT_WITH_CODE(!vega20_od8_get_gfx_clock_base_voltage(hwmgr, PP_ASSERT_WITH_CODE 1264 drivers/gpu/drm/amd/powerplay/hwmgr/vega20_hwmgr.c PP_ASSERT_WITH_CODE(!vega20_od8_get_gfx_clock_base_voltage(hwmgr, PP_ASSERT_WITH_CODE 1272 drivers/gpu/drm/amd/powerplay/hwmgr/vega20_hwmgr.c PP_ASSERT_WITH_CODE(!vega20_od8_get_gfx_clock_base_voltage(hwmgr, PP_ASSERT_WITH_CODE 1355 drivers/gpu/drm/amd/powerplay/hwmgr/vega20_hwmgr.c PP_ASSERT_WITH_CODE(!ret, PP_ASSERT_WITH_CODE 1374 drivers/gpu/drm/amd/powerplay/hwmgr/vega20_hwmgr.c PP_ASSERT_WITH_CODE(!ret, PP_ASSERT_WITH_CODE 1431 drivers/gpu/drm/amd/powerplay/hwmgr/vega20_hwmgr.c PP_ASSERT_WITH_CODE(!ret, PP_ASSERT_WITH_CODE 1471 drivers/gpu/drm/amd/powerplay/hwmgr/vega20_hwmgr.c PP_ASSERT_WITH_CODE(!ret, PP_ASSERT_WITH_CODE 1477 drivers/gpu/drm/amd/powerplay/hwmgr/vega20_hwmgr.c PP_ASSERT_WITH_CODE(!ret, PP_ASSERT_WITH_CODE 1517 drivers/gpu/drm/amd/powerplay/hwmgr/vega20_hwmgr.c PP_ASSERT_WITH_CODE(!ret, PP_ASSERT_WITH_CODE 1523 drivers/gpu/drm/amd/powerplay/hwmgr/vega20_hwmgr.c PP_ASSERT_WITH_CODE(!ret, PP_ASSERT_WITH_CODE 1557 drivers/gpu/drm/amd/powerplay/hwmgr/vega20_hwmgr.c PP_ASSERT_WITH_CODE((ret = smum_send_msg_to_smc_with_parameter(hwmgr, PP_ASSERT_WITH_CODE 1566 drivers/gpu/drm/amd/powerplay/hwmgr/vega20_hwmgr.c PP_ASSERT_WITH_CODE((ret = smum_send_msg_to_smc_with_parameter(hwmgr, PP_ASSERT_WITH_CODE 1593 drivers/gpu/drm/amd/powerplay/hwmgr/vega20_hwmgr.c PP_ASSERT_WITH_CODE((ret = vega20_get_max_sustainable_clock(hwmgr, PP_ASSERT_WITH_CODE 1600 drivers/gpu/drm/amd/powerplay/hwmgr/vega20_hwmgr.c PP_ASSERT_WITH_CODE((ret = vega20_get_max_sustainable_clock(hwmgr, PP_ASSERT_WITH_CODE 1607 drivers/gpu/drm/amd/powerplay/hwmgr/vega20_hwmgr.c PP_ASSERT_WITH_CODE((ret = vega20_get_max_sustainable_clock(hwmgr, PP_ASSERT_WITH_CODE 1612 drivers/gpu/drm/amd/powerplay/hwmgr/vega20_hwmgr.c PP_ASSERT_WITH_CODE((ret = vega20_get_max_sustainable_clock(hwmgr, PP_ASSERT_WITH_CODE 1617 drivers/gpu/drm/amd/powerplay/hwmgr/vega20_hwmgr.c PP_ASSERT_WITH_CODE((ret = vega20_get_max_sustainable_clock(hwmgr, PP_ASSERT_WITH_CODE 1622 drivers/gpu/drm/amd/powerplay/hwmgr/vega20_hwmgr.c PP_ASSERT_WITH_CODE((ret = vega20_get_max_sustainable_clock(hwmgr, PP_ASSERT_WITH_CODE 1641 drivers/gpu/drm/amd/powerplay/hwmgr/vega20_hwmgr.c PP_ASSERT_WITH_CODE(!result, PP_ASSERT_WITH_CODE 1671 drivers/gpu/drm/amd/powerplay/hwmgr/vega20_hwmgr.c PP_ASSERT_WITH_CODE(!result, PP_ASSERT_WITH_CODE 1676 drivers/gpu/drm/amd/powerplay/hwmgr/vega20_hwmgr.c PP_ASSERT_WITH_CODE(!result, PP_ASSERT_WITH_CODE 1681 drivers/gpu/drm/amd/powerplay/hwmgr/vega20_hwmgr.c PP_ASSERT_WITH_CODE(!result, PP_ASSERT_WITH_CODE 1686 drivers/gpu/drm/amd/powerplay/hwmgr/vega20_hwmgr.c PP_ASSERT_WITH_CODE(!result, PP_ASSERT_WITH_CODE 1691 drivers/gpu/drm/amd/powerplay/hwmgr/vega20_hwmgr.c PP_ASSERT_WITH_CODE(!result, PP_ASSERT_WITH_CODE 1696 drivers/gpu/drm/amd/powerplay/hwmgr/vega20_hwmgr.c PP_ASSERT_WITH_CODE(!result, PP_ASSERT_WITH_CODE 1701 drivers/gpu/drm/amd/powerplay/hwmgr/vega20_hwmgr.c PP_ASSERT_WITH_CODE(!result, PP_ASSERT_WITH_CODE 1706 drivers/gpu/drm/amd/powerplay/hwmgr/vega20_hwmgr.c PP_ASSERT_WITH_CODE(!result, PP_ASSERT_WITH_CODE 1714 drivers/gpu/drm/amd/powerplay/hwmgr/vega20_hwmgr.c PP_ASSERT_WITH_CODE(!result, PP_ASSERT_WITH_CODE 1719 drivers/gpu/drm/amd/powerplay/hwmgr/vega20_hwmgr.c PP_ASSERT_WITH_CODE(!result, PP_ASSERT_WITH_CODE 1724 drivers/gpu/drm/amd/powerplay/hwmgr/vega20_hwmgr.c PP_ASSERT_WITH_CODE(!result, PP_ASSERT_WITH_CODE 1729 drivers/gpu/drm/amd/powerplay/hwmgr/vega20_hwmgr.c PP_ASSERT_WITH_CODE(!result, PP_ASSERT_WITH_CODE 1734 drivers/gpu/drm/amd/powerplay/hwmgr/vega20_hwmgr.c PP_ASSERT_WITH_CODE(!result, PP_ASSERT_WITH_CODE 1740 drivers/gpu/drm/amd/powerplay/hwmgr/vega20_hwmgr.c PP_ASSERT_WITH_CODE(!result, PP_ASSERT_WITH_CODE 1771 drivers/gpu/drm/amd/powerplay/hwmgr/vega20_hwmgr.c PP_ASSERT_WITH_CODE(table != NULL, PP_ASSERT_WITH_CODE 1774 drivers/gpu/drm/amd/powerplay/hwmgr/vega20_hwmgr.c PP_ASSERT_WITH_CODE(table->count > 0, PP_ASSERT_WITH_CODE 1777 drivers/gpu/drm/amd/powerplay/hwmgr/vega20_hwmgr.c PP_ASSERT_WITH_CODE(table->count <= MAX_REGULAR_DPM_NUMBER, PP_ASSERT_WITH_CODE 1803 drivers/gpu/drm/amd/powerplay/hwmgr/vega20_hwmgr.c PP_ASSERT_WITH_CODE(!(ret = smum_send_msg_to_smc_with_parameter( PP_ASSERT_WITH_CODE 1813 drivers/gpu/drm/amd/powerplay/hwmgr/vega20_hwmgr.c PP_ASSERT_WITH_CODE(!(ret = smum_send_msg_to_smc_with_parameter( PP_ASSERT_WITH_CODE 1824 drivers/gpu/drm/amd/powerplay/hwmgr/vega20_hwmgr.c PP_ASSERT_WITH_CODE(!(ret = smum_send_msg_to_smc_with_parameter( PP_ASSERT_WITH_CODE 1832 drivers/gpu/drm/amd/powerplay/hwmgr/vega20_hwmgr.c PP_ASSERT_WITH_CODE(!(ret = smum_send_msg_to_smc_with_parameter( PP_ASSERT_WITH_CODE 1843 drivers/gpu/drm/amd/powerplay/hwmgr/vega20_hwmgr.c PP_ASSERT_WITH_CODE(!(ret = smum_send_msg_to_smc_with_parameter( PP_ASSERT_WITH_CODE 1854 drivers/gpu/drm/amd/powerplay/hwmgr/vega20_hwmgr.c PP_ASSERT_WITH_CODE(!(ret = smum_send_msg_to_smc_with_parameter( PP_ASSERT_WITH_CODE 1865 drivers/gpu/drm/amd/powerplay/hwmgr/vega20_hwmgr.c PP_ASSERT_WITH_CODE(!(ret = smum_send_msg_to_smc_with_parameter( PP_ASSERT_WITH_CODE 1876 drivers/gpu/drm/amd/powerplay/hwmgr/vega20_hwmgr.c PP_ASSERT_WITH_CODE(!(ret = smum_send_msg_to_smc_with_parameter( PP_ASSERT_WITH_CODE 1897 drivers/gpu/drm/amd/powerplay/hwmgr/vega20_hwmgr.c PP_ASSERT_WITH_CODE(!(ret = smum_send_msg_to_smc_with_parameter( PP_ASSERT_WITH_CODE 1908 drivers/gpu/drm/amd/powerplay/hwmgr/vega20_hwmgr.c PP_ASSERT_WITH_CODE(!(ret = smum_send_msg_to_smc_with_parameter( PP_ASSERT_WITH_CODE 1919 drivers/gpu/drm/amd/powerplay/hwmgr/vega20_hwmgr.c PP_ASSERT_WITH_CODE(!(ret = smum_send_msg_to_smc_with_parameter( PP_ASSERT_WITH_CODE 1926 drivers/gpu/drm/amd/powerplay/hwmgr/vega20_hwmgr.c PP_ASSERT_WITH_CODE(!(ret = smum_send_msg_to_smc_with_parameter( PP_ASSERT_WITH_CODE 1937 drivers/gpu/drm/amd/powerplay/hwmgr/vega20_hwmgr.c PP_ASSERT_WITH_CODE(!(ret = smum_send_msg_to_smc_with_parameter( PP_ASSERT_WITH_CODE 1948 drivers/gpu/drm/amd/powerplay/hwmgr/vega20_hwmgr.c PP_ASSERT_WITH_CODE(!(ret = smum_send_msg_to_smc_with_parameter( PP_ASSERT_WITH_CODE 1959 drivers/gpu/drm/amd/powerplay/hwmgr/vega20_hwmgr.c PP_ASSERT_WITH_CODE(!(ret = smum_send_msg_to_smc_with_parameter( PP_ASSERT_WITH_CODE 1986 drivers/gpu/drm/amd/powerplay/hwmgr/vega20_hwmgr.c PP_ASSERT_WITH_CODE(!ret, PP_ASSERT_WITH_CODE 2004 drivers/gpu/drm/amd/powerplay/hwmgr/vega20_hwmgr.c PP_ASSERT_WITH_CODE((ret = smum_send_msg_to_smc_with_parameter(hwmgr, PP_ASSERT_WITH_CODE 2010 drivers/gpu/drm/amd/powerplay/hwmgr/vega20_hwmgr.c PP_ASSERT_WITH_CODE((ret = smum_send_msg_to_smc_with_parameter(hwmgr, PP_ASSERT_WITH_CODE 2028 drivers/gpu/drm/amd/powerplay/hwmgr/vega20_hwmgr.c PP_ASSERT_WITH_CODE(data->smu_features[GNLD_DPM_GFXCLK].enabled, PP_ASSERT_WITH_CODE 2034 drivers/gpu/drm/amd/powerplay/hwmgr/vega20_hwmgr.c PP_ASSERT_WITH_CODE(!ret, PP_ASSERT_WITH_CODE 2039 drivers/gpu/drm/amd/powerplay/hwmgr/vega20_hwmgr.c PP_ASSERT_WITH_CODE(!ret, PP_ASSERT_WITH_CODE 2054 drivers/gpu/drm/amd/powerplay/hwmgr/vega20_hwmgr.c PP_ASSERT_WITH_CODE(data->smu_features[GNLD_DPM_UCLK].enabled, PP_ASSERT_WITH_CODE 2060 drivers/gpu/drm/amd/powerplay/hwmgr/vega20_hwmgr.c PP_ASSERT_WITH_CODE(!ret, PP_ASSERT_WITH_CODE 2065 drivers/gpu/drm/amd/powerplay/hwmgr/vega20_hwmgr.c PP_ASSERT_WITH_CODE(!ret, PP_ASSERT_WITH_CODE 2120 drivers/gpu/drm/amd/powerplay/hwmgr/vega20_hwmgr.c PP_ASSERT_WITH_CODE((ret = smum_send_msg_to_smc_with_parameter(hwmgr, PP_ASSERT_WITH_CODE 2309 drivers/gpu/drm/amd/powerplay/hwmgr/vega20_hwmgr.c PP_ASSERT_WITH_CODE((ret = smum_send_msg_to_smc_with_parameter( PP_ASSERT_WITH_CODE 2321 drivers/gpu/drm/amd/powerplay/hwmgr/vega20_hwmgr.c PP_ASSERT_WITH_CODE(!(ret = smum_send_msg_to_smc_with_parameter(hwmgr, PP_ASSERT_WITH_CODE 2359 drivers/gpu/drm/amd/powerplay/hwmgr/vega20_hwmgr.c PP_ASSERT_WITH_CODE(!ret, PP_ASSERT_WITH_CODE 2366 drivers/gpu/drm/amd/powerplay/hwmgr/vega20_hwmgr.c PP_ASSERT_WITH_CODE(!ret, PP_ASSERT_WITH_CODE 2401 drivers/gpu/drm/amd/powerplay/hwmgr/vega20_hwmgr.c PP_ASSERT_WITH_CODE(!ret, PP_ASSERT_WITH_CODE 2408 drivers/gpu/drm/amd/powerplay/hwmgr/vega20_hwmgr.c PP_ASSERT_WITH_CODE(!ret, PP_ASSERT_WITH_CODE 2459 drivers/gpu/drm/amd/powerplay/hwmgr/vega20_hwmgr.c PP_ASSERT_WITH_CODE(!ret, PP_ASSERT_WITH_CODE 2466 drivers/gpu/drm/amd/powerplay/hwmgr/vega20_hwmgr.c PP_ASSERT_WITH_CODE(!ret, PP_ASSERT_WITH_CODE 2531 drivers/gpu/drm/amd/powerplay/hwmgr/vega20_hwmgr.c PP_ASSERT_WITH_CODE(!ret, PP_ASSERT_WITH_CODE 2536 drivers/gpu/drm/amd/powerplay/hwmgr/vega20_hwmgr.c PP_ASSERT_WITH_CODE(!ret, PP_ASSERT_WITH_CODE 2558 drivers/gpu/drm/amd/powerplay/hwmgr/vega20_hwmgr.c PP_ASSERT_WITH_CODE(!ret, PP_ASSERT_WITH_CODE 2563 drivers/gpu/drm/amd/powerplay/hwmgr/vega20_hwmgr.c PP_ASSERT_WITH_CODE(!ret, PP_ASSERT_WITH_CODE 2586 drivers/gpu/drm/amd/powerplay/hwmgr/vega20_hwmgr.c PP_ASSERT_WITH_CODE(!ret, PP_ASSERT_WITH_CODE 2591 drivers/gpu/drm/amd/powerplay/hwmgr/vega20_hwmgr.c PP_ASSERT_WITH_CODE(!ret, PP_ASSERT_WITH_CODE 2614 drivers/gpu/drm/amd/powerplay/hwmgr/vega20_hwmgr.c PP_ASSERT_WITH_CODE(!ret, PP_ASSERT_WITH_CODE 2619 drivers/gpu/drm/amd/powerplay/hwmgr/vega20_hwmgr.c PP_ASSERT_WITH_CODE(!ret, PP_ASSERT_WITH_CODE 2639 drivers/gpu/drm/amd/powerplay/hwmgr/vega20_hwmgr.c PP_ASSERT_WITH_CODE(!ret, PP_ASSERT_WITH_CODE 2656 drivers/gpu/drm/amd/powerplay/hwmgr/vega20_hwmgr.c PP_ASSERT_WITH_CODE(!ret, PP_ASSERT_WITH_CODE 2919 drivers/gpu/drm/amd/powerplay/hwmgr/vega20_hwmgr.c PP_ASSERT_WITH_CODE(input, "NULL user input for clock and voltage", PP_ASSERT_WITH_CODE 3079 drivers/gpu/drm/amd/powerplay/hwmgr/vega20_hwmgr.c PP_ASSERT_WITH_CODE(!ret, PP_ASSERT_WITH_CODE 3088 drivers/gpu/drm/amd/powerplay/hwmgr/vega20_hwmgr.c PP_ASSERT_WITH_CODE(!ret, PP_ASSERT_WITH_CODE 3139 drivers/gpu/drm/amd/powerplay/hwmgr/vega20_hwmgr.c PP_ASSERT_WITH_CODE((ret = smum_send_msg_to_smc(hwmgr, msg)) == 0, PP_ASSERT_WITH_CODE 3193 drivers/gpu/drm/amd/powerplay/hwmgr/vega20_hwmgr.c PP_ASSERT_WITH_CODE(!ret, PP_ASSERT_WITH_CODE 3272 drivers/gpu/drm/amd/powerplay/hwmgr/vega20_hwmgr.c PP_ASSERT_WITH_CODE(!ret, PP_ASSERT_WITH_CODE 3290 drivers/gpu/drm/amd/powerplay/hwmgr/vega20_hwmgr.c PP_ASSERT_WITH_CODE(!ret, PP_ASSERT_WITH_CODE 3308 drivers/gpu/drm/amd/powerplay/hwmgr/vega20_hwmgr.c PP_ASSERT_WITH_CODE(!ret, PP_ASSERT_WITH_CODE 3326 drivers/gpu/drm/amd/powerplay/hwmgr/vega20_hwmgr.c PP_ASSERT_WITH_CODE(!ret, PP_ASSERT_WITH_CODE 3338 drivers/gpu/drm/amd/powerplay/hwmgr/vega20_hwmgr.c PP_ASSERT_WITH_CODE(!ret, PP_ASSERT_WITH_CODE 3484 drivers/gpu/drm/amd/powerplay/hwmgr/vega20_hwmgr.c PP_ASSERT_WITH_CODE(dpm_table->count > 0, PP_ASSERT_WITH_CODE 3487 drivers/gpu/drm/amd/powerplay/hwmgr/vega20_hwmgr.c PP_ASSERT_WITH_CODE(dpm_table->count <= NUM_UCLK_DPM_LEVELS, PP_ASSERT_WITH_CODE 3492 drivers/gpu/drm/amd/powerplay/hwmgr/vega20_hwmgr.c PP_ASSERT_WITH_CODE(!(ret = smum_send_msg_to_smc_with_parameter(hwmgr, PP_ASSERT_WITH_CODE 3509 drivers/gpu/drm/amd/powerplay/hwmgr/vega20_hwmgr.c PP_ASSERT_WITH_CODE(dpm_table->count > 0, PP_ASSERT_WITH_CODE 3512 drivers/gpu/drm/amd/powerplay/hwmgr/vega20_hwmgr.c PP_ASSERT_WITH_CODE(dpm_table->count <= NUM_FCLK_DPM_LEVELS, PP_ASSERT_WITH_CODE 3517 drivers/gpu/drm/amd/powerplay/hwmgr/vega20_hwmgr.c PP_ASSERT_WITH_CODE(!(ret = smum_send_msg_to_smc_with_parameter(hwmgr, PP_ASSERT_WITH_CODE 3553 drivers/gpu/drm/amd/powerplay/hwmgr/vega20_hwmgr.c PP_ASSERT_WITH_CODE(!result, PP_ASSERT_WITH_CODE 3587 drivers/gpu/drm/amd/powerplay/hwmgr/vega20_hwmgr.c PP_ASSERT_WITH_CODE(!ret, PP_ASSERT_WITH_CODE 3829 drivers/gpu/drm/amd/powerplay/hwmgr/vega20_hwmgr.c PP_ASSERT_WITH_CODE(!ret, PP_ASSERT_WITH_CODE 3842 drivers/gpu/drm/amd/powerplay/hwmgr/vega20_hwmgr.c PP_ASSERT_WITH_CODE((0 == result), PP_ASSERT_WITH_CODE 3920 drivers/gpu/drm/amd/powerplay/hwmgr/vega20_hwmgr.c PP_ASSERT_WITH_CODE(!result, PP_ASSERT_WITH_CODE 4009 drivers/gpu/drm/amd/powerplay/hwmgr/vega20_hwmgr.c PP_ASSERT_WITH_CODE(!result, PP_ASSERT_WITH_CODE 4071 drivers/gpu/drm/amd/powerplay/hwmgr/vega20_hwmgr.c PP_ASSERT_WITH_CODE(!result, PP_ASSERT_WITH_CODE 4154 drivers/gpu/drm/amd/powerplay/hwmgr/vega20_hwmgr.c PP_ASSERT_WITH_CODE(!res, "[SmuI2CAccessBus] Failed to access bus!", return res); PP_ASSERT_WITH_CODE 642 drivers/gpu/drm/amd/powerplay/hwmgr/vega20_processpptables.c PP_ASSERT_WITH_CODE((powerplay_table->sHeader.format_revision >= PP_ASSERT_WITH_CODE 645 drivers/gpu/drm/amd/powerplay/hwmgr/vega20_processpptables.c PP_ASSERT_WITH_CODE(powerplay_table->sHeader.structuresize > 0, PP_ASSERT_WITH_CODE 722 drivers/gpu/drm/amd/powerplay/hwmgr/vega20_processpptables.c PP_ASSERT_WITH_CODE( PP_ASSERT_WITH_CODE 917 drivers/gpu/drm/amd/powerplay/hwmgr/vega20_processpptables.c PP_ASSERT_WITH_CODE((hwmgr->pptable != NULL), PP_ASSERT_WITH_CODE 921 drivers/gpu/drm/amd/powerplay/hwmgr/vega20_processpptables.c PP_ASSERT_WITH_CODE((powerplay_table != NULL), PP_ASSERT_WITH_CODE 925 drivers/gpu/drm/amd/powerplay/hwmgr/vega20_processpptables.c PP_ASSERT_WITH_CODE((result == 0), PP_ASSERT_WITH_CODE 930 drivers/gpu/drm/amd/powerplay/hwmgr/vega20_processpptables.c PP_ASSERT_WITH_CODE((result == 0), PP_ASSERT_WITH_CODE 934 drivers/gpu/drm/amd/powerplay/hwmgr/vega20_processpptables.c PP_ASSERT_WITH_CODE((result == 0), PP_ASSERT_WITH_CODE 42 drivers/gpu/drm/amd/powerplay/hwmgr/vega20_thermal.c PP_ASSERT_WITH_CODE(!ret, PP_ASSERT_WITH_CODE 71 drivers/gpu/drm/amd/powerplay/hwmgr/vega20_thermal.c PP_ASSERT_WITH_CODE(!ret, PP_ASSERT_WITH_CODE 108 drivers/gpu/drm/amd/powerplay/hwmgr/vega20_thermal.c PP_ASSERT_WITH_CODE((ret = smum_send_msg_to_smc(hwmgr, PP_ASSERT_WITH_CODE 313 drivers/gpu/drm/amd/powerplay/smumgr/ci_smumgr.c PP_ASSERT_WITH_CODE(result == 0, PP_ASSERT_WITH_CODE 550 drivers/gpu/drm/amd/powerplay/smumgr/ci_smumgr.c PP_ASSERT_WITH_CODE(false, PP_ASSERT_WITH_CODE 583 drivers/gpu/drm/amd/powerplay/smumgr/ci_smumgr.c PP_ASSERT_WITH_CODE(NULL != hwmgr->dyn_state.cac_leakage_table, PP_ASSERT_WITH_CODE 585 drivers/gpu/drm/amd/powerplay/smumgr/ci_smumgr.c PP_ASSERT_WITH_CODE(hwmgr->dyn_state.cac_leakage_table->count <= 8, PP_ASSERT_WITH_CODE 587 drivers/gpu/drm/amd/powerplay/smumgr/ci_smumgr.c PP_ASSERT_WITH_CODE(hwmgr->dyn_state.cac_leakage_table->count == hwmgr->dyn_state.vddc_dependency_on_sclk->count, PP_ASSERT_WITH_CODE 611 drivers/gpu/drm/amd/powerplay/smumgr/ci_smumgr.c PP_ASSERT_WITH_CODE(data->vddc_voltage_table.count <= 8, PP_ASSERT_WITH_CODE 771 drivers/gpu/drm/amd/powerplay/smumgr/ci_smumgr.c PP_ASSERT_WITH_CODE(NULL != hwmgr->dyn_state.vddc_dependency_on_sclk, PP_ASSERT_WITH_CODE 851 drivers/gpu/drm/amd/powerplay/smumgr/ci_smumgr.c PP_ASSERT_WITH_CODE(0 == result, "do not populate SMC VDDC voltage table", return -EINVAL); PP_ASSERT_WITH_CODE 881 drivers/gpu/drm/amd/powerplay/smumgr/ci_smumgr.c PP_ASSERT_WITH_CODE(result == 0, "do not populate SMC VDDCI voltage table", return -EINVAL); PP_ASSERT_WITH_CODE 909 drivers/gpu/drm/amd/powerplay/smumgr/ci_smumgr.c PP_ASSERT_WITH_CODE(result == 0, "do not populate SMC mvdd voltage table", return -EINVAL); PP_ASSERT_WITH_CODE 931 drivers/gpu/drm/amd/powerplay/smumgr/ci_smumgr.c PP_ASSERT_WITH_CODE(0 == result, PP_ASSERT_WITH_CODE 935 drivers/gpu/drm/amd/powerplay/smumgr/ci_smumgr.c PP_ASSERT_WITH_CODE(0 == result, PP_ASSERT_WITH_CODE 939 drivers/gpu/drm/amd/powerplay/smumgr/ci_smumgr.c PP_ASSERT_WITH_CODE(0 == result, PP_ASSERT_WITH_CODE 956 drivers/gpu/drm/amd/powerplay/smumgr/ci_smumgr.c PP_ASSERT_WITH_CODE((0 == result), "can not get ULV voltage value", return result;); PP_ASSERT_WITH_CODE 1045 drivers/gpu/drm/amd/powerplay/smumgr/ci_smumgr.c PP_ASSERT_WITH_CODE(0 == result, PP_ASSERT_WITH_CODE 1188 drivers/gpu/drm/amd/powerplay/smumgr/ci_smumgr.c PP_ASSERT_WITH_CODE((0 == result), PP_ASSERT_WITH_CODE 1197 drivers/gpu/drm/amd/powerplay/smumgr/ci_smumgr.c PP_ASSERT_WITH_CODE((0 == result), PP_ASSERT_WITH_CODE 1206 drivers/gpu/drm/amd/powerplay/smumgr/ci_smumgr.c PP_ASSERT_WITH_CODE((0 == result), PP_ASSERT_WITH_CODE 1315 drivers/gpu/drm/amd/powerplay/smumgr/ci_smumgr.c PP_ASSERT_WITH_CODE((0 != dpm_table->mclk_table.dpm_levels[i].value), PP_ASSERT_WITH_CODE 1365 drivers/gpu/drm/amd/powerplay/smumgr/ci_smumgr.c PP_ASSERT_WITH_CODE(i < hwmgr->dyn_state.mvdd_dependency_on_mclk->count, PP_ASSERT_WITH_CODE 1405 drivers/gpu/drm/amd/powerplay/smumgr/ci_smumgr.c PP_ASSERT_WITH_CODE(result == 0, PP_ASSERT_WITH_CODE 1538 drivers/gpu/drm/amd/powerplay/smumgr/ci_smumgr.c PP_ASSERT_WITH_CODE((0 == result), PP_ASSERT_WITH_CODE 1545 drivers/gpu/drm/amd/powerplay/smumgr/ci_smumgr.c PP_ASSERT_WITH_CODE((0 == result), PP_ASSERT_WITH_CODE 1577 drivers/gpu/drm/amd/powerplay/smumgr/ci_smumgr.c PP_ASSERT_WITH_CODE((0 == result), PP_ASSERT_WITH_CODE 1608 drivers/gpu/drm/amd/powerplay/smumgr/ci_smumgr.c PP_ASSERT_WITH_CODE((0 == result), PP_ASSERT_WITH_CODE 1634 drivers/gpu/drm/amd/powerplay/smumgr/ci_smumgr.c PP_ASSERT_WITH_CODE(result == 0, PP_ASSERT_WITH_CODE 1730 drivers/gpu/drm/amd/powerplay/smumgr/ci_smumgr.c PP_ASSERT_WITH_CODE(i < SMU7_DISCRETE_MC_REGISTER_ARRAY_SIZE, PP_ASSERT_WITH_CODE 1841 drivers/gpu/drm/amd/powerplay/smumgr/ci_smumgr.c PP_ASSERT_WITH_CODE(0 == result, PP_ASSERT_WITH_CODE 1845 drivers/gpu/drm/amd/powerplay/smumgr/ci_smumgr.c PP_ASSERT_WITH_CODE(0 == result, PP_ASSERT_WITH_CODE 1969 drivers/gpu/drm/amd/powerplay/smumgr/ci_smumgr.c PP_ASSERT_WITH_CODE(0 == result, PP_ASSERT_WITH_CODE 1977 drivers/gpu/drm/amd/powerplay/smumgr/ci_smumgr.c PP_ASSERT_WITH_CODE(0 == result, PP_ASSERT_WITH_CODE 1981 drivers/gpu/drm/amd/powerplay/smumgr/ci_smumgr.c PP_ASSERT_WITH_CODE(0 == result, PP_ASSERT_WITH_CODE 1985 drivers/gpu/drm/amd/powerplay/smumgr/ci_smumgr.c PP_ASSERT_WITH_CODE(0 == result, PP_ASSERT_WITH_CODE 1989 drivers/gpu/drm/amd/powerplay/smumgr/ci_smumgr.c PP_ASSERT_WITH_CODE(0 == result, PP_ASSERT_WITH_CODE 1993 drivers/gpu/drm/amd/powerplay/smumgr/ci_smumgr.c PP_ASSERT_WITH_CODE(0 == result, PP_ASSERT_WITH_CODE 1997 drivers/gpu/drm/amd/powerplay/smumgr/ci_smumgr.c PP_ASSERT_WITH_CODE(0 == result, PP_ASSERT_WITH_CODE 2003 drivers/gpu/drm/amd/powerplay/smumgr/ci_smumgr.c PP_ASSERT_WITH_CODE(0 == result, PP_ASSERT_WITH_CODE 2007 drivers/gpu/drm/amd/powerplay/smumgr/ci_smumgr.c PP_ASSERT_WITH_CODE(0 == result, PP_ASSERT_WITH_CODE 2019 drivers/gpu/drm/amd/powerplay/smumgr/ci_smumgr.c PP_ASSERT_WITH_CODE(0 == result, PP_ASSERT_WITH_CODE 2023 drivers/gpu/drm/amd/powerplay/smumgr/ci_smumgr.c PP_ASSERT_WITH_CODE(0 == result, "Failed to initialize Boot State!", return result); PP_ASSERT_WITH_CODE 2026 drivers/gpu/drm/amd/powerplay/smumgr/ci_smumgr.c PP_ASSERT_WITH_CODE(0 == result, "Failed to populate BAPM Parameters!", return result); PP_ASSERT_WITH_CODE 2052 drivers/gpu/drm/amd/powerplay/smumgr/ci_smumgr.c PP_ASSERT_WITH_CODE((1 <= data->dpm_table.pcie_speed_table.count), PP_ASSERT_WITH_CODE 2060 drivers/gpu/drm/amd/powerplay/smumgr/ci_smumgr.c PP_ASSERT_WITH_CODE(0 == result, PP_ASSERT_WITH_CODE 2107 drivers/gpu/drm/amd/powerplay/smumgr/ci_smumgr.c PP_ASSERT_WITH_CODE(0 == result, PP_ASSERT_WITH_CODE 2111 drivers/gpu/drm/amd/powerplay/smumgr/ci_smumgr.c PP_ASSERT_WITH_CODE((0 == result), PP_ASSERT_WITH_CODE 2115 drivers/gpu/drm/amd/powerplay/smumgr/ci_smumgr.c PP_ASSERT_WITH_CODE(0 == result, PP_ASSERT_WITH_CODE 2237 drivers/gpu/drm/amd/powerplay/smumgr/ci_smumgr.c PP_ASSERT_WITH_CODE((0 == result), "Failed to upload MC reg table!", return result); PP_ASSERT_WITH_CODE 2240 drivers/gpu/drm/amd/powerplay/smumgr/ci_smumgr.c PP_ASSERT_WITH_CODE((result == 0), PP_ASSERT_WITH_CODE 2556 drivers/gpu/drm/amd/powerplay/smumgr/ci_smumgr.c PP_ASSERT_WITH_CODE((table->last <= SMU7_DISCRETE_MC_REGISTER_ARRAY_SIZE), PP_ASSERT_WITH_CODE 2558 drivers/gpu/drm/amd/powerplay/smumgr/ci_smumgr.c PP_ASSERT_WITH_CODE((table->num_entries <= MAX_AC_TIMING_ENTRIES), PP_ASSERT_WITH_CODE 2588 drivers/gpu/drm/amd/powerplay/smumgr/ci_smumgr.c PP_ASSERT_WITH_CODE((j < SMU7_DISCRETE_MC_REGISTER_ARRAY_SIZE), PP_ASSERT_WITH_CODE 2604 drivers/gpu/drm/amd/powerplay/smumgr/ci_smumgr.c PP_ASSERT_WITH_CODE((j < SMU7_DISCRETE_MC_REGISTER_ARRAY_SIZE), PP_ASSERT_WITH_CODE 2620 drivers/gpu/drm/amd/powerplay/smumgr/ci_smumgr.c PP_ASSERT_WITH_CODE((j < SMU7_DISCRETE_MC_REGISTER_ARRAY_SIZE), PP_ASSERT_WITH_CODE 151 drivers/gpu/drm/amd/powerplay/smumgr/fiji_smumgr.c PP_ASSERT_WITH_CODE(false, PP_ASSERT_WITH_CODE 230 drivers/gpu/drm/amd/powerplay/smumgr/fiji_smumgr.c PP_ASSERT_WITH_CODE(0 == smu7_read_smc_sram_dword(hwmgr, PP_ASSERT_WITH_CODE 245 drivers/gpu/drm/amd/powerplay/smumgr/fiji_smumgr.c PP_ASSERT_WITH_CODE(0 == smu7_copy_bytes_to_smc(hwmgr, vr_config_addr, PP_ASSERT_WITH_CODE 253 drivers/gpu/drm/amd/powerplay/smumgr/fiji_smumgr.c PP_ASSERT_WITH_CODE(0 == smu7_copy_bytes_to_smc(hwmgr, level_addr, PP_ASSERT_WITH_CODE 266 drivers/gpu/drm/amd/powerplay/smumgr/fiji_smumgr.c PP_ASSERT_WITH_CODE(0 == fiji_setup_graphics_level_structure(hwmgr), PP_ASSERT_WITH_CODE 270 drivers/gpu/drm/amd/powerplay/smumgr/fiji_smumgr.c PP_ASSERT_WITH_CODE(0 == smu7_setup_pwr_virus(hwmgr), PP_ASSERT_WITH_CODE 274 drivers/gpu/drm/amd/powerplay/smumgr/fiji_smumgr.c PP_ASSERT_WITH_CODE(0 == fiji_start_avfs_btc(hwmgr), PP_ASSERT_WITH_CODE 509 drivers/gpu/drm/amd/powerplay/smumgr/fiji_smumgr.c PP_ASSERT_WITH_CODE(cac_dtp_table->usTargetOperatingTemp <= 255, PP_ASSERT_WITH_CODE 615 drivers/gpu/drm/amd/powerplay/smumgr/fiji_smumgr.c PP_ASSERT_WITH_CODE(false, PP_ASSERT_WITH_CODE 702 drivers/gpu/drm/amd/powerplay/smumgr/fiji_smumgr.c PP_ASSERT_WITH_CODE(false, PP_ASSERT_WITH_CODE 708 drivers/gpu/drm/amd/powerplay/smumgr/fiji_smumgr.c PP_ASSERT_WITH_CODE(false, PP_ASSERT_WITH_CODE 713 drivers/gpu/drm/amd/powerplay/smumgr/fiji_smumgr.c PP_ASSERT_WITH_CODE(false, PP_ASSERT_WITH_CODE 717 drivers/gpu/drm/amd/powerplay/smumgr/fiji_smumgr.c PP_ASSERT_WITH_CODE(false, PP_ASSERT_WITH_CODE 724 drivers/gpu/drm/amd/powerplay/smumgr/fiji_smumgr.c PP_ASSERT_WITH_CODE(false, PP_ASSERT_WITH_CODE 730 drivers/gpu/drm/amd/powerplay/smumgr/fiji_smumgr.c PP_ASSERT_WITH_CODE(false, PP_ASSERT_WITH_CODE 736 drivers/gpu/drm/amd/powerplay/smumgr/fiji_smumgr.c PP_ASSERT_WITH_CODE(false, PP_ASSERT_WITH_CODE 742 drivers/gpu/drm/amd/powerplay/smumgr/fiji_smumgr.c PP_ASSERT_WITH_CODE(false, PP_ASSERT_WITH_CODE 749 drivers/gpu/drm/amd/powerplay/smumgr/fiji_smumgr.c PP_ASSERT_WITH_CODE(false, PP_ASSERT_WITH_CODE 790 drivers/gpu/drm/amd/powerplay/smumgr/fiji_smumgr.c PP_ASSERT_WITH_CODE(0 == result, PP_ASSERT_WITH_CODE 875 drivers/gpu/drm/amd/powerplay/smumgr/fiji_smumgr.c PP_ASSERT_WITH_CODE(result == 0, PP_ASSERT_WITH_CODE 960 drivers/gpu/drm/amd/powerplay/smumgr/fiji_smumgr.c PP_ASSERT_WITH_CODE((0 == result), PP_ASSERT_WITH_CODE 1051 drivers/gpu/drm/amd/powerplay/smumgr/fiji_smumgr.c PP_ASSERT_WITH_CODE((1 <= pcie_entry_cnt), PP_ASSERT_WITH_CODE 1153 drivers/gpu/drm/amd/powerplay/smumgr/fiji_smumgr.c PP_ASSERT_WITH_CODE((0 == result), PP_ASSERT_WITH_CODE 1184 drivers/gpu/drm/amd/powerplay/smumgr/fiji_smumgr.c PP_ASSERT_WITH_CODE((0 == result), PP_ASSERT_WITH_CODE 1239 drivers/gpu/drm/amd/powerplay/smumgr/fiji_smumgr.c PP_ASSERT_WITH_CODE((0 != dpm_table->mclk_table.dpm_levels[i].value), PP_ASSERT_WITH_CODE 1291 drivers/gpu/drm/amd/powerplay/smumgr/fiji_smumgr.c PP_ASSERT_WITH_CODE(i < table_info->vdd_dep_on_mclk->count, PP_ASSERT_WITH_CODE 1325 drivers/gpu/drm/amd/powerplay/smumgr/fiji_smumgr.c PP_ASSERT_WITH_CODE((0 == result), PP_ASSERT_WITH_CODE 1339 drivers/gpu/drm/amd/powerplay/smumgr/fiji_smumgr.c PP_ASSERT_WITH_CODE(result == 0, PP_ASSERT_WITH_CODE 1383 drivers/gpu/drm/amd/powerplay/smumgr/fiji_smumgr.c PP_ASSERT_WITH_CODE((0 == result), PP_ASSERT_WITH_CODE 1449 drivers/gpu/drm/amd/powerplay/smumgr/fiji_smumgr.c PP_ASSERT_WITH_CODE((0 == result), PP_ASSERT_WITH_CODE 1486 drivers/gpu/drm/amd/powerplay/smumgr/fiji_smumgr.c PP_ASSERT_WITH_CODE((0 == result), PP_ASSERT_WITH_CODE 1509 drivers/gpu/drm/amd/powerplay/smumgr/fiji_smumgr.c PP_ASSERT_WITH_CODE(result == 0, PP_ASSERT_WITH_CODE 1585 drivers/gpu/drm/amd/powerplay/smumgr/fiji_smumgr.c PP_ASSERT_WITH_CODE((0 == result), PP_ASSERT_WITH_CODE 1592 drivers/gpu/drm/amd/powerplay/smumgr/fiji_smumgr.c PP_ASSERT_WITH_CODE((0 == result), PP_ASSERT_WITH_CODE 1738 drivers/gpu/drm/amd/powerplay/smumgr/fiji_smumgr.c PP_ASSERT_WITH_CODE(false, PP_ASSERT_WITH_CODE 1837 drivers/gpu/drm/amd/powerplay/smumgr/fiji_smumgr.c PP_ASSERT_WITH_CODE(false, PP_ASSERT_WITH_CODE 1954 drivers/gpu/drm/amd/powerplay/smumgr/fiji_smumgr.c PP_ASSERT_WITH_CODE(0 == result, PP_ASSERT_WITH_CODE 1961 drivers/gpu/drm/amd/powerplay/smumgr/fiji_smumgr.c PP_ASSERT_WITH_CODE(0 == result, PP_ASSERT_WITH_CODE 1965 drivers/gpu/drm/amd/powerplay/smumgr/fiji_smumgr.c PP_ASSERT_WITH_CODE(0 == result, PP_ASSERT_WITH_CODE 1969 drivers/gpu/drm/amd/powerplay/smumgr/fiji_smumgr.c PP_ASSERT_WITH_CODE(0 == result, PP_ASSERT_WITH_CODE 1973 drivers/gpu/drm/amd/powerplay/smumgr/fiji_smumgr.c PP_ASSERT_WITH_CODE(0 == result, PP_ASSERT_WITH_CODE 1977 drivers/gpu/drm/amd/powerplay/smumgr/fiji_smumgr.c PP_ASSERT_WITH_CODE(0 == result, PP_ASSERT_WITH_CODE 1981 drivers/gpu/drm/amd/powerplay/smumgr/fiji_smumgr.c PP_ASSERT_WITH_CODE(0 == result, PP_ASSERT_WITH_CODE 1989 drivers/gpu/drm/amd/powerplay/smumgr/fiji_smumgr.c PP_ASSERT_WITH_CODE(0 == result, PP_ASSERT_WITH_CODE 1993 drivers/gpu/drm/amd/powerplay/smumgr/fiji_smumgr.c PP_ASSERT_WITH_CODE(0 == result, PP_ASSERT_WITH_CODE 1997 drivers/gpu/drm/amd/powerplay/smumgr/fiji_smumgr.c PP_ASSERT_WITH_CODE(0 == result, PP_ASSERT_WITH_CODE 2001 drivers/gpu/drm/amd/powerplay/smumgr/fiji_smumgr.c PP_ASSERT_WITH_CODE(0 == result, PP_ASSERT_WITH_CODE 2005 drivers/gpu/drm/amd/powerplay/smumgr/fiji_smumgr.c PP_ASSERT_WITH_CODE(0 == result, PP_ASSERT_WITH_CODE 2011 drivers/gpu/drm/amd/powerplay/smumgr/fiji_smumgr.c PP_ASSERT_WITH_CODE(0 == result, PP_ASSERT_WITH_CODE 2037 drivers/gpu/drm/amd/powerplay/smumgr/fiji_smumgr.c PP_ASSERT_WITH_CODE(0 == result, PP_ASSERT_WITH_CODE 2115 drivers/gpu/drm/amd/powerplay/smumgr/fiji_smumgr.c PP_ASSERT_WITH_CODE(0 == result, PP_ASSERT_WITH_CODE 2119 drivers/gpu/drm/amd/powerplay/smumgr/fiji_smumgr.c PP_ASSERT_WITH_CODE(0 == result, PP_ASSERT_WITH_CODE 2123 drivers/gpu/drm/amd/powerplay/smumgr/fiji_smumgr.c PP_ASSERT_WITH_CODE(0 == result, PP_ASSERT_WITH_CODE 2127 drivers/gpu/drm/amd/powerplay/smumgr/fiji_smumgr.c PP_ASSERT_WITH_CODE(0 == result, PP_ASSERT_WITH_CODE 2290 drivers/gpu/drm/amd/powerplay/smumgr/fiji_smumgr.c PP_ASSERT_WITH_CODE((result == 0), PP_ASSERT_WITH_CODE 164 drivers/gpu/drm/amd/powerplay/smumgr/iceland_smumgr.c PP_ASSERT_WITH_CODE((limit >= byte_count), "SMC address is beyond the SMC RAM area.", return -EINVAL); PP_ASSERT_WITH_CODE 178 drivers/gpu/drm/amd/powerplay/smumgr/iceland_smumgr.c PP_ASSERT_WITH_CODE((0 == byte_count), "SMC size must be divisible by 4.", return -EINVAL); PP_ASSERT_WITH_CODE 345 drivers/gpu/drm/amd/powerplay/smumgr/iceland_smumgr.c PP_ASSERT_WITH_CODE(false, PP_ASSERT_WITH_CODE 396 drivers/gpu/drm/amd/powerplay/smumgr/iceland_smumgr.c PP_ASSERT_WITH_CODE(NULL != hwmgr->dyn_state.cac_leakage_table, PP_ASSERT_WITH_CODE 398 drivers/gpu/drm/amd/powerplay/smumgr/iceland_smumgr.c PP_ASSERT_WITH_CODE(hwmgr->dyn_state.cac_leakage_table->count <= 8, PP_ASSERT_WITH_CODE 400 drivers/gpu/drm/amd/powerplay/smumgr/iceland_smumgr.c PP_ASSERT_WITH_CODE(hwmgr->dyn_state.cac_leakage_table->count == hwmgr->dyn_state.vddc_dependency_on_sclk->count, PP_ASSERT_WITH_CODE 409 drivers/gpu/drm/amd/powerplay/smumgr/iceland_smumgr.c PP_ASSERT_WITH_CODE(false, "Iceland should always support EVV", return -EINVAL); PP_ASSERT_WITH_CODE 422 drivers/gpu/drm/amd/powerplay/smumgr/iceland_smumgr.c PP_ASSERT_WITH_CODE(data->vddc_voltage_table.count <= 8, PP_ASSERT_WITH_CODE 446 drivers/gpu/drm/amd/powerplay/smumgr/iceland_smumgr.c PP_ASSERT_WITH_CODE(false, PP_ASSERT_WITH_CODE 452 drivers/gpu/drm/amd/powerplay/smumgr/iceland_smumgr.c PP_ASSERT_WITH_CODE(false, PP_ASSERT_WITH_CODE 458 drivers/gpu/drm/amd/powerplay/smumgr/iceland_smumgr.c PP_ASSERT_WITH_CODE(false, PP_ASSERT_WITH_CODE 464 drivers/gpu/drm/amd/powerplay/smumgr/iceland_smumgr.c PP_ASSERT_WITH_CODE(false, PP_ASSERT_WITH_CODE 469 drivers/gpu/drm/amd/powerplay/smumgr/iceland_smumgr.c PP_ASSERT_WITH_CODE(false, PP_ASSERT_WITH_CODE 473 drivers/gpu/drm/amd/powerplay/smumgr/iceland_smumgr.c PP_ASSERT_WITH_CODE(false, PP_ASSERT_WITH_CODE 480 drivers/gpu/drm/amd/powerplay/smumgr/iceland_smumgr.c PP_ASSERT_WITH_CODE(false, PP_ASSERT_WITH_CODE 486 drivers/gpu/drm/amd/powerplay/smumgr/iceland_smumgr.c PP_ASSERT_WITH_CODE(false, PP_ASSERT_WITH_CODE 492 drivers/gpu/drm/amd/powerplay/smumgr/iceland_smumgr.c PP_ASSERT_WITH_CODE(false, PP_ASSERT_WITH_CODE 499 drivers/gpu/drm/amd/powerplay/smumgr/iceland_smumgr.c PP_ASSERT_WITH_CODE(false, PP_ASSERT_WITH_CODE 540 drivers/gpu/drm/amd/powerplay/smumgr/iceland_smumgr.c PP_ASSERT_WITH_CODE(NULL != hwmgr->dyn_state.vddc_dependency_on_sclk, PP_ASSERT_WITH_CODE 629 drivers/gpu/drm/amd/powerplay/smumgr/iceland_smumgr.c PP_ASSERT_WITH_CODE(0 == result, "do not populate SMC VDDC voltage table", return -EINVAL); PP_ASSERT_WITH_CODE 656 drivers/gpu/drm/amd/powerplay/smumgr/iceland_smumgr.c PP_ASSERT_WITH_CODE(result == 0, "do not populate SMC VDDCI voltage table", return -EINVAL); PP_ASSERT_WITH_CODE 681 drivers/gpu/drm/amd/powerplay/smumgr/iceland_smumgr.c PP_ASSERT_WITH_CODE(result == 0, "do not populate SMC mvdd voltage table", return -EINVAL); PP_ASSERT_WITH_CODE 700 drivers/gpu/drm/amd/powerplay/smumgr/iceland_smumgr.c PP_ASSERT_WITH_CODE(0 == result, PP_ASSERT_WITH_CODE 704 drivers/gpu/drm/amd/powerplay/smumgr/iceland_smumgr.c PP_ASSERT_WITH_CODE(0 == result, PP_ASSERT_WITH_CODE 708 drivers/gpu/drm/amd/powerplay/smumgr/iceland_smumgr.c PP_ASSERT_WITH_CODE(0 == result, PP_ASSERT_WITH_CODE 725 drivers/gpu/drm/amd/powerplay/smumgr/iceland_smumgr.c PP_ASSERT_WITH_CODE((0 == result), "can not get ULV voltage value", return result;); PP_ASSERT_WITH_CODE 813 drivers/gpu/drm/amd/powerplay/smumgr/iceland_smumgr.c PP_ASSERT_WITH_CODE(result == 0, PP_ASSERT_WITH_CODE 904 drivers/gpu/drm/amd/powerplay/smumgr/iceland_smumgr.c PP_ASSERT_WITH_CODE((0 == result), PP_ASSERT_WITH_CODE 1069 drivers/gpu/drm/amd/powerplay/smumgr/iceland_smumgr.c PP_ASSERT_WITH_CODE(0 == result, PP_ASSERT_WITH_CODE 1243 drivers/gpu/drm/amd/powerplay/smumgr/iceland_smumgr.c PP_ASSERT_WITH_CODE((0 == result), PP_ASSERT_WITH_CODE 1254 drivers/gpu/drm/amd/powerplay/smumgr/iceland_smumgr.c PP_ASSERT_WITH_CODE((0 == result), PP_ASSERT_WITH_CODE 1362 drivers/gpu/drm/amd/powerplay/smumgr/iceland_smumgr.c PP_ASSERT_WITH_CODE((0 != dpm_table->mclk_table.dpm_levels[i].value), PP_ASSERT_WITH_CODE 1412 drivers/gpu/drm/amd/powerplay/smumgr/iceland_smumgr.c PP_ASSERT_WITH_CODE(i < hwmgr->dyn_state.mvdd_dependency_on_mclk->count, PP_ASSERT_WITH_CODE 1453 drivers/gpu/drm/amd/powerplay/smumgr/iceland_smumgr.c PP_ASSERT_WITH_CODE(result == 0, PP_ASSERT_WITH_CODE 1597 drivers/gpu/drm/amd/powerplay/smumgr/iceland_smumgr.c PP_ASSERT_WITH_CODE(result == 0, PP_ASSERT_WITH_CODE 1697 drivers/gpu/drm/amd/powerplay/smumgr/iceland_smumgr.c PP_ASSERT_WITH_CODE(i < SMU71_DISCRETE_MC_REGISTER_ARRAY_SIZE, PP_ASSERT_WITH_CODE 1809 drivers/gpu/drm/amd/powerplay/smumgr/iceland_smumgr.c PP_ASSERT_WITH_CODE(0 == result, PP_ASSERT_WITH_CODE 1813 drivers/gpu/drm/amd/powerplay/smumgr/iceland_smumgr.c PP_ASSERT_WITH_CODE(0 == result, PP_ASSERT_WITH_CODE 1923 drivers/gpu/drm/amd/powerplay/smumgr/iceland_smumgr.c PP_ASSERT_WITH_CODE(tab->SVI2Enable != (VDDC_ON_SVI2 | VDDCI_ON_SVI2 | MVDD_ON_SVI2) && PP_ASSERT_WITH_CODE 1959 drivers/gpu/drm/amd/powerplay/smumgr/iceland_smumgr.c PP_ASSERT_WITH_CODE(0 == result, PP_ASSERT_WITH_CODE 1967 drivers/gpu/drm/amd/powerplay/smumgr/iceland_smumgr.c PP_ASSERT_WITH_CODE(0 == result, PP_ASSERT_WITH_CODE 1971 drivers/gpu/drm/amd/powerplay/smumgr/iceland_smumgr.c PP_ASSERT_WITH_CODE(0 == result, PP_ASSERT_WITH_CODE 1975 drivers/gpu/drm/amd/powerplay/smumgr/iceland_smumgr.c PP_ASSERT_WITH_CODE(0 == result, PP_ASSERT_WITH_CODE 1979 drivers/gpu/drm/amd/powerplay/smumgr/iceland_smumgr.c PP_ASSERT_WITH_CODE(0 == result, PP_ASSERT_WITH_CODE 1983 drivers/gpu/drm/amd/powerplay/smumgr/iceland_smumgr.c PP_ASSERT_WITH_CODE(0 == result, PP_ASSERT_WITH_CODE 1987 drivers/gpu/drm/amd/powerplay/smumgr/iceland_smumgr.c PP_ASSERT_WITH_CODE(0 == result, PP_ASSERT_WITH_CODE 1993 drivers/gpu/drm/amd/powerplay/smumgr/iceland_smumgr.c PP_ASSERT_WITH_CODE(0 == result, PP_ASSERT_WITH_CODE 1997 drivers/gpu/drm/amd/powerplay/smumgr/iceland_smumgr.c PP_ASSERT_WITH_CODE(0 == result, PP_ASSERT_WITH_CODE 2004 drivers/gpu/drm/amd/powerplay/smumgr/iceland_smumgr.c PP_ASSERT_WITH_CODE(0 == result, PP_ASSERT_WITH_CODE 2008 drivers/gpu/drm/amd/powerplay/smumgr/iceland_smumgr.c PP_ASSERT_WITH_CODE(0 == result, "Failed to initialize Boot State!", return result); PP_ASSERT_WITH_CODE 2011 drivers/gpu/drm/amd/powerplay/smumgr/iceland_smumgr.c PP_ASSERT_WITH_CODE(0 == result, "Failed to populate BAPM Parameters!", return result); PP_ASSERT_WITH_CODE 2035 drivers/gpu/drm/amd/powerplay/smumgr/iceland_smumgr.c PP_ASSERT_WITH_CODE(0 == result, PP_ASSERT_WITH_CODE 2063 drivers/gpu/drm/amd/powerplay/smumgr/iceland_smumgr.c PP_ASSERT_WITH_CODE(0 == result, PP_ASSERT_WITH_CODE 2075 drivers/gpu/drm/amd/powerplay/smumgr/iceland_smumgr.c PP_ASSERT_WITH_CODE((0 == result), PP_ASSERT_WITH_CODE 2079 drivers/gpu/drm/amd/powerplay/smumgr/iceland_smumgr.c PP_ASSERT_WITH_CODE(0 == result, PP_ASSERT_WITH_CODE 2202 drivers/gpu/drm/amd/powerplay/smumgr/iceland_smumgr.c PP_ASSERT_WITH_CODE((0 == result), "Failed to upload MC reg table!", return result); PP_ASSERT_WITH_CODE 2205 drivers/gpu/drm/amd/powerplay/smumgr/iceland_smumgr.c PP_ASSERT_WITH_CODE((result == 0), PP_ASSERT_WITH_CODE 2485 drivers/gpu/drm/amd/powerplay/smumgr/iceland_smumgr.c PP_ASSERT_WITH_CODE((table->last <= SMU71_DISCRETE_MC_REGISTER_ARRAY_SIZE), PP_ASSERT_WITH_CODE 2487 drivers/gpu/drm/amd/powerplay/smumgr/iceland_smumgr.c PP_ASSERT_WITH_CODE((table->num_entries <= MAX_AC_TIMING_ENTRIES), PP_ASSERT_WITH_CODE 2517 drivers/gpu/drm/amd/powerplay/smumgr/iceland_smumgr.c PP_ASSERT_WITH_CODE((j < SMU71_DISCRETE_MC_REGISTER_ARRAY_SIZE), PP_ASSERT_WITH_CODE 2533 drivers/gpu/drm/amd/powerplay/smumgr/iceland_smumgr.c PP_ASSERT_WITH_CODE((j < SMU71_DISCRETE_MC_REGISTER_ARRAY_SIZE), PP_ASSERT_WITH_CODE 2550 drivers/gpu/drm/amd/powerplay/smumgr/iceland_smumgr.c PP_ASSERT_WITH_CODE((j < SMU71_DISCRETE_MC_REGISTER_ARRAY_SIZE), PP_ASSERT_WITH_CODE 130 drivers/gpu/drm/amd/powerplay/smumgr/polaris10_smumgr.c PP_ASSERT_WITH_CODE(0 == smu7_read_smc_sram_dword(hwmgr, PP_ASSERT_WITH_CODE 141 drivers/gpu/drm/amd/powerplay/smumgr/polaris10_smumgr.c PP_ASSERT_WITH_CODE(0 == smu7_copy_bytes_to_smc(hwmgr, vr_config_address, PP_ASSERT_WITH_CODE 148 drivers/gpu/drm/amd/powerplay/smumgr/polaris10_smumgr.c PP_ASSERT_WITH_CODE(0 == smu7_copy_bytes_to_smc(hwmgr, graphics_level_address, PP_ASSERT_WITH_CODE 156 drivers/gpu/drm/amd/powerplay/smumgr/polaris10_smumgr.c PP_ASSERT_WITH_CODE(0 == smu7_copy_bytes_to_smc(hwmgr, graphics_level_address, PP_ASSERT_WITH_CODE 165 drivers/gpu/drm/amd/powerplay/smumgr/polaris10_smumgr.c PP_ASSERT_WITH_CODE(0 == smu7_copy_bytes_to_smc(hwmgr, graphics_level_address, PP_ASSERT_WITH_CODE 181 drivers/gpu/drm/amd/powerplay/smumgr/polaris10_smumgr.c PP_ASSERT_WITH_CODE(0 == polaris10_setup_graphics_level_structure(hwmgr), PP_ASSERT_WITH_CODE 187 drivers/gpu/drm/amd/powerplay/smumgr/polaris10_smumgr.c PP_ASSERT_WITH_CODE(0 == smu7_setup_pwr_virus(hwmgr), PP_ASSERT_WITH_CODE 192 drivers/gpu/drm/amd/powerplay/smumgr/polaris10_smumgr.c PP_ASSERT_WITH_CODE(0 == polaris10_perform_btc(hwmgr), PP_ASSERT_WITH_CODE 238 drivers/gpu/drm/amd/powerplay/smumgr/polaris10_smumgr.c PP_ASSERT_WITH_CODE(false, "SMU Firmware start failed!", return -1); PP_ASSERT_WITH_CODE 308 drivers/gpu/drm/amd/powerplay/smumgr/polaris10_smumgr.c PP_ASSERT_WITH_CODE(0, "Failed to load SMU ucode.", return result); PP_ASSERT_WITH_CODE 442 drivers/gpu/drm/amd/powerplay/smumgr/polaris10_smumgr.c PP_ASSERT_WITH_CODE(cac_dtp_table->usTargetOperatingTemp <= 255, PP_ASSERT_WITH_CODE 513 drivers/gpu/drm/amd/powerplay/smumgr/polaris10_smumgr.c PP_ASSERT_WITH_CODE(false, PP_ASSERT_WITH_CODE 597 drivers/gpu/drm/amd/powerplay/smumgr/polaris10_smumgr.c PP_ASSERT_WITH_CODE(false, PP_ASSERT_WITH_CODE 602 drivers/gpu/drm/amd/powerplay/smumgr/polaris10_smumgr.c PP_ASSERT_WITH_CODE(false, PP_ASSERT_WITH_CODE 607 drivers/gpu/drm/amd/powerplay/smumgr/polaris10_smumgr.c PP_ASSERT_WITH_CODE(false, PP_ASSERT_WITH_CODE 611 drivers/gpu/drm/amd/powerplay/smumgr/polaris10_smumgr.c PP_ASSERT_WITH_CODE(false, PP_ASSERT_WITH_CODE 617 drivers/gpu/drm/amd/powerplay/smumgr/polaris10_smumgr.c PP_ASSERT_WITH_CODE(false, PP_ASSERT_WITH_CODE 622 drivers/gpu/drm/amd/powerplay/smumgr/polaris10_smumgr.c PP_ASSERT_WITH_CODE(false, PP_ASSERT_WITH_CODE 627 drivers/gpu/drm/amd/powerplay/smumgr/polaris10_smumgr.c PP_ASSERT_WITH_CODE(false, PP_ASSERT_WITH_CODE 632 drivers/gpu/drm/amd/powerplay/smumgr/polaris10_smumgr.c PP_ASSERT_WITH_CODE(false, PP_ASSERT_WITH_CODE 639 drivers/gpu/drm/amd/powerplay/smumgr/polaris10_smumgr.c PP_ASSERT_WITH_CODE(false, PP_ASSERT_WITH_CODE 930 drivers/gpu/drm/amd/powerplay/smumgr/polaris10_smumgr.c PP_ASSERT_WITH_CODE((0 == result), PP_ASSERT_WITH_CODE 1025 drivers/gpu/drm/amd/powerplay/smumgr/polaris10_smumgr.c PP_ASSERT_WITH_CODE((1 <= pcie_entry_cnt), PP_ASSERT_WITH_CODE 1091 drivers/gpu/drm/amd/powerplay/smumgr/polaris10_smumgr.c PP_ASSERT_WITH_CODE((0 == result), PP_ASSERT_WITH_CODE 1140 drivers/gpu/drm/amd/powerplay/smumgr/polaris10_smumgr.c PP_ASSERT_WITH_CODE((0 != dpm_table->mclk_table.dpm_levels[i].value), PP_ASSERT_WITH_CODE 1190 drivers/gpu/drm/amd/powerplay/smumgr/polaris10_smumgr.c PP_ASSERT_WITH_CODE(i < table_info->vdd_dep_on_mclk->count, PP_ASSERT_WITH_CODE 1219 drivers/gpu/drm/amd/powerplay/smumgr/polaris10_smumgr.c PP_ASSERT_WITH_CODE((0 == result), PP_ASSERT_WITH_CODE 1225 drivers/gpu/drm/amd/powerplay/smumgr/polaris10_smumgr.c PP_ASSERT_WITH_CODE(result == 0, "Error retrieving Engine Clock dividers from VBIOS.", return result); PP_ASSERT_WITH_CODE 1254 drivers/gpu/drm/amd/powerplay/smumgr/polaris10_smumgr.c PP_ASSERT_WITH_CODE((0 == result), PP_ASSERT_WITH_CODE 1324 drivers/gpu/drm/amd/powerplay/smumgr/polaris10_smumgr.c PP_ASSERT_WITH_CODE((0 == result), PP_ASSERT_WITH_CODE 1347 drivers/gpu/drm/amd/powerplay/smumgr/polaris10_smumgr.c PP_ASSERT_WITH_CODE(result == 0, PP_ASSERT_WITH_CODE 1429 drivers/gpu/drm/amd/powerplay/smumgr/polaris10_smumgr.c PP_ASSERT_WITH_CODE((0 == result), PP_ASSERT_WITH_CODE 1436 drivers/gpu/drm/amd/powerplay/smumgr/polaris10_smumgr.c PP_ASSERT_WITH_CODE((0 == result), PP_ASSERT_WITH_CODE 1583 drivers/gpu/drm/amd/powerplay/smumgr/polaris10_smumgr.c PP_ASSERT_WITH_CODE(false, PP_ASSERT_WITH_CODE 1610 drivers/gpu/drm/amd/powerplay/smumgr/polaris10_smumgr.c PP_ASSERT_WITH_CODE(false, PP_ASSERT_WITH_CODE 1852 drivers/gpu/drm/amd/powerplay/smumgr/polaris10_smumgr.c PP_ASSERT_WITH_CODE(0 == result, PP_ASSERT_WITH_CODE 1859 drivers/gpu/drm/amd/powerplay/smumgr/polaris10_smumgr.c PP_ASSERT_WITH_CODE(0 == result, PP_ASSERT_WITH_CODE 1863 drivers/gpu/drm/amd/powerplay/smumgr/polaris10_smumgr.c PP_ASSERT_WITH_CODE(0 == result, PP_ASSERT_WITH_CODE 1867 drivers/gpu/drm/amd/powerplay/smumgr/polaris10_smumgr.c PP_ASSERT_WITH_CODE(0 == result, PP_ASSERT_WITH_CODE 1871 drivers/gpu/drm/amd/powerplay/smumgr/polaris10_smumgr.c PP_ASSERT_WITH_CODE(0 == result, PP_ASSERT_WITH_CODE 1875 drivers/gpu/drm/amd/powerplay/smumgr/polaris10_smumgr.c PP_ASSERT_WITH_CODE(0 == result, PP_ASSERT_WITH_CODE 1883 drivers/gpu/drm/amd/powerplay/smumgr/polaris10_smumgr.c PP_ASSERT_WITH_CODE(0 == result, PP_ASSERT_WITH_CODE 1887 drivers/gpu/drm/amd/powerplay/smumgr/polaris10_smumgr.c PP_ASSERT_WITH_CODE(0 == result, PP_ASSERT_WITH_CODE 1891 drivers/gpu/drm/amd/powerplay/smumgr/polaris10_smumgr.c PP_ASSERT_WITH_CODE(0 == result, PP_ASSERT_WITH_CODE 1895 drivers/gpu/drm/amd/powerplay/smumgr/polaris10_smumgr.c PP_ASSERT_WITH_CODE(0 == result, PP_ASSERT_WITH_CODE 1899 drivers/gpu/drm/amd/powerplay/smumgr/polaris10_smumgr.c PP_ASSERT_WITH_CODE(0 == result, PP_ASSERT_WITH_CODE 1905 drivers/gpu/drm/amd/powerplay/smumgr/polaris10_smumgr.c PP_ASSERT_WITH_CODE(0 == result, PP_ASSERT_WITH_CODE 1911 drivers/gpu/drm/amd/powerplay/smumgr/polaris10_smumgr.c PP_ASSERT_WITH_CODE(0 == result, "Failed to populate AVFS Parameters!", return result;); PP_ASSERT_WITH_CODE 1935 drivers/gpu/drm/amd/powerplay/smumgr/polaris10_smumgr.c PP_ASSERT_WITH_CODE(0 == result, PP_ASSERT_WITH_CODE 1990 drivers/gpu/drm/amd/powerplay/smumgr/polaris10_smumgr.c PP_ASSERT_WITH_CODE((result == 0), "Can not find DFS divide id for Sclk", return result); PP_ASSERT_WITH_CODE 2019 drivers/gpu/drm/amd/powerplay/smumgr/polaris10_smumgr.c PP_ASSERT_WITH_CODE(0 == result, PP_ASSERT_WITH_CODE 2023 drivers/gpu/drm/amd/powerplay/smumgr/polaris10_smumgr.c PP_ASSERT_WITH_CODE(0 == result, PP_ASSERT_WITH_CODE 2027 drivers/gpu/drm/amd/powerplay/smumgr/polaris10_smumgr.c PP_ASSERT_WITH_CODE(0 == result, PP_ASSERT_WITH_CODE 2300 drivers/gpu/drm/amd/powerplay/smumgr/polaris10_smumgr.c PP_ASSERT_WITH_CODE((result == 0), PP_ASSERT_WITH_CODE 2304 drivers/gpu/drm/amd/powerplay/smumgr/polaris10_smumgr.c PP_ASSERT_WITH_CODE((result == 0), PP_ASSERT_WITH_CODE 123 drivers/gpu/drm/amd/powerplay/smumgr/smu10_smumgr.c PP_ASSERT_WITH_CODE(table_id < MAX_SMU_TABLE, PP_ASSERT_WITH_CODE 125 drivers/gpu/drm/amd/powerplay/smumgr/smu10_smumgr.c PP_ASSERT_WITH_CODE(priv->smu_tables.entry[table_id].version != 0, PP_ASSERT_WITH_CODE 127 drivers/gpu/drm/amd/powerplay/smumgr/smu10_smumgr.c PP_ASSERT_WITH_CODE(priv->smu_tables.entry[table_id].size != 0, PP_ASSERT_WITH_CODE 154 drivers/gpu/drm/amd/powerplay/smumgr/smu10_smumgr.c PP_ASSERT_WITH_CODE(table_id < MAX_SMU_TABLE, PP_ASSERT_WITH_CODE 156 drivers/gpu/drm/amd/powerplay/smumgr/smu10_smumgr.c PP_ASSERT_WITH_CODE(priv->smu_tables.entry[table_id].version != 0, PP_ASSERT_WITH_CODE 158 drivers/gpu/drm/amd/powerplay/smumgr/smu10_smumgr.c PP_ASSERT_WITH_CODE(priv->smu_tables.entry[table_id].size != 0, PP_ASSERT_WITH_CODE 40 drivers/gpu/drm/amd/powerplay/smumgr/smu7_smumgr.c PP_ASSERT_WITH_CODE((0 == (3 & smc_addr)), "SMC address must be 4 byte aligned.", return -EINVAL); PP_ASSERT_WITH_CODE 41 drivers/gpu/drm/amd/powerplay/smumgr/smu7_smumgr.c PP_ASSERT_WITH_CODE((limit > (smc_addr + 3)), "SMC addr is beyond the SMC RAM area.", return -EINVAL); PP_ASSERT_WITH_CODE 57 drivers/gpu/drm/amd/powerplay/smumgr/smu7_smumgr.c PP_ASSERT_WITH_CODE((0 == (3 & smc_start_address)), "SMC address must be 4 byte aligned.", return -EINVAL); PP_ASSERT_WITH_CODE 58 drivers/gpu/drm/amd/powerplay/smumgr/smu7_smumgr.c PP_ASSERT_WITH_CODE((limit > (smc_start_address + byte_count)), "SMC address is beyond the SMC RAM area.", return -EINVAL); PP_ASSERT_WITH_CODE 94 drivers/gpu/drm/amd/powerplay/smumgr/smu7_smumgr.c PP_ASSERT_WITH_CODE((0 == (3 & smc_start_address)), "SMC address must be 4 byte aligned.", return -EINVAL); PP_ASSERT_WITH_CODE 95 drivers/gpu/drm/amd/powerplay/smumgr/smu7_smumgr.c PP_ASSERT_WITH_CODE((limit > (smc_start_address + byte_count)), "SMC address is beyond the SMC RAM area.", return -EINVAL); PP_ASSERT_WITH_CODE 392 drivers/gpu/drm/amd/powerplay/smumgr/smu7_smumgr.c PP_ASSERT_WITH_CODE(0 == smu7_populate_single_firmware_entry(hwmgr, PP_ASSERT_WITH_CODE 395 drivers/gpu/drm/amd/powerplay/smumgr/smu7_smumgr.c PP_ASSERT_WITH_CODE(0 == smu7_populate_single_firmware_entry(hwmgr, PP_ASSERT_WITH_CODE 398 drivers/gpu/drm/amd/powerplay/smumgr/smu7_smumgr.c PP_ASSERT_WITH_CODE(0 == smu7_populate_single_firmware_entry(hwmgr, PP_ASSERT_WITH_CODE 401 drivers/gpu/drm/amd/powerplay/smumgr/smu7_smumgr.c PP_ASSERT_WITH_CODE(0 == smu7_populate_single_firmware_entry(hwmgr, PP_ASSERT_WITH_CODE 404 drivers/gpu/drm/amd/powerplay/smumgr/smu7_smumgr.c PP_ASSERT_WITH_CODE(0 == smu7_populate_single_firmware_entry(hwmgr, PP_ASSERT_WITH_CODE 407 drivers/gpu/drm/amd/powerplay/smumgr/smu7_smumgr.c PP_ASSERT_WITH_CODE(0 == smu7_populate_single_firmware_entry(hwmgr, PP_ASSERT_WITH_CODE 410 drivers/gpu/drm/amd/powerplay/smumgr/smu7_smumgr.c PP_ASSERT_WITH_CODE(0 == smu7_populate_single_firmware_entry(hwmgr, PP_ASSERT_WITH_CODE 413 drivers/gpu/drm/amd/powerplay/smumgr/smu7_smumgr.c PP_ASSERT_WITH_CODE(0 == smu7_populate_single_firmware_entry(hwmgr, PP_ASSERT_WITH_CODE 416 drivers/gpu/drm/amd/powerplay/smumgr/smu7_smumgr.c PP_ASSERT_WITH_CODE(0 == smu7_populate_single_firmware_entry(hwmgr, PP_ASSERT_WITH_CODE 420 drivers/gpu/drm/amd/powerplay/smumgr/smu7_smumgr.c PP_ASSERT_WITH_CODE(0 == smu7_populate_single_firmware_entry(hwmgr, PP_ASSERT_WITH_CODE 465 drivers/gpu/drm/amd/powerplay/smumgr/smu7_smumgr.c PP_ASSERT_WITH_CODE((limit >= byte_count), "SMC address is beyond the SMC RAM area.", return -EINVAL); PP_ASSERT_WITH_CODE 475 drivers/gpu/drm/amd/powerplay/smumgr/smu7_smumgr.c PP_ASSERT_WITH_CODE((0 == byte_count), "SMC size must be divisible by 4.", return -EINVAL); PP_ASSERT_WITH_CODE 452 drivers/gpu/drm/amd/powerplay/smumgr/tonga_smumgr.c PP_ASSERT_WITH_CODE(!result, PP_ASSERT_WITH_CODE 457 drivers/gpu/drm/amd/powerplay/smumgr/tonga_smumgr.c PP_ASSERT_WITH_CODE(!result, PP_ASSERT_WITH_CODE 462 drivers/gpu/drm/amd/powerplay/smumgr/tonga_smumgr.c PP_ASSERT_WITH_CODE(!result, PP_ASSERT_WITH_CODE 467 drivers/gpu/drm/amd/powerplay/smumgr/tonga_smumgr.c PP_ASSERT_WITH_CODE(!result, PP_ASSERT_WITH_CODE 472 drivers/gpu/drm/amd/powerplay/smumgr/tonga_smumgr.c PP_ASSERT_WITH_CODE(!result, PP_ASSERT_WITH_CODE 556 drivers/gpu/drm/amd/powerplay/smumgr/tonga_smumgr.c PP_ASSERT_WITH_CODE(result == 0, PP_ASSERT_WITH_CODE 638 drivers/gpu/drm/amd/powerplay/smumgr/tonga_smumgr.c PP_ASSERT_WITH_CODE((!result), PP_ASSERT_WITH_CODE 736 drivers/gpu/drm/amd/powerplay/smumgr/tonga_smumgr.c PP_ASSERT_WITH_CODE((pcie_entry_count >= 1), PP_ASSERT_WITH_CODE 812 drivers/gpu/drm/amd/powerplay/smumgr/tonga_smumgr.c PP_ASSERT_WITH_CODE( PP_ASSERT_WITH_CODE 987 drivers/gpu/drm/amd/powerplay/smumgr/tonga_smumgr.c PP_ASSERT_WITH_CODE( PP_ASSERT_WITH_CODE 1108 drivers/gpu/drm/amd/powerplay/smumgr/tonga_smumgr.c PP_ASSERT_WITH_CODE((0 != dpm_table->mclk_table.dpm_levels[i].value), PP_ASSERT_WITH_CODE 1162 drivers/gpu/drm/amd/powerplay/smumgr/tonga_smumgr.c PP_ASSERT_WITH_CODE(i < table_info->vdd_dep_on_mclk->count, PP_ASSERT_WITH_CODE 1201 drivers/gpu/drm/amd/powerplay/smumgr/tonga_smumgr.c PP_ASSERT_WITH_CODE(result == 0, PP_ASSERT_WITH_CODE 1344 drivers/gpu/drm/amd/powerplay/smumgr/tonga_smumgr.c PP_ASSERT_WITH_CODE((!result), PP_ASSERT_WITH_CODE 1352 drivers/gpu/drm/amd/powerplay/smumgr/tonga_smumgr.c PP_ASSERT_WITH_CODE((!result), PP_ASSERT_WITH_CODE 1401 drivers/gpu/drm/amd/powerplay/smumgr/tonga_smumgr.c PP_ASSERT_WITH_CODE((!result), PP_ASSERT_WITH_CODE 1446 drivers/gpu/drm/amd/powerplay/smumgr/tonga_smumgr.c PP_ASSERT_WITH_CODE((!result), PP_ASSERT_WITH_CODE 1472 drivers/gpu/drm/amd/powerplay/smumgr/tonga_smumgr.c PP_ASSERT_WITH_CODE(result == 0, PP_ASSERT_WITH_CODE 1661 drivers/gpu/drm/amd/powerplay/smumgr/tonga_smumgr.c PP_ASSERT_WITH_CODE(false, PP_ASSERT_WITH_CODE 1843 drivers/gpu/drm/amd/powerplay/smumgr/tonga_smumgr.c PP_ASSERT_WITH_CODE(cac_dtp_table->usTargetOperatingTemp <= 255, PP_ASSERT_WITH_CODE 1920 drivers/gpu/drm/amd/powerplay/smumgr/tonga_smumgr.c PP_ASSERT_WITH_CODE(false, PP_ASSERT_WITH_CODE 2006 drivers/gpu/drm/amd/powerplay/smumgr/tonga_smumgr.c PP_ASSERT_WITH_CODE(false, PP_ASSERT_WITH_CODE 2012 drivers/gpu/drm/amd/powerplay/smumgr/tonga_smumgr.c PP_ASSERT_WITH_CODE(false, PP_ASSERT_WITH_CODE 2017 drivers/gpu/drm/amd/powerplay/smumgr/tonga_smumgr.c PP_ASSERT_WITH_CODE(false, PP_ASSERT_WITH_CODE 2022 drivers/gpu/drm/amd/powerplay/smumgr/tonga_smumgr.c PP_ASSERT_WITH_CODE(false, PP_ASSERT_WITH_CODE 2028 drivers/gpu/drm/amd/powerplay/smumgr/tonga_smumgr.c PP_ASSERT_WITH_CODE(false, PP_ASSERT_WITH_CODE 2034 drivers/gpu/drm/amd/powerplay/smumgr/tonga_smumgr.c PP_ASSERT_WITH_CODE(false, PP_ASSERT_WITH_CODE 2041 drivers/gpu/drm/amd/powerplay/smumgr/tonga_smumgr.c PP_ASSERT_WITH_CODE(false, PP_ASSERT_WITH_CODE 2047 drivers/gpu/drm/amd/powerplay/smumgr/tonga_smumgr.c PP_ASSERT_WITH_CODE( PP_ASSERT_WITH_CODE 2056 drivers/gpu/drm/amd/powerplay/smumgr/tonga_smumgr.c PP_ASSERT_WITH_CODE(false, PP_ASSERT_WITH_CODE 2072 drivers/gpu/drm/amd/powerplay/smumgr/tonga_smumgr.c PP_ASSERT_WITH_CODE( PP_ASSERT_WITH_CODE 2191 drivers/gpu/drm/amd/powerplay/smumgr/tonga_smumgr.c PP_ASSERT_WITH_CODE(!result, PP_ASSERT_WITH_CODE 2196 drivers/gpu/drm/amd/powerplay/smumgr/tonga_smumgr.c PP_ASSERT_WITH_CODE(!result, PP_ASSERT_WITH_CODE 2260 drivers/gpu/drm/amd/powerplay/smumgr/tonga_smumgr.c PP_ASSERT_WITH_CODE(!result, PP_ASSERT_WITH_CODE 2269 drivers/gpu/drm/amd/powerplay/smumgr/tonga_smumgr.c PP_ASSERT_WITH_CODE(!result, PP_ASSERT_WITH_CODE 2273 drivers/gpu/drm/amd/powerplay/smumgr/tonga_smumgr.c PP_ASSERT_WITH_CODE(!result, PP_ASSERT_WITH_CODE 2277 drivers/gpu/drm/amd/powerplay/smumgr/tonga_smumgr.c PP_ASSERT_WITH_CODE(!result, PP_ASSERT_WITH_CODE 2281 drivers/gpu/drm/amd/powerplay/smumgr/tonga_smumgr.c PP_ASSERT_WITH_CODE(!result, PP_ASSERT_WITH_CODE 2285 drivers/gpu/drm/amd/powerplay/smumgr/tonga_smumgr.c PP_ASSERT_WITH_CODE(!result, PP_ASSERT_WITH_CODE 2289 drivers/gpu/drm/amd/powerplay/smumgr/tonga_smumgr.c PP_ASSERT_WITH_CODE(!result, PP_ASSERT_WITH_CODE 2297 drivers/gpu/drm/amd/powerplay/smumgr/tonga_smumgr.c PP_ASSERT_WITH_CODE(!result, PP_ASSERT_WITH_CODE 2302 drivers/gpu/drm/amd/powerplay/smumgr/tonga_smumgr.c PP_ASSERT_WITH_CODE(!result, PP_ASSERT_WITH_CODE 2306 drivers/gpu/drm/amd/powerplay/smumgr/tonga_smumgr.c PP_ASSERT_WITH_CODE(!result, PP_ASSERT_WITH_CODE 2310 drivers/gpu/drm/amd/powerplay/smumgr/tonga_smumgr.c PP_ASSERT_WITH_CODE(!result, PP_ASSERT_WITH_CODE 2316 drivers/gpu/drm/amd/powerplay/smumgr/tonga_smumgr.c PP_ASSERT_WITH_CODE(!result, PP_ASSERT_WITH_CODE 2346 drivers/gpu/drm/amd/powerplay/smumgr/tonga_smumgr.c PP_ASSERT_WITH_CODE((1 <= data->dpm_table.pcie_speed_table.count), PP_ASSERT_WITH_CODE 2355 drivers/gpu/drm/amd/powerplay/smumgr/tonga_smumgr.c PP_ASSERT_WITH_CODE(!result, PP_ASSERT_WITH_CODE 2442 drivers/gpu/drm/amd/powerplay/smumgr/tonga_smumgr.c PP_ASSERT_WITH_CODE(!result, PP_ASSERT_WITH_CODE 2446 drivers/gpu/drm/amd/powerplay/smumgr/tonga_smumgr.c PP_ASSERT_WITH_CODE(!result, PP_ASSERT_WITH_CODE 2450 drivers/gpu/drm/amd/powerplay/smumgr/tonga_smumgr.c PP_ASSERT_WITH_CODE((!result), PP_ASSERT_WITH_CODE 2454 drivers/gpu/drm/amd/powerplay/smumgr/tonga_smumgr.c PP_ASSERT_WITH_CODE((!result), PP_ASSERT_WITH_CODE 2592 drivers/gpu/drm/amd/powerplay/smumgr/tonga_smumgr.c PP_ASSERT_WITH_CODE((!result), PP_ASSERT_WITH_CODE 2597 drivers/gpu/drm/amd/powerplay/smumgr/tonga_smumgr.c PP_ASSERT_WITH_CODE((result == 0), PP_ASSERT_WITH_CODE 2948 drivers/gpu/drm/amd/powerplay/smumgr/tonga_smumgr.c PP_ASSERT_WITH_CODE((table->last <= SMU72_DISCRETE_MC_REGISTER_ARRAY_SIZE), PP_ASSERT_WITH_CODE 2950 drivers/gpu/drm/amd/powerplay/smumgr/tonga_smumgr.c PP_ASSERT_WITH_CODE((table->num_entries <= MAX_AC_TIMING_ENTRIES), PP_ASSERT_WITH_CODE 2980 drivers/gpu/drm/amd/powerplay/smumgr/tonga_smumgr.c PP_ASSERT_WITH_CODE((j < SMU72_DISCRETE_MC_REGISTER_ARRAY_SIZE), PP_ASSERT_WITH_CODE 2997 drivers/gpu/drm/amd/powerplay/smumgr/tonga_smumgr.c PP_ASSERT_WITH_CODE((j < SMU72_DISCRETE_MC_REGISTER_ARRAY_SIZE), PP_ASSERT_WITH_CODE 3013 drivers/gpu/drm/amd/powerplay/smumgr/tonga_smumgr.c PP_ASSERT_WITH_CODE((j < SMU72_DISCRETE_MC_REGISTER_ARRAY_SIZE), PP_ASSERT_WITH_CODE 44 drivers/gpu/drm/amd/powerplay/smumgr/vega10_smumgr.c PP_ASSERT_WITH_CODE(table_id < MAX_SMU_TABLE, PP_ASSERT_WITH_CODE 46 drivers/gpu/drm/amd/powerplay/smumgr/vega10_smumgr.c PP_ASSERT_WITH_CODE(priv->smu_tables.entry[table_id].version != 0, PP_ASSERT_WITH_CODE 48 drivers/gpu/drm/amd/powerplay/smumgr/vega10_smumgr.c PP_ASSERT_WITH_CODE(priv->smu_tables.entry[table_id].size != 0, PP_ASSERT_WITH_CODE 74 drivers/gpu/drm/amd/powerplay/smumgr/vega10_smumgr.c PP_ASSERT_WITH_CODE(table_id < MAX_SMU_TABLE, PP_ASSERT_WITH_CODE 76 drivers/gpu/drm/amd/powerplay/smumgr/vega10_smumgr.c PP_ASSERT_WITH_CODE(priv->smu_tables.entry[table_id].version != 0, PP_ASSERT_WITH_CODE 78 drivers/gpu/drm/amd/powerplay/smumgr/vega10_smumgr.c PP_ASSERT_WITH_CODE(priv->smu_tables.entry[table_id].size != 0, PP_ASSERT_WITH_CODE 153 drivers/gpu/drm/amd/powerplay/smumgr/vega10_smumgr.c PP_ASSERT_WITH_CODE(!smu9_send_msg_to_smc(hwmgr, PP_ASSERT_WITH_CODE 332 drivers/gpu/drm/amd/powerplay/smumgr/vega10_smumgr.c PP_ASSERT_WITH_CODE(!vega10_verify_smc_interface(hwmgr), PP_ASSERT_WITH_CODE 47 drivers/gpu/drm/amd/powerplay/smumgr/vega12_smumgr.c PP_ASSERT_WITH_CODE(table_id < TABLE_COUNT, PP_ASSERT_WITH_CODE 49 drivers/gpu/drm/amd/powerplay/smumgr/vega12_smumgr.c PP_ASSERT_WITH_CODE(priv->smu_tables.entry[table_id].version != 0, PP_ASSERT_WITH_CODE 51 drivers/gpu/drm/amd/powerplay/smumgr/vega12_smumgr.c PP_ASSERT_WITH_CODE(priv->smu_tables.entry[table_id].size != 0, PP_ASSERT_WITH_CODE 53 drivers/gpu/drm/amd/powerplay/smumgr/vega12_smumgr.c PP_ASSERT_WITH_CODE(smu9_send_msg_to_smc_with_parameter(hwmgr, PP_ASSERT_WITH_CODE 57 drivers/gpu/drm/amd/powerplay/smumgr/vega12_smumgr.c PP_ASSERT_WITH_CODE(smu9_send_msg_to_smc_with_parameter(hwmgr, PP_ASSERT_WITH_CODE 62 drivers/gpu/drm/amd/powerplay/smumgr/vega12_smumgr.c PP_ASSERT_WITH_CODE(smu9_send_msg_to_smc_with_parameter(hwmgr, PP_ASSERT_WITH_CODE 88 drivers/gpu/drm/amd/powerplay/smumgr/vega12_smumgr.c PP_ASSERT_WITH_CODE(table_id < TABLE_COUNT, PP_ASSERT_WITH_CODE 90 drivers/gpu/drm/amd/powerplay/smumgr/vega12_smumgr.c PP_ASSERT_WITH_CODE(priv->smu_tables.entry[table_id].version != 0, PP_ASSERT_WITH_CODE 92 drivers/gpu/drm/amd/powerplay/smumgr/vega12_smumgr.c PP_ASSERT_WITH_CODE(priv->smu_tables.entry[table_id].size != 0, PP_ASSERT_WITH_CODE 98 drivers/gpu/drm/amd/powerplay/smumgr/vega12_smumgr.c PP_ASSERT_WITH_CODE(smu9_send_msg_to_smc_with_parameter(hwmgr, PP_ASSERT_WITH_CODE 103 drivers/gpu/drm/amd/powerplay/smumgr/vega12_smumgr.c PP_ASSERT_WITH_CODE(smu9_send_msg_to_smc_with_parameter(hwmgr, PP_ASSERT_WITH_CODE 108 drivers/gpu/drm/amd/powerplay/smumgr/vega12_smumgr.c PP_ASSERT_WITH_CODE(smu9_send_msg_to_smc_with_parameter(hwmgr, PP_ASSERT_WITH_CODE 126 drivers/gpu/drm/amd/powerplay/smumgr/vega12_smumgr.c PP_ASSERT_WITH_CODE(smu9_send_msg_to_smc_with_parameter(hwmgr, PP_ASSERT_WITH_CODE 130 drivers/gpu/drm/amd/powerplay/smumgr/vega12_smumgr.c PP_ASSERT_WITH_CODE(smu9_send_msg_to_smc_with_parameter(hwmgr, PP_ASSERT_WITH_CODE 135 drivers/gpu/drm/amd/powerplay/smumgr/vega12_smumgr.c PP_ASSERT_WITH_CODE(smu9_send_msg_to_smc_with_parameter(hwmgr, PP_ASSERT_WITH_CODE 139 drivers/gpu/drm/amd/powerplay/smumgr/vega12_smumgr.c PP_ASSERT_WITH_CODE(smu9_send_msg_to_smc_with_parameter(hwmgr, PP_ASSERT_WITH_CODE 156 drivers/gpu/drm/amd/powerplay/smumgr/vega12_smumgr.c PP_ASSERT_WITH_CODE(smu9_send_msg_to_smc(hwmgr, PP_ASSERT_WITH_CODE 162 drivers/gpu/drm/amd/powerplay/smumgr/vega12_smumgr.c PP_ASSERT_WITH_CODE(smu9_send_msg_to_smc(hwmgr, PP_ASSERT_WITH_CODE 370 drivers/gpu/drm/amd/powerplay/smumgr/vega12_smumgr.c PP_ASSERT_WITH_CODE(smu9_is_smc_ram_running(hwmgr), PP_ASSERT_WITH_CODE 169 drivers/gpu/drm/amd/powerplay/smumgr/vega20_smumgr.c PP_ASSERT_WITH_CODE(table_id < TABLE_COUNT, PP_ASSERT_WITH_CODE 171 drivers/gpu/drm/amd/powerplay/smumgr/vega20_smumgr.c PP_ASSERT_WITH_CODE(priv->smu_tables.entry[table_id].version != 0, PP_ASSERT_WITH_CODE 173 drivers/gpu/drm/amd/powerplay/smumgr/vega20_smumgr.c PP_ASSERT_WITH_CODE(priv->smu_tables.entry[table_id].size != 0, PP_ASSERT_WITH_CODE 176 drivers/gpu/drm/amd/powerplay/smumgr/vega20_smumgr.c PP_ASSERT_WITH_CODE((ret = vega20_send_msg_to_smc_with_parameter(hwmgr, PP_ASSERT_WITH_CODE 181 drivers/gpu/drm/amd/powerplay/smumgr/vega20_smumgr.c PP_ASSERT_WITH_CODE((ret = vega20_send_msg_to_smc_with_parameter(hwmgr, PP_ASSERT_WITH_CODE 186 drivers/gpu/drm/amd/powerplay/smumgr/vega20_smumgr.c PP_ASSERT_WITH_CODE((ret = vega20_send_msg_to_smc_with_parameter(hwmgr, PP_ASSERT_WITH_CODE 212 drivers/gpu/drm/amd/powerplay/smumgr/vega20_smumgr.c PP_ASSERT_WITH_CODE(table_id < TABLE_COUNT, PP_ASSERT_WITH_CODE 214 drivers/gpu/drm/amd/powerplay/smumgr/vega20_smumgr.c PP_ASSERT_WITH_CODE(priv->smu_tables.entry[table_id].version != 0, PP_ASSERT_WITH_CODE 216 drivers/gpu/drm/amd/powerplay/smumgr/vega20_smumgr.c PP_ASSERT_WITH_CODE(priv->smu_tables.entry[table_id].size != 0, PP_ASSERT_WITH_CODE 222 drivers/gpu/drm/amd/powerplay/smumgr/vega20_smumgr.c PP_ASSERT_WITH_CODE((ret = vega20_send_msg_to_smc_with_parameter(hwmgr, PP_ASSERT_WITH_CODE 227 drivers/gpu/drm/amd/powerplay/smumgr/vega20_smumgr.c PP_ASSERT_WITH_CODE((ret = vega20_send_msg_to_smc_with_parameter(hwmgr, PP_ASSERT_WITH_CODE 232 drivers/gpu/drm/amd/powerplay/smumgr/vega20_smumgr.c PP_ASSERT_WITH_CODE((ret = vega20_send_msg_to_smc_with_parameter(hwmgr, PP_ASSERT_WITH_CODE 250 drivers/gpu/drm/amd/powerplay/smumgr/vega20_smumgr.c PP_ASSERT_WITH_CODE((ret = vega20_send_msg_to_smc_with_parameter(hwmgr, PP_ASSERT_WITH_CODE 255 drivers/gpu/drm/amd/powerplay/smumgr/vega20_smumgr.c PP_ASSERT_WITH_CODE((ret = vega20_send_msg_to_smc_with_parameter(hwmgr, PP_ASSERT_WITH_CODE 260 drivers/gpu/drm/amd/powerplay/smumgr/vega20_smumgr.c PP_ASSERT_WITH_CODE((ret = vega20_send_msg_to_smc_with_parameter(hwmgr, PP_ASSERT_WITH_CODE 276 drivers/gpu/drm/amd/powerplay/smumgr/vega20_smumgr.c PP_ASSERT_WITH_CODE((ret = vega20_send_msg_to_smc_with_parameter(hwmgr, PP_ASSERT_WITH_CODE 281 drivers/gpu/drm/amd/powerplay/smumgr/vega20_smumgr.c PP_ASSERT_WITH_CODE((ret = vega20_send_msg_to_smc_with_parameter(hwmgr, PP_ASSERT_WITH_CODE 286 drivers/gpu/drm/amd/powerplay/smumgr/vega20_smumgr.c PP_ASSERT_WITH_CODE((ret = vega20_send_msg_to_smc_with_parameter(hwmgr, PP_ASSERT_WITH_CODE 311 drivers/gpu/drm/amd/powerplay/smumgr/vega20_smumgr.c PP_ASSERT_WITH_CODE((ret = vega20_send_msg_to_smc_with_parameter(hwmgr, PP_ASSERT_WITH_CODE 315 drivers/gpu/drm/amd/powerplay/smumgr/vega20_smumgr.c PP_ASSERT_WITH_CODE((ret = vega20_send_msg_to_smc_with_parameter(hwmgr, PP_ASSERT_WITH_CODE 320 drivers/gpu/drm/amd/powerplay/smumgr/vega20_smumgr.c PP_ASSERT_WITH_CODE((ret = vega20_send_msg_to_smc_with_parameter(hwmgr, PP_ASSERT_WITH_CODE 324 drivers/gpu/drm/amd/powerplay/smumgr/vega20_smumgr.c PP_ASSERT_WITH_CODE((ret = vega20_send_msg_to_smc_with_parameter(hwmgr, PP_ASSERT_WITH_CODE 342 drivers/gpu/drm/amd/powerplay/smumgr/vega20_smumgr.c PP_ASSERT_WITH_CODE((ret = vega20_send_msg_to_smc(hwmgr, PP_ASSERT_WITH_CODE 347 drivers/gpu/drm/amd/powerplay/smumgr/vega20_smumgr.c PP_ASSERT_WITH_CODE((ret = vega20_send_msg_to_smc(hwmgr, PP_ASSERT_WITH_CODE 384 drivers/gpu/drm/amd/powerplay/smumgr/vega20_smumgr.c PP_ASSERT_WITH_CODE((ret = vega20_send_msg_to_smc_with_parameter(hwmgr, PP_ASSERT_WITH_CODE 389 drivers/gpu/drm/amd/powerplay/smumgr/vega20_smumgr.c PP_ASSERT_WITH_CODE((ret = vega20_send_msg_to_smc_with_parameter(hwmgr, PP_ASSERT_WITH_CODE 565 drivers/gpu/drm/amd/powerplay/smumgr/vega20_smumgr.c PP_ASSERT_WITH_CODE(ret, PP_ASSERT_WITH_CODE 570 drivers/gpu/drm/amd/powerplay/smumgr/vega20_smumgr.c PP_ASSERT_WITH_CODE(!ret, PP_ASSERT_WITH_CODE 139 drivers/gpu/drm/amd/powerplay/smumgr/vegam_smumgr.c PP_ASSERT_WITH_CODE(false, "SMU Firmware start failed!", return -1); PP_ASSERT_WITH_CODE 211 drivers/gpu/drm/amd/powerplay/smumgr/vegam_smumgr.c PP_ASSERT_WITH_CODE(0, "Failed to load SMU ucode.", return result); PP_ASSERT_WITH_CODE 794 drivers/gpu/drm/amd/powerplay/smumgr/vegam_smumgr.c PP_ASSERT_WITH_CODE((clock >= min), PP_ASSERT_WITH_CODE 824 drivers/gpu/drm/amd/powerplay/smumgr/vegam_smumgr.c PP_ASSERT_WITH_CODE((0 == result), PP_ASSERT_WITH_CODE 915 drivers/gpu/drm/amd/powerplay/smumgr/vegam_smumgr.c PP_ASSERT_WITH_CODE((1 <= pcie_entry_cnt), PP_ASSERT_WITH_CODE 965 drivers/gpu/drm/amd/powerplay/smumgr/vegam_smumgr.c PP_ASSERT_WITH_CODE(!atomctrl_get_memory_pll_dividers_ai(hwmgr, PP_ASSERT_WITH_CODE 992 drivers/gpu/drm/amd/powerplay/smumgr/vegam_smumgr.c PP_ASSERT_WITH_CODE(!result, PP_ASSERT_WITH_CODE 998 drivers/gpu/drm/amd/powerplay/smumgr/vegam_smumgr.c PP_ASSERT_WITH_CODE(!result, PP_ASSERT_WITH_CODE 1047 drivers/gpu/drm/amd/powerplay/smumgr/vegam_smumgr.c PP_ASSERT_WITH_CODE((0 != dpm_table->mclk_table.dpm_levels[i].value), PP_ASSERT_WITH_CODE 1098 drivers/gpu/drm/amd/powerplay/smumgr/vegam_smumgr.c PP_ASSERT_WITH_CODE(i < table_info->vdd_dep_on_mclk->count, PP_ASSERT_WITH_CODE 1128 drivers/gpu/drm/amd/powerplay/smumgr/vegam_smumgr.c PP_ASSERT_WITH_CODE(!result, PP_ASSERT_WITH_CODE 1135 drivers/gpu/drm/amd/powerplay/smumgr/vegam_smumgr.c PP_ASSERT_WITH_CODE(!result, PP_ASSERT_WITH_CODE 1166 drivers/gpu/drm/amd/powerplay/smumgr/vegam_smumgr.c PP_ASSERT_WITH_CODE((0 == result), PP_ASSERT_WITH_CODE 1241 drivers/gpu/drm/amd/powerplay/smumgr/vegam_smumgr.c PP_ASSERT_WITH_CODE((0 == result), PP_ASSERT_WITH_CODE 1267 drivers/gpu/drm/amd/powerplay/smumgr/vegam_smumgr.c PP_ASSERT_WITH_CODE(result == 0, PP_ASSERT_WITH_CODE 1353 drivers/gpu/drm/amd/powerplay/smumgr/vegam_smumgr.c PP_ASSERT_WITH_CODE((0 == result), PP_ASSERT_WITH_CODE 1360 drivers/gpu/drm/amd/powerplay/smumgr/vegam_smumgr.c PP_ASSERT_WITH_CODE((0 == result), PP_ASSERT_WITH_CODE 1460 drivers/gpu/drm/amd/powerplay/smumgr/vegam_smumgr.c PP_ASSERT_WITH_CODE(cac_dtp_table->usTargetOperatingTemp <= 255, PP_ASSERT_WITH_CODE 1542 drivers/gpu/drm/amd/powerplay/smumgr/vegam_smumgr.c PP_ASSERT_WITH_CODE(false, PP_ASSERT_WITH_CODE 1690 drivers/gpu/drm/amd/powerplay/smumgr/vegam_smumgr.c PP_ASSERT_WITH_CODE(false, PP_ASSERT_WITH_CODE 1716 drivers/gpu/drm/amd/powerplay/smumgr/vegam_smumgr.c PP_ASSERT_WITH_CODE(false, PP_ASSERT_WITH_CODE 1778 drivers/gpu/drm/amd/powerplay/smumgr/vegam_smumgr.c PP_ASSERT_WITH_CODE(false, PP_ASSERT_WITH_CODE 1862 drivers/gpu/drm/amd/powerplay/smumgr/vegam_smumgr.c PP_ASSERT_WITH_CODE(false, PP_ASSERT_WITH_CODE 1867 drivers/gpu/drm/amd/powerplay/smumgr/vegam_smumgr.c PP_ASSERT_WITH_CODE(false, PP_ASSERT_WITH_CODE 1872 drivers/gpu/drm/amd/powerplay/smumgr/vegam_smumgr.c PP_ASSERT_WITH_CODE(false, PP_ASSERT_WITH_CODE 1876 drivers/gpu/drm/amd/powerplay/smumgr/vegam_smumgr.c PP_ASSERT_WITH_CODE(false, PP_ASSERT_WITH_CODE 1882 drivers/gpu/drm/amd/powerplay/smumgr/vegam_smumgr.c PP_ASSERT_WITH_CODE(false, PP_ASSERT_WITH_CODE 1887 drivers/gpu/drm/amd/powerplay/smumgr/vegam_smumgr.c PP_ASSERT_WITH_CODE(false, PP_ASSERT_WITH_CODE 1892 drivers/gpu/drm/amd/powerplay/smumgr/vegam_smumgr.c PP_ASSERT_WITH_CODE(false, PP_ASSERT_WITH_CODE 1897 drivers/gpu/drm/amd/powerplay/smumgr/vegam_smumgr.c PP_ASSERT_WITH_CODE(false, PP_ASSERT_WITH_CODE 1905 drivers/gpu/drm/amd/powerplay/smumgr/vegam_smumgr.c PP_ASSERT_WITH_CODE(false, PP_ASSERT_WITH_CODE 1960 drivers/gpu/drm/amd/powerplay/smumgr/vegam_smumgr.c PP_ASSERT_WITH_CODE(!result, PP_ASSERT_WITH_CODE 1967 drivers/gpu/drm/amd/powerplay/smumgr/vegam_smumgr.c PP_ASSERT_WITH_CODE(!result, PP_ASSERT_WITH_CODE 1971 drivers/gpu/drm/amd/powerplay/smumgr/vegam_smumgr.c PP_ASSERT_WITH_CODE(!result, PP_ASSERT_WITH_CODE 1975 drivers/gpu/drm/amd/powerplay/smumgr/vegam_smumgr.c PP_ASSERT_WITH_CODE(!result, PP_ASSERT_WITH_CODE 1979 drivers/gpu/drm/amd/powerplay/smumgr/vegam_smumgr.c PP_ASSERT_WITH_CODE(!result, PP_ASSERT_WITH_CODE 1983 drivers/gpu/drm/amd/powerplay/smumgr/vegam_smumgr.c PP_ASSERT_WITH_CODE(!result, PP_ASSERT_WITH_CODE 1991 drivers/gpu/drm/amd/powerplay/smumgr/vegam_smumgr.c PP_ASSERT_WITH_CODE(!result, PP_ASSERT_WITH_CODE 1995 drivers/gpu/drm/amd/powerplay/smumgr/vegam_smumgr.c PP_ASSERT_WITH_CODE(!result, PP_ASSERT_WITH_CODE 1999 drivers/gpu/drm/amd/powerplay/smumgr/vegam_smumgr.c PP_ASSERT_WITH_CODE(!result, PP_ASSERT_WITH_CODE 2003 drivers/gpu/drm/amd/powerplay/smumgr/vegam_smumgr.c PP_ASSERT_WITH_CODE(!result, PP_ASSERT_WITH_CODE 2007 drivers/gpu/drm/amd/powerplay/smumgr/vegam_smumgr.c PP_ASSERT_WITH_CODE(!result, PP_ASSERT_WITH_CODE 2013 drivers/gpu/drm/amd/powerplay/smumgr/vegam_smumgr.c PP_ASSERT_WITH_CODE(!result, PP_ASSERT_WITH_CODE 2019 drivers/gpu/drm/amd/powerplay/smumgr/vegam_smumgr.c PP_ASSERT_WITH_CODE(!result, PP_ASSERT_WITH_CODE 2040 drivers/gpu/drm/amd/powerplay/smumgr/vegam_smumgr.c PP_ASSERT_WITH_CODE(hw_data->dpm_table.pcie_speed_table.count >= 1, PP_ASSERT_WITH_CODE 2049 drivers/gpu/drm/amd/powerplay/smumgr/vegam_smumgr.c PP_ASSERT_WITH_CODE(!result, PP_ASSERT_WITH_CODE 2112 drivers/gpu/drm/amd/powerplay/smumgr/vegam_smumgr.c PP_ASSERT_WITH_CODE(!result, PP_ASSERT_WITH_CODE 2145 drivers/gpu/drm/amd/powerplay/smumgr/vegam_smumgr.c PP_ASSERT_WITH_CODE(!result, PP_ASSERT_WITH_CODE 2149 drivers/gpu/drm/amd/powerplay/smumgr/vegam_smumgr.c PP_ASSERT_WITH_CODE(!result, PP_ASSERT_WITH_CODE 2153 drivers/gpu/drm/amd/powerplay/smumgr/vegam_smumgr.c PP_ASSERT_WITH_CODE(!result, PP_ASSERT_WITH_CODE 2243 drivers/gpu/drm/amd/powerplay/smumgr/vegam_smumgr.c PP_ASSERT_WITH_CODE((result == 0), PP_ASSERT_WITH_CODE 2247 drivers/gpu/drm/amd/powerplay/smumgr/vegam_smumgr.c PP_ASSERT_WITH_CODE((result == 0), PP_ASSERT_WITH_CODE 2273 drivers/gpu/drm/amd/powerplay/smumgr/vegam_smumgr.c PP_ASSERT_WITH_CODE(hwmgr->thermal_controller.fanInfo.bNoFan,