PPCVEC3          3090 arch/powerpc/xmon/ppc-opc.c {"vmul10cuq",	VX (4,	 1),	VXVB_MASK,   PPCVEC3,	0,		{VD, VA}},
PPCVEC3          3094 arch/powerpc/xmon/ppc-opc.c {"vcmpneb",	VXR(4,	 7,0),	VXR_MASK,    PPCVEC3,	0,		{VD, VA, VB}},
PPCVEC3          3120 arch/powerpc/xmon/ppc-opc.c {"vmsumudm",	VXA(4,	35),	VXA_MASK,    PPCVEC3,	0,		{VD, VA, VB, VC}},
PPCVEC3          3154 arch/powerpc/xmon/ppc-opc.c {"vpermr",	VXA(4,	59),	VXA_MASK,    PPCVEC3,	0,		{VD, VA, VB, VC}},
PPCVEC3          3165 arch/powerpc/xmon/ppc-opc.c {"vmul10ecuq",	VX (4,	65),	VX_MASK,     PPCVEC3,	0,		{VD, VA, VB}},
PPCVEC3          3169 arch/powerpc/xmon/ppc-opc.c {"vcmpneh",	VXR(4,	71,0),	VXR_MASK,    PPCVEC3,	0,		{VD, VA, VB}},
PPCVEC3          3188 arch/powerpc/xmon/ppc-opc.c {"vrlwmi",	VX (4,	133),	VX_MASK,     PPCVEC3,	0,		{VD, VA, VB}},
PPCVEC3          3190 arch/powerpc/xmon/ppc-opc.c {"vcmpnew",	VXR(4,	135,0),	VXR_MASK,    PPCVEC3,	0,		{VD, VA, VB}},
PPCVEC3          3203 arch/powerpc/xmon/ppc-opc.c {"vrldmi",	VX (4, 197),	VX_MASK,     PPCVEC3,	0,		{VD, VA, VB}},
PPCVEC3          3214 arch/powerpc/xmon/ppc-opc.c {"vcmpnezb",	VXR(4, 263,0),	VXR_MASK,    PPCVEC3,	0,		{VD, VA, VB}},
PPCVEC3          3228 arch/powerpc/xmon/ppc-opc.c {"vcmpnezh",	VXR(4, 327,0),	VXR_MASK,    PPCVEC3,	0,		{VD, VA, VB}},
PPCVEC3          3242 arch/powerpc/xmon/ppc-opc.c {"vrlwnm",	VX (4, 389),	VX_MASK,     PPCVEC3,	0,		{VD, VA, VB}},
PPCVEC3          3243 arch/powerpc/xmon/ppc-opc.c {"vcmpnezw",	VXR(4, 391,0),	VXR_MASK,    PPCVEC3,	0,		{VD, VA, VB}},
PPCVEC3          3252 arch/powerpc/xmon/ppc-opc.c {"vrldnm",	VX (4, 453),	VX_MASK,     PPCVEC3,	0,		{VD, VA, VB}},
PPCVEC3          3262 arch/powerpc/xmon/ppc-opc.c {"vmul10uq",	VX (4, 513),	VXVB_MASK,   PPCVEC3,	0,		{VD, VA}},
PPCVEC3          3279 arch/powerpc/xmon/ppc-opc.c {"vextractub",	VX (4, 525),   VXUIMM4_MASK, PPCVEC3,	0,		{VD, VB, UIMM4}},
PPCVEC3          3318 arch/powerpc/xmon/ppc-opc.c {"vmul10euq",	VX (4, 577),	VX_MASK,     PPCVEC3,	0,		{VD, VA, VB}},
PPCVEC3          3325 arch/powerpc/xmon/ppc-opc.c {"vextractuh",	VX (4, 589),   VXUIMM4_MASK, PPCVEC3,	0,		{VD, VB, UIMM4}},
PPCVEC3          3345 arch/powerpc/xmon/ppc-opc.c {"vextractuw",	VX (4, 653),   VXUIMM4_MASK, PPCVEC3,	0,		{VD, VB, UIMM4}},
PPCVEC3          3377 arch/powerpc/xmon/ppc-opc.c {"vextractd",	VX (4, 717),   VXUIMM4_MASK, PPCVEC3,	0,		{VD, VB, UIMM4}},
PPCVEC3          3442 arch/powerpc/xmon/ppc-opc.c {"vinsertb",	VX (4, 781),   VXUIMM4_MASK, PPCVEC3,	0,		{VD, VB, UIMM4}},
PPCVEC3          3476 arch/powerpc/xmon/ppc-opc.c {"bcdcpsgn.",	VX (4, 833),	VX_MASK,     PPCVEC3,	0,		{VD, VA, VB}},
PPCVEC3          3484 arch/powerpc/xmon/ppc-opc.c {"vinserth",	VX (4, 845),   VXUIMM4_MASK, PPCVEC3,	0,		{VD, VB, UIMM4}},
PPCVEC3          3500 arch/powerpc/xmon/ppc-opc.c {"vinsertw",	VX (4, 909),   VXUIMM4_MASK, PPCVEC3,	0,		{VD, VB, UIMM4}},
PPCVEC3          3509 arch/powerpc/xmon/ppc-opc.c {"vinsertd",	VX (4, 973),   VXUIMM4_MASK, PPCVEC3,	0,		{VD, VB, UIMM4}},
PPCVEC3          3522 arch/powerpc/xmon/ppc-opc.c {"vcmpneb.",	VXR(4,	 7,1),	VXR_MASK,    PPCVEC3,	0,		{VD, VA, VB}},
PPCVEC3          3555 arch/powerpc/xmon/ppc-opc.c {"vcmpneh.",	VXR(4,	71,1),	VXR_MASK,    PPCVEC3,	0,		{VD, VA, VB}},
PPCVEC3          3585 arch/powerpc/xmon/ppc-opc.c {"bcdus.",	VX (4,1153),	VX_MASK,     PPCVEC3,	0,		{VD, VA, VB}},
PPCVEC3          3590 arch/powerpc/xmon/ppc-opc.c {"vcmpnew.",	VXR(4, 135,1),	VXR_MASK,    PPCVEC3,	0,		{VD, VA, VB}},
PPCVEC3          3601 arch/powerpc/xmon/ppc-opc.c {"bcds.",	VX (4,1217),	VXPS_MASK,   PPCVEC3,	0,		{VD, VA, VB, PS}},
PPCVEC3          3627 arch/powerpc/xmon/ppc-opc.c {"bcdtrunc.",	VX (4,1281),	VXPS_MASK,   PPCVEC3,	0,		{VD, VA, VB, PS}},
PPCVEC3          3637 arch/powerpc/xmon/ppc-opc.c {"vcmpnezb.",	VXR(4, 263,1),	VXR_MASK,    PPCVEC3,	0,		{VD, VA, VB}},
PPCVEC3          3658 arch/powerpc/xmon/ppc-opc.c {"bcdutrunc.",	VX (4,1345),	VX_MASK,     PPCVEC3,	0,		{VD, VA, VB}},
PPCVEC3          3664 arch/powerpc/xmon/ppc-opc.c {"vcmpnezh.",	VXR(4, 327,1),	VXR_MASK,    PPCVEC3,	0,		{VD, VA, VB}},
PPCVEC3          3682 arch/powerpc/xmon/ppc-opc.c {"bcdctsq.",	VXVA(4,1409,0),	VXVA_MASK,   PPCVEC3,	0,		{VD, VB}},
PPCVEC3          3683 arch/powerpc/xmon/ppc-opc.c {"bcdcfsq.",	VXVA(4,1409,2),	VXVAPS_MASK, PPCVEC3,	0,		{VD, VB, PS}},
PPCVEC3          3684 arch/powerpc/xmon/ppc-opc.c {"bcdctz.",	VXVA(4,1409,4),	VXVAPS_MASK, PPCVEC3,	0,		{VD, VB, PS}},
PPCVEC3          3685 arch/powerpc/xmon/ppc-opc.c {"bcdctn.",	VXVA(4,1409,5),	VXVA_MASK,   PPCVEC3,	0,		{VD, VB}},
PPCVEC3          3686 arch/powerpc/xmon/ppc-opc.c {"bcdcfz.",	VXVA(4,1409,6),	VXVAPS_MASK, PPCVEC3,	0,		{VD, VB, PS}},
PPCVEC3          3687 arch/powerpc/xmon/ppc-opc.c {"bcdcfn.",	VXVA(4,1409,7),	VXVAPS_MASK, PPCVEC3,	0,		{VD, VB, PS}},
PPCVEC3          3688 arch/powerpc/xmon/ppc-opc.c {"bcdsetsgn.",	VXVA(4,1409,31), VXVAPS_MASK, PPCVEC3,	0,		{VD, VB, PS}},
PPCVEC3          3696 arch/powerpc/xmon/ppc-opc.c {"vcmpnezw.",	VXR(4, 391,1),	VXR_MASK,    PPCVEC3,	0,		{VD, VA, VB}},
PPCVEC3          3713 arch/powerpc/xmon/ppc-opc.c {"bcdsr.",	VX (4,1473),	VXPS_MASK,   PPCVEC3,	0,		{VD, VA, VB, PS}},
PPCVEC3          3722 arch/powerpc/xmon/ppc-opc.c {"vbpermd",	VX (4,1484),	VX_MASK,     PPCVEC3,	0,		{VD, VA, VB}},
PPCVEC3          3733 arch/powerpc/xmon/ppc-opc.c {"vclzlsbb",	VXVA(4,1538,0), VXVA_MASK,   PPCVEC3,	0,		{RT, VB}},
PPCVEC3          3734 arch/powerpc/xmon/ppc-opc.c {"vctzlsbb",	VXVA(4,1538,1), VXVA_MASK,   PPCVEC3,	0,		{RT, VB}},
PPCVEC3          3735 arch/powerpc/xmon/ppc-opc.c {"vnegw",	VXVA(4,1538,6), VXVA_MASK,   PPCVEC3,	0,		{VD, VB}},
PPCVEC3          3736 arch/powerpc/xmon/ppc-opc.c {"vnegd",	VXVA(4,1538,7), VXVA_MASK,   PPCVEC3,	0,		{VD, VB}},
PPCVEC3          3737 arch/powerpc/xmon/ppc-opc.c {"vprtybw",	VXVA(4,1538,8), VXVA_MASK,   PPCVEC3,	0,		{VD, VB}},
PPCVEC3          3738 arch/powerpc/xmon/ppc-opc.c {"vprtybd",	VXVA(4,1538,9), VXVA_MASK,   PPCVEC3,	0,		{VD, VB}},
PPCVEC3          3739 arch/powerpc/xmon/ppc-opc.c {"vprtybq",	VXVA(4,1538,10), VXVA_MASK,  PPCVEC3,	0,		{VD, VB}},
PPCVEC3          3740 arch/powerpc/xmon/ppc-opc.c {"vextsb2w",	VXVA(4,1538,16), VXVA_MASK,  PPCVEC3,	0,		{VD, VB}},
PPCVEC3          3741 arch/powerpc/xmon/ppc-opc.c {"vextsh2w",	VXVA(4,1538,17), VXVA_MASK,  PPCVEC3,	0,		{VD, VB}},
PPCVEC3          3742 arch/powerpc/xmon/ppc-opc.c {"vextsb2d",	VXVA(4,1538,24), VXVA_MASK,  PPCVEC3,	0,		{VD, VB}},
PPCVEC3          3743 arch/powerpc/xmon/ppc-opc.c {"vextsh2d",	VXVA(4,1538,25), VXVA_MASK,  PPCVEC3,	0,		{VD, VB}},
PPCVEC3          3744 arch/powerpc/xmon/ppc-opc.c {"vextsw2d",	VXVA(4,1538,26), VXVA_MASK,  PPCVEC3,	0,		{VD, VB}},
PPCVEC3          3745 arch/powerpc/xmon/ppc-opc.c {"vctzb",	VXVA(4,1538,28), VXVA_MASK,  PPCVEC3,	0,		{VD, VB}},
PPCVEC3          3746 arch/powerpc/xmon/ppc-opc.c {"vctzh",	VXVA(4,1538,29), VXVA_MASK,  PPCVEC3,	0,		{VD, VB}},
PPCVEC3          3747 arch/powerpc/xmon/ppc-opc.c {"vctzw",	VXVA(4,1538,30), VXVA_MASK,  PPCVEC3,	0,		{VD, VB}},
PPCVEC3          3748 arch/powerpc/xmon/ppc-opc.c {"vctzd",	VXVA(4,1538,31), VXVA_MASK,  PPCVEC3,	0,		{VD, VB}},
PPCVEC3          3754 arch/powerpc/xmon/ppc-opc.c {"vextublx",	VX (4,1549),	VX_MASK,     PPCVEC3,	0,		{RT, RA, VB}},
PPCVEC3          3761 arch/powerpc/xmon/ppc-opc.c {"vextuhlx",	VX (4,1613),	VX_MASK,     PPCVEC3,	0,		{RT, RA, VB}},
PPCVEC3          3771 arch/powerpc/xmon/ppc-opc.c {"vextuwlx",	VX (4,1677),	VX_MASK,     PPCVEC3,	0,		{RT, RA, VB}},
PPCVEC3          3782 arch/powerpc/xmon/ppc-opc.c {"vsrv",	VX (4,1796),	VX_MASK,     PPCVEC3,	0,		{VD, VA, VB}},
PPCVEC3          3787 arch/powerpc/xmon/ppc-opc.c {"vextubrx",	VX (4,1805),	VX_MASK,     PPCVEC3,	0,		{RT, RA, VB}},
PPCVEC3          3793 arch/powerpc/xmon/ppc-opc.c {"vslv",	VX (4,1860),	VX_MASK,     PPCVEC3,	0,		{VD, VA, VB}},
PPCVEC3          3795 arch/powerpc/xmon/ppc-opc.c {"vextuhrx",	VX (4,1869),	VX_MASK,     PPCVEC3,	0,		{RT, RA, VB}},
PPCVEC3          3810 arch/powerpc/xmon/ppc-opc.c {"vextuwrx",	VX (4,1933),	VX_MASK,     PPCVEC3,	0,		{RT, RA, VB}},