PPCVEC2          3136 arch/powerpc/xmon/ppc-opc.c {"vpermxor",	VXA(4,	45),	VXA_MASK,    PPCVEC2,	0,		{VD, VA, VB, VC}},
PPCVEC2          3156 arch/powerpc/xmon/ppc-opc.c {"vaddeuqm",	VXA(4,	60),	VXA_MASK,    PPCVEC2,	0,		{VD, VA, VB, VC}},
PPCVEC2          3158 arch/powerpc/xmon/ppc-opc.c {"vaddecuq",	VXA(4,	61),	VXA_MASK,    PPCVEC2,	0,		{VD, VA, VB, VC}},
PPCVEC2          3160 arch/powerpc/xmon/ppc-opc.c {"vsubeuqm",	VXA(4,	62),	VXA_MASK,    PPCVEC2,	0,		{VD, VA, VB, VC}},
PPCVEC2          3162 arch/powerpc/xmon/ppc-opc.c {"vsubecuq",	VXA(4,	63),	VXA_MASK,    PPCVEC2,	0,		{VD, VA, VB, VC}},
PPCVEC2          3191 arch/powerpc/xmon/ppc-opc.c {"vmulouw",	VX (4,	136),	VX_MASK,     PPCVEC2,	0,		{VD, VA, VB}},
PPCVEC2          3192 arch/powerpc/xmon/ppc-opc.c {"vmuluwm",	VX (4,	137),	VX_MASK,     PPCVEC2,	0,		{VD, VA, VB}},
PPCVEC2          3200 arch/powerpc/xmon/ppc-opc.c {"vaddudm",	VX (4, 192),	VX_MASK,     PPCVEC2,	0,		{VD, VA, VB}},
PPCVEC2          3201 arch/powerpc/xmon/ppc-opc.c {"vmaxud",	VX (4, 194),	VX_MASK,     PPCVEC2,	0,		{VD, VA, VB}},
PPCVEC2          3202 arch/powerpc/xmon/ppc-opc.c {"vrld",	VX (4, 196),	VX_MASK,     PPCVEC2,	0,		{VD, VA, VB}},
PPCVEC2          3205 arch/powerpc/xmon/ppc-opc.c {"vcmpequd",	VXR(4, 199,0),	VXR_MASK,    PPCVEC2,	0,		{VD, VA, VB}},
PPCVEC2          3211 arch/powerpc/xmon/ppc-opc.c {"vadduqm",	VX (4, 256),	VX_MASK,     PPCVEC2,	0,		{VD, VA, VB}},
PPCVEC2          3225 arch/powerpc/xmon/ppc-opc.c {"vaddcuq",	VX (4, 320),	VX_MASK,     PPCVEC2,	0,		{VD, VA, VB}},
PPCVEC2          3244 arch/powerpc/xmon/ppc-opc.c {"vmulosw",	VX (4, 392),	VX_MASK,     PPCVEC2,	0,		{VD, VA, VB}},
PPCVEC2          3250 arch/powerpc/xmon/ppc-opc.c {"vmaxsd",	VX (4, 450),	VX_MASK,     PPCVEC2,	0,		{VD, VA, VB}},
PPCVEC2          3339 arch/powerpc/xmon/ppc-opc.c {"vmuleuw",	VX (4, 648),	VX_MASK,     PPCVEC2,	0,		{VD, VA, VB}},
PPCVEC2          3366 arch/powerpc/xmon/ppc-opc.c {"vminud",	VX (4, 706),	VX_MASK,     PPCVEC2,	0,		{VD, VA, VB}},
PPCVEC2          3372 arch/powerpc/xmon/ppc-opc.c {"vcmpgtud",	VXR(4, 711,0),	VXR_MASK,    PPCVEC2,	0,		{VD, VA, VB}},
PPCVEC2          3496 arch/powerpc/xmon/ppc-opc.c {"vmulesw",	VX (4, 904),	VX_MASK,     PPCVEC2,	0,		{VD, VA, VB}},
PPCVEC2          3503 arch/powerpc/xmon/ppc-opc.c {"vminsd",	VX (4, 962),	VX_MASK,     PPCVEC2,	0,		{VD, VA, VB}},
PPCVEC2          3504 arch/powerpc/xmon/ppc-opc.c {"vsrad",	VX (4, 964),	VX_MASK,     PPCVEC2,	0,		{VD, VA, VB}},
PPCVEC2          3506 arch/powerpc/xmon/ppc-opc.c {"vcmpgtsd",	VXR(4, 967,0),	VXR_MASK,    PPCVEC2,	0,		{VD, VA, VB}},
PPCVEC2          3516 arch/powerpc/xmon/ppc-opc.c {"bcdadd.",	VX (4,1025),	VXPS_MASK,   PPCVEC2,	0,		{VD, VA, VB, PS}},
PPCVEC2          3518 arch/powerpc/xmon/ppc-opc.c {"vabsdub",	VX (4,1027),	VX_MASK,     PPCVEC2,	0,		{VD, VA, VB}},
PPCVEC2          3526 arch/powerpc/xmon/ppc-opc.c {"vpmsumb",	VX (4,1032),	VX_MASK,     PPCVEC2,	0,		{VD, VA, VB}},
PPCVEC2          3548 arch/powerpc/xmon/ppc-opc.c {"bcdsub.",	VX (4,1089),	VXPS_MASK,   PPCVEC2,	0,		{VD, VA, VB, PS}},
PPCVEC2          3550 arch/powerpc/xmon/ppc-opc.c {"vabsduh",	VX (4,1091),	VX_MASK,     PPCVEC2,	0,		{VD, VA, VB}},
PPCVEC2          3557 arch/powerpc/xmon/ppc-opc.c {"vpmsumh",	VX (4,1096),	VX_MASK,     PPCVEC2,	0,		{VD, VA, VB}},
PPCVEC2          3563 arch/powerpc/xmon/ppc-opc.c {"vpkudum",	VX (4,1102),	VX_MASK,     PPCVEC2,	0,		{VD, VA, VB}},
PPCVEC2          3587 arch/powerpc/xmon/ppc-opc.c {"vabsduw",	VX (4,1155),	VX_MASK,     PPCVEC2,	0,		{VD, VA, VB}},
PPCVEC2          3591 arch/powerpc/xmon/ppc-opc.c {"vpmsumw",	VX (4,1160),	VX_MASK,     PPCVEC2,	0,		{VD, VA, VB}},
PPCVEC2          3599 arch/powerpc/xmon/ppc-opc.c {"vsubudm",	VX (4,1216),	VX_MASK,     PPCVEC2,	0,		{VD, VA, VB}},
PPCVEC2          3610 arch/powerpc/xmon/ppc-opc.c {"vcmpequd.",	VXR(4, 199,1),	VXR_MASK,    PPCVEC2,	0,		{VD, VA, VB}},
PPCVEC2          3613 arch/powerpc/xmon/ppc-opc.c {"vpmsumd",	VX (4,1224),	VX_MASK,     PPCVEC2,	0,		{VD, VA, VB}},
PPCVEC2          3618 arch/powerpc/xmon/ppc-opc.c {"vpkudus",	VX (4,1230),	VX_MASK,     PPCVEC2,	0,		{VD, VA, VB}},
PPCVEC2          3625 arch/powerpc/xmon/ppc-opc.c {"vsubuqm",	VX (4,1280),	VX_MASK,     PPCVEC2,	0,		{VD, VA, VB}},
PPCVEC2          3640 arch/powerpc/xmon/ppc-opc.c {"vcipher",	VX (4,1288),	VX_MASK,     PPCVEC2,	0,		{VD, VA, VB}},
PPCVEC2          3641 arch/powerpc/xmon/ppc-opc.c {"vcipherlast",	VX (4,1289),	VX_MASK,     PPCVEC2,	0,		{VD, VA, VB}},
PPCVEC2          3644 arch/powerpc/xmon/ppc-opc.c {"vgbbd",	VX (4,1292),	VXVA_MASK,   PPCVEC2,	0,		{VD, VB}},
PPCVEC2          3656 arch/powerpc/xmon/ppc-opc.c {"vsubcuq",	VX (4,1344),	VX_MASK,     PPCVEC2,	0,		{VD, VA, VB}},
PPCVEC2          3661 arch/powerpc/xmon/ppc-opc.c {"vorc",	VX (4,1348),	VX_MASK,     PPCVEC2,	0,		{VD, VA, VB}},
PPCVEC2          3665 arch/powerpc/xmon/ppc-opc.c {"vncipher",	VX (4,1352),	VX_MASK,     PPCVEC2,	0,		{VD, VA, VB}},
PPCVEC2          3667 arch/powerpc/xmon/ppc-opc.c {"vncipherlast",VX (4,1353),	VX_MASK,     PPCVEC2,	0,		{VD, VA, VB}},
PPCVEC2          3669 arch/powerpc/xmon/ppc-opc.c {"vbpermq",	VX (4,1356),	VX_MASK,     PPCVEC2,	0,		{VD, VA, VB}},
PPCVEC2          3670 arch/powerpc/xmon/ppc-opc.c {"vpksdus",	VX (4,1358),	VX_MASK,     PPCVEC2,	0,		{VD, VA, VB}},
PPCVEC2          3691 arch/powerpc/xmon/ppc-opc.c {"vnand",	VX (4,1412),	VX_MASK,     PPCVEC2,	0,		{VD, VA, VB}},
PPCVEC2          3715 arch/powerpc/xmon/ppc-opc.c {"vsld",	VX (4,1476),	VX_MASK,     PPCVEC2,	0,		{VD, VA, VB}},
PPCVEC2          3719 arch/powerpc/xmon/ppc-opc.c {"vsbox",	VX (4,1480),	VXVB_MASK,   PPCVEC2,	0,		{VD, VA}},
PPCVEC2          3723 arch/powerpc/xmon/ppc-opc.c {"vpksdss",	VX (4,1486),	VX_MASK,     PPCVEC2,	0,		{VD, VA, VB}},
PPCVEC2          3762 arch/powerpc/xmon/ppc-opc.c {"vupkhsw",	VX (4,1614),	VXVA_MASK,   PPCVEC2,	0,		{VD, VB}},
PPCVEC2          3764 arch/powerpc/xmon/ppc-opc.c {"vshasigmaw",	VX (4,1666),	VX_MASK,     PPCVEC2,	0,		{VD, VA, ST, SIX}},
PPCVEC2          3765 arch/powerpc/xmon/ppc-opc.c {"veqv",	VX (4,1668),	VX_MASK,     PPCVEC2,	0,		{VD, VA, VB}},
PPCVEC2          3770 arch/powerpc/xmon/ppc-opc.c {"vmrgow",	VX (4,1676),	VX_MASK,     PPCVEC2,	0,		{VD, VA, VB}},
PPCVEC2          3772 arch/powerpc/xmon/ppc-opc.c {"vshasigmad",	VX (4,1730),	VX_MASK,     PPCVEC2,	0,		{VD, VA, ST, SIX}},
PPCVEC2          3773 arch/powerpc/xmon/ppc-opc.c {"vsrd",	VX (4,1732),	VX_MASK,     PPCVEC2,	0,		{VD, VA, VB}},
PPCVEC2          3776 arch/powerpc/xmon/ppc-opc.c {"vcmpgtud.",	VXR(4, 711,1),	VXR_MASK,    PPCVEC2,	0,		{VD, VA, VB}},
PPCVEC2          3778 arch/powerpc/xmon/ppc-opc.c {"vupklsw",	VX (4,1742),	VXVA_MASK,   PPCVEC2,	0,		{VD, VB}},
PPCVEC2          3780 arch/powerpc/xmon/ppc-opc.c {"vclzb",	VX (4,1794),	VXVA_MASK,   PPCVEC2,	0,		{VD, VB}},
PPCVEC2          3781 arch/powerpc/xmon/ppc-opc.c {"vpopcntb",	VX (4,1795),	VXVA_MASK,   PPCVEC2,	0,		{VD, VB}},
PPCVEC2          3791 arch/powerpc/xmon/ppc-opc.c {"vclzh",	VX (4,1858),	VXVA_MASK,   PPCVEC2,	0,		{VD, VB}},
PPCVEC2          3792 arch/powerpc/xmon/ppc-opc.c {"vpopcnth",	VX (4,1859),	VXVA_MASK,   PPCVEC2,	0,		{VD, VB}},
PPCVEC2          3803 arch/powerpc/xmon/ppc-opc.c {"vclzw",	VX (4,1922),	VXVA_MASK,   PPCVEC2,	0,		{VD, VB}},
PPCVEC2          3804 arch/powerpc/xmon/ppc-opc.c {"vpopcntw",	VX (4,1923),	VXVA_MASK,   PPCVEC2,	0,		{VD, VB}},
PPCVEC2          3809 arch/powerpc/xmon/ppc-opc.c {"vmrgew",	VX (4,1932),	VX_MASK,     PPCVEC2,	0,		{VD, VA, VB}},
PPCVEC2          3813 arch/powerpc/xmon/ppc-opc.c {"vclzd",	VX (4,1986),	VXVA_MASK,   PPCVEC2,	0,		{VD, VB}},
PPCVEC2          3814 arch/powerpc/xmon/ppc-opc.c {"vpopcntd",	VX (4,1987),	VXVA_MASK,   PPCVEC2,	0,		{VD, VB}},
PPCVEC2          3817 arch/powerpc/xmon/ppc-opc.c {"vcmpgtsd.",	VXR(4, 967,1),	VXR_MASK,    PPCVEC2,	0,		{VD, VA, VB}},
PPCVEC2          4773 arch/powerpc/xmon/ppc-opc.c {"mviwsplt",	X(31,46),	X_MASK,	     PPCVEC2,	0,		{VD, RA, RB}},
PPCVEC2          4869 arch/powerpc/xmon/ppc-opc.c {"mvidsplt",	X(31,110),	X_MASK,	     PPCVEC2,	0,		{VD, RA, RB}},
PPCVEC2          5069 arch/powerpc/xmon/ppc-opc.c {"lvexbx",	X(31,261),	X_MASK,	     PPCVEC2,	0,		{VD, RA0, RB}},
PPCVEC2          5073 arch/powerpc/xmon/ppc-opc.c {"lvepxl",	X(31,263),	X_MASK,	     PPCVEC2,	0,		{VD, RA0, RB}},
PPCVEC2          5119 arch/powerpc/xmon/ppc-opc.c {"lvexhx",	X(31,293),	X_MASK,	     PPCVEC2,	0,		{VD, RA0, RB}},
PPCVEC2          5120 arch/powerpc/xmon/ppc-opc.c {"lvepx",	X(31,295),	X_MASK,	     PPCVEC2,	0,		{VD, RA0, RB}},
PPCVEC2          5183 arch/powerpc/xmon/ppc-opc.c {"lvexwx",	X(31,325),	X_MASK,	     PPCVEC2,	0,		{VD, RA0, RB}},
PPCVEC2          5432 arch/powerpc/xmon/ppc-opc.c {"stvexbx",	X(31,389),	X_MASK,	     PPCVEC2,	0,		{VS, RA0, RB}},
PPCVEC2          5465 arch/powerpc/xmon/ppc-opc.c {"stvexhx",	X(31,421),	X_MASK,	     PPCVEC2,	0,		{VS, RA0, RB}},
PPCVEC2          5537 arch/powerpc/xmon/ppc-opc.c {"stvexwx",	X(31,453),	X_MASK,	     PPCVEC2,	0,		{VS, RA0, RB}},
PPCVEC2          5808 arch/powerpc/xmon/ppc-opc.c {"lvtrx",	X(31,549),	X_MASK,	     PPCVEC2,	0,		{VD, RA0, RB}},
PPCVEC2          5832 arch/powerpc/xmon/ppc-opc.c {"lvtlx",	X(31,581),	X_MASK,	     PPCVEC2,	0,		{VD, RA0, RB}},
PPCVEC2          5862 arch/powerpc/xmon/ppc-opc.c {"lvswx",	X(31,613),	X_MASK,	     PPCVEC2,	0,		{VD, RA0, RB}},
PPCVEC2          5921 arch/powerpc/xmon/ppc-opc.c {"stvfrx",	X(31,677),	X_MASK,	     PPCVEC2,	0,		{VS, RA0, RB}},
PPCVEC2          5939 arch/powerpc/xmon/ppc-opc.c {"stvflx",	X(31,709),	X_MASK,	     PPCVEC2,	0,		{VS, RA0, RB}},
PPCVEC2          5977 arch/powerpc/xmon/ppc-opc.c {"stvswx",	X(31,741),	X_MASK,	     PPCVEC2,	0,		{VS, RA0, RB}},
PPCVEC2          6015 arch/powerpc/xmon/ppc-opc.c {"lvsm",	X(31,773),	X_MASK,	     PPCVEC2,	0,		{VD, RA0, RB}},
PPCVEC2          6019 arch/powerpc/xmon/ppc-opc.c {"stvepxl",	X(31,775),	X_MASK,	     PPCVEC2,	0,		{VS, RA0, RB}},
PPCVEC2          6058 arch/powerpc/xmon/ppc-opc.c {"lvtrxl",	X(31,805),	X_MASK,	     PPCVEC2,	0,		{VD, RA0, RB}},
PPCVEC2          6059 arch/powerpc/xmon/ppc-opc.c {"stvepx",	X(31,807),	X_MASK,	     PPCVEC2,	0,		{VS, RA0, RB}},
PPCVEC2          6085 arch/powerpc/xmon/ppc-opc.c {"lvtlxl",	X(31,837),	X_MASK,	     PPCVEC2,	0,		{VD, RA0, RB}},
PPCVEC2          6112 arch/powerpc/xmon/ppc-opc.c {"lvswxl",	X(31,869),	X_MASK,	     PPCVEC2,	0,		{VD, RA0, RB}},
PPCVEC2          6176 arch/powerpc/xmon/ppc-opc.c {"stvfrxl",	X(31,933),	X_MASK,	     PPCVEC2,	0,		{VS, RA0, RB}},
PPCVEC2          6211 arch/powerpc/xmon/ppc-opc.c {"stvflxl",	X(31,965),	X_MASK,	     PPCVEC2,	0,		{VS, RA0, RB}},
PPCVEC2          6243 arch/powerpc/xmon/ppc-opc.c {"stvswxl",	X(31,997),	X_MASK,	     PPCVEC2,	0,		{VS, RA0, RB}},