PPCSPE 3260 arch/powerpc/xmon/ppc-opc.c {"evaddw", VX (4, 512), VX_MASK, PPCSPE, 0, {RS, RA, RB}}, PPCSPE 3263 arch/powerpc/xmon/ppc-opc.c {"evaddiw", VX (4, 514), VX_MASK, PPCSPE, 0, {RS, RB, UIMM}}, PPCSPE 3265 arch/powerpc/xmon/ppc-opc.c {"evsubfw", VX (4, 516), VX_MASK, PPCSPE, 0, {RS, RA, RB}}, PPCSPE 3266 arch/powerpc/xmon/ppc-opc.c {"evsubw", VX (4, 516), VX_MASK, PPCSPE, 0, {RS, RB, RA}}, PPCSPE 3268 arch/powerpc/xmon/ppc-opc.c {"evsubifw", VX (4, 518), VX_MASK, PPCSPE, 0, {RS, UIMM, RB}}, PPCSPE 3269 arch/powerpc/xmon/ppc-opc.c {"evsubiw", VX (4, 518), VX_MASK, PPCSPE, 0, {RS, RB, UIMM}}, PPCSPE 3271 arch/powerpc/xmon/ppc-opc.c {"evabs", VX (4, 520), VX_MASK, PPCSPE, 0, {RS, RA}}, PPCSPE 3273 arch/powerpc/xmon/ppc-opc.c {"evneg", VX (4, 521), VX_MASK, PPCSPE, 0, {RS, RA}}, PPCSPE 3274 arch/powerpc/xmon/ppc-opc.c {"evextsb", VX (4, 522), VX_MASK, PPCSPE, 0, {RS, RA}}, PPCSPE 3276 arch/powerpc/xmon/ppc-opc.c {"evextsh", VX (4, 523), VX_MASK, PPCSPE, 0, {RS, RA}}, PPCSPE 3277 arch/powerpc/xmon/ppc-opc.c {"evrndw", VX (4, 524), VX_MASK, PPCSPE, 0, {RS, RA}}, PPCSPE 3280 arch/powerpc/xmon/ppc-opc.c {"evcntlzw", VX (4, 525), VX_MASK, PPCSPE, 0, {RS, RA}}, PPCSPE 3281 arch/powerpc/xmon/ppc-opc.c {"evcntlsw", VX (4, 526), VX_MASK, PPCSPE, 0, {RS, RA}}, PPCSPE 3283 arch/powerpc/xmon/ppc-opc.c {"brinc", VX (4, 527), VX_MASK, PPCSPE, 0, {RS, RA, RB}}, PPCSPE 3286 arch/powerpc/xmon/ppc-opc.c {"evand", VX (4, 529), VX_MASK, PPCSPE, 0, {RS, RA, RB}}, PPCSPE 3287 arch/powerpc/xmon/ppc-opc.c {"evandc", VX (4, 530), VX_MASK, PPCSPE, 0, {RS, RA, RB}}, PPCSPE 3288 arch/powerpc/xmon/ppc-opc.c {"evxor", VX (4, 534), VX_MASK, PPCSPE, 0, {RS, RA, RB}}, PPCSPE 3289 arch/powerpc/xmon/ppc-opc.c {"evmr", VX (4, 535), VX_MASK, PPCSPE, 0, {RS, RA, BBA}}, PPCSPE 3290 arch/powerpc/xmon/ppc-opc.c {"evor", VX (4, 535), VX_MASK, PPCSPE, 0, {RS, RA, RB}}, PPCSPE 3291 arch/powerpc/xmon/ppc-opc.c {"evnor", VX (4, 536), VX_MASK, PPCSPE, 0, {RS, RA, RB}}, PPCSPE 3292 arch/powerpc/xmon/ppc-opc.c {"evnot", VX (4, 536), VX_MASK, PPCSPE, 0, {RS, RA, BBA}}, PPCSPE 3294 arch/powerpc/xmon/ppc-opc.c {"eveqv", VX (4, 537), VX_MASK, PPCSPE, 0, {RS, RA, RB}}, PPCSPE 3295 arch/powerpc/xmon/ppc-opc.c {"evorc", VX (4, 539), VX_MASK, PPCSPE, 0, {RS, RA, RB}}, PPCSPE 3296 arch/powerpc/xmon/ppc-opc.c {"evnand", VX (4, 542), VX_MASK, PPCSPE, 0, {RS, RA, RB}}, PPCSPE 3297 arch/powerpc/xmon/ppc-opc.c {"evsrwu", VX (4, 544), VX_MASK, PPCSPE, 0, {RS, RA, RB}}, PPCSPE 3298 arch/powerpc/xmon/ppc-opc.c {"evsrws", VX (4, 545), VX_MASK, PPCSPE, 0, {RS, RA, RB}}, PPCSPE 3299 arch/powerpc/xmon/ppc-opc.c {"evsrwiu", VX (4, 546), VX_MASK, PPCSPE, 0, {RS, RA, EVUIMM}}, PPCSPE 3300 arch/powerpc/xmon/ppc-opc.c {"evsrwis", VX (4, 547), VX_MASK, PPCSPE, 0, {RS, RA, EVUIMM}}, PPCSPE 3301 arch/powerpc/xmon/ppc-opc.c {"evslw", VX (4, 548), VX_MASK, PPCSPE, 0, {RS, RA, RB}}, PPCSPE 3302 arch/powerpc/xmon/ppc-opc.c {"evslwi", VX (4, 550), VX_MASK, PPCSPE, 0, {RS, RA, EVUIMM}}, PPCSPE 3303 arch/powerpc/xmon/ppc-opc.c {"evrlw", VX (4, 552), VX_MASK, PPCSPE, 0, {RS, RA, RB}}, PPCSPE 3304 arch/powerpc/xmon/ppc-opc.c {"evsplati", VX (4, 553), VX_MASK, PPCSPE, 0, {RS, SIMM}}, PPCSPE 3305 arch/powerpc/xmon/ppc-opc.c {"evrlwi", VX (4, 554), VX_MASK, PPCSPE, 0, {RS, RA, EVUIMM}}, PPCSPE 3306 arch/powerpc/xmon/ppc-opc.c {"evsplatfi", VX (4, 555), VX_MASK, PPCSPE, 0, {RS, SIMM}}, PPCSPE 3307 arch/powerpc/xmon/ppc-opc.c {"evmergehi", VX (4, 556), VX_MASK, PPCSPE, 0, {RS, RA, RB}}, PPCSPE 3308 arch/powerpc/xmon/ppc-opc.c {"evmergelo", VX (4, 557), VX_MASK, PPCSPE, 0, {RS, RA, RB}}, PPCSPE 3309 arch/powerpc/xmon/ppc-opc.c {"evmergehilo", VX (4, 558), VX_MASK, PPCSPE, 0, {RS, RA, RB}}, PPCSPE 3310 arch/powerpc/xmon/ppc-opc.c {"evmergelohi", VX (4, 559), VX_MASK, PPCSPE, 0, {RS, RA, RB}}, PPCSPE 3311 arch/powerpc/xmon/ppc-opc.c {"evcmpgtu", VX (4, 560), VX_MASK, PPCSPE, 0, {CRFD, RA, RB}}, PPCSPE 3312 arch/powerpc/xmon/ppc-opc.c {"evcmpgts", VX (4, 561), VX_MASK, PPCSPE, 0, {CRFD, RA, RB}}, PPCSPE 3313 arch/powerpc/xmon/ppc-opc.c {"evcmpltu", VX (4, 562), VX_MASK, PPCSPE, 0, {CRFD, RA, RB}}, PPCSPE 3314 arch/powerpc/xmon/ppc-opc.c {"evcmplts", VX (4, 563), VX_MASK, PPCSPE, 0, {CRFD, RA, RB}}, PPCSPE 3315 arch/powerpc/xmon/ppc-opc.c {"evcmpeq", VX (4, 564), VX_MASK, PPCSPE, 0, {CRFD, RA, RB}}, PPCSPE 3328 arch/powerpc/xmon/ppc-opc.c {"evsel", EVSEL(4,79), EVSEL_MASK, PPCSPE, 0, {RS, RA, RB, CRFS}}, PPCSPE 3330 arch/powerpc/xmon/ppc-opc.c {"evfsadd", VX (4, 640), VX_MASK, PPCSPE, 0, {RS, RA, RB}}, PPCSPE 3332 arch/powerpc/xmon/ppc-opc.c {"evfssub", VX (4, 641), VX_MASK, PPCSPE, 0, {RS, RA, RB}}, PPCSPE 3334 arch/powerpc/xmon/ppc-opc.c {"evfsabs", VX (4, 644), VX_MASK, PPCSPE, 0, {RS, RA}}, PPCSPE 3336 arch/powerpc/xmon/ppc-opc.c {"evfsnabs", VX (4, 645), VX_MASK, PPCSPE, 0, {RS, RA}}, PPCSPE 3337 arch/powerpc/xmon/ppc-opc.c {"evfsneg", VX (4, 646), VX_MASK, PPCSPE, 0, {RS, RA}}, PPCSPE 3340 arch/powerpc/xmon/ppc-opc.c {"evfsmul", VX (4, 648), VX_MASK, PPCSPE, 0, {RS, RA, RB}}, PPCSPE 3341 arch/powerpc/xmon/ppc-opc.c {"evfsdiv", VX (4, 649), VX_MASK, PPCSPE, 0, {RS, RA, RB}}, PPCSPE 3343 arch/powerpc/xmon/ppc-opc.c {"evfscmpgt", VX (4, 652), VX_MASK, PPCSPE, 0, {CRFD, RA, RB}}, PPCSPE 3346 arch/powerpc/xmon/ppc-opc.c {"evfscmplt", VX (4, 653), VX_MASK, PPCSPE, 0, {CRFD, RA, RB}}, PPCSPE 3347 arch/powerpc/xmon/ppc-opc.c {"evfscmpeq", VX (4, 654), VX_MASK, PPCSPE, 0, {CRFD, RA, RB}}, PPCSPE 3349 arch/powerpc/xmon/ppc-opc.c {"evfscfui", VX (4, 656), VX_MASK, PPCSPE, 0, {RS, RB}}, PPCSPE 3350 arch/powerpc/xmon/ppc-opc.c {"evfscfsi", VX (4, 657), VX_MASK, PPCSPE, 0, {RS, RB}}, PPCSPE 3351 arch/powerpc/xmon/ppc-opc.c {"evfscfuf", VX (4, 658), VX_MASK, PPCSPE, 0, {RS, RB}}, PPCSPE 3352 arch/powerpc/xmon/ppc-opc.c {"evfscfsf", VX (4, 659), VX_MASK, PPCSPE, 0, {RS, RB}}, PPCSPE 3353 arch/powerpc/xmon/ppc-opc.c {"evfsctui", VX (4, 660), VX_MASK, PPCSPE, 0, {RS, RB}}, PPCSPE 3354 arch/powerpc/xmon/ppc-opc.c {"evfsctsi", VX (4, 661), VX_MASK, PPCSPE, 0, {RS, RB}}, PPCSPE 3355 arch/powerpc/xmon/ppc-opc.c {"evfsctuf", VX (4, 662), VX_MASK, PPCSPE, 0, {RS, RB}}, PPCSPE 3356 arch/powerpc/xmon/ppc-opc.c {"evfsctsf", VX (4, 663), VX_MASK, PPCSPE, 0, {RS, RB}}, PPCSPE 3357 arch/powerpc/xmon/ppc-opc.c {"evfsctuiz", VX (4, 664), VX_MASK, PPCSPE, 0, {RS, RB}}, PPCSPE 3359 arch/powerpc/xmon/ppc-opc.c {"evfsctsiz", VX (4, 666), VX_MASK, PPCSPE, 0, {RS, RB}}, PPCSPE 3360 arch/powerpc/xmon/ppc-opc.c {"evfststgt", VX (4, 668), VX_MASK, PPCSPE, 0, {CRFD, RA, RB}}, PPCSPE 3361 arch/powerpc/xmon/ppc-opc.c {"evfststlt", VX (4, 669), VX_MASK, PPCSPE, 0, {CRFD, RA, RB}}, PPCSPE 3362 arch/powerpc/xmon/ppc-opc.c {"evfststeq", VX (4, 670), VX_MASK, PPCSPE, 0, {CRFD, RA, RB}}, PPCSPE 3425 arch/powerpc/xmon/ppc-opc.c {"evlddx", VX (4, 768), VX_MASK, PPCSPE, 0, {RS, RA, RB}}, PPCSPE 3427 arch/powerpc/xmon/ppc-opc.c {"evldd", VX (4, 769), VX_MASK, PPCSPE, 0, {RS, EVUIMM_8, RA}}, PPCSPE 3428 arch/powerpc/xmon/ppc-opc.c {"evldwx", VX (4, 770), VX_MASK, PPCSPE, 0, {RS, RA, RB}}, PPCSPE 3430 arch/powerpc/xmon/ppc-opc.c {"evldw", VX (4, 771), VX_MASK, PPCSPE, 0, {RS, EVUIMM_8, RA}}, PPCSPE 3431 arch/powerpc/xmon/ppc-opc.c {"evldhx", VX (4, 772), VX_MASK, PPCSPE, 0, {RS, RA, RB}}, PPCSPE 3433 arch/powerpc/xmon/ppc-opc.c {"evldh", VX (4, 773), VX_MASK, PPCSPE, 0, {RS, EVUIMM_8, RA}}, PPCSPE 3435 arch/powerpc/xmon/ppc-opc.c {"evlhhesplatx",VX (4, 776), VX_MASK, PPCSPE, 0, {RS, RA, RB}}, PPCSPE 3437 arch/powerpc/xmon/ppc-opc.c {"evlhhesplat", VX (4, 777), VX_MASK, PPCSPE, 0, {RS, EVUIMM_2, RA}}, PPCSPE 3440 arch/powerpc/xmon/ppc-opc.c {"evlhhousplatx",VX(4, 780), VX_MASK, PPCSPE, 0, {RS, RA, RB}}, PPCSPE 3443 arch/powerpc/xmon/ppc-opc.c {"evlhhousplat",VX (4, 781), VX_MASK, PPCSPE, 0, {RS, EVUIMM_2, RA}}, PPCSPE 3444 arch/powerpc/xmon/ppc-opc.c {"evlhhossplatx",VX(4, 782), VX_MASK, PPCSPE, 0, {RS, RA, RB}}, PPCSPE 3446 arch/powerpc/xmon/ppc-opc.c {"evlhhossplat",VX (4, 783), VX_MASK, PPCSPE, 0, {RS, EVUIMM_2, RA}}, PPCSPE 3448 arch/powerpc/xmon/ppc-opc.c {"evlwhex", VX (4, 784), VX_MASK, PPCSPE, 0, {RS, RA, RB}}, PPCSPE 3450 arch/powerpc/xmon/ppc-opc.c {"evlwhe", VX (4, 785), VX_MASK, PPCSPE, 0, {RS, EVUIMM_4, RA}}, PPCSPE 3451 arch/powerpc/xmon/ppc-opc.c {"evlwhoux", VX (4, 788), VX_MASK, PPCSPE, 0, {RS, RA, RB}}, PPCSPE 3452 arch/powerpc/xmon/ppc-opc.c {"evlwhou", VX (4, 789), VX_MASK, PPCSPE, 0, {RS, EVUIMM_4, RA}}, PPCSPE 3453 arch/powerpc/xmon/ppc-opc.c {"evlwhosx", VX (4, 790), VX_MASK, PPCSPE, 0, {RS, RA, RB}}, PPCSPE 3454 arch/powerpc/xmon/ppc-opc.c {"evlwhos", VX (4, 791), VX_MASK, PPCSPE, 0, {RS, EVUIMM_4, RA}}, PPCSPE 3456 arch/powerpc/xmon/ppc-opc.c {"evlwwsplatx", VX (4, 792), VX_MASK, PPCSPE, 0, {RS, RA, RB}}, PPCSPE 3458 arch/powerpc/xmon/ppc-opc.c {"evlwwsplat", VX (4, 793), VX_MASK, PPCSPE, 0, {RS, EVUIMM_4, RA}}, PPCSPE 3459 arch/powerpc/xmon/ppc-opc.c {"evlwhsplatx", VX (4, 796), VX_MASK, PPCSPE, 0, {RS, RA, RB}}, PPCSPE 3460 arch/powerpc/xmon/ppc-opc.c {"evlwhsplat", VX (4, 797), VX_MASK, PPCSPE, 0, {RS, EVUIMM_4, RA}}, PPCSPE 3461 arch/powerpc/xmon/ppc-opc.c {"evstddx", VX (4, 800), VX_MASK, PPCSPE, 0, {RS, RA, RB}}, PPCSPE 3462 arch/powerpc/xmon/ppc-opc.c {"evstdd", VX (4, 801), VX_MASK, PPCSPE, 0, {RS, EVUIMM_8, RA}}, PPCSPE 3463 arch/powerpc/xmon/ppc-opc.c {"evstdwx", VX (4, 802), VX_MASK, PPCSPE, 0, {RS, RA, RB}}, PPCSPE 3464 arch/powerpc/xmon/ppc-opc.c {"evstdw", VX (4, 803), VX_MASK, PPCSPE, 0, {RS, EVUIMM_8, RA}}, PPCSPE 3465 arch/powerpc/xmon/ppc-opc.c {"evstdhx", VX (4, 804), VX_MASK, PPCSPE, 0, {RS, RA, RB}}, PPCSPE 3466 arch/powerpc/xmon/ppc-opc.c {"evstdh", VX (4, 805), VX_MASK, PPCSPE, 0, {RS, EVUIMM_8, RA}}, PPCSPE 3467 arch/powerpc/xmon/ppc-opc.c {"evstwhex", VX (4, 816), VX_MASK, PPCSPE, 0, {RS, RA, RB}}, PPCSPE 3468 arch/powerpc/xmon/ppc-opc.c {"evstwhe", VX (4, 817), VX_MASK, PPCSPE, 0, {RS, EVUIMM_4, RA}}, PPCSPE 3469 arch/powerpc/xmon/ppc-opc.c {"evstwhox", VX (4, 820), VX_MASK, PPCSPE, 0, {RS, RA, RB}}, PPCSPE 3470 arch/powerpc/xmon/ppc-opc.c {"evstwho", VX (4, 821), VX_MASK, PPCSPE, 0, {RS, EVUIMM_4, RA}}, PPCSPE 3471 arch/powerpc/xmon/ppc-opc.c {"evstwwex", VX (4, 824), VX_MASK, PPCSPE, 0, {RS, RA, RB}}, PPCSPE 3472 arch/powerpc/xmon/ppc-opc.c {"evstwwe", VX (4, 825), VX_MASK, PPCSPE, 0, {RS, EVUIMM_4, RA}}, PPCSPE 3473 arch/powerpc/xmon/ppc-opc.c {"evstwwox", VX (4, 828), VX_MASK, PPCSPE, 0, {RS, RA, RB}}, PPCSPE 3474 arch/powerpc/xmon/ppc-opc.c {"evstwwo", VX (4, 829), VX_MASK, PPCSPE, 0, {RS, EVUIMM_4, RA}}, PPCSPE 3519 arch/powerpc/xmon/ppc-opc.c {"evmhessf", VX (4,1027), VX_MASK, PPCSPE, 0, {RS, RA, RB}}, PPCSPE 3525 arch/powerpc/xmon/ppc-opc.c {"evmhossf", VX (4,1031), VX_MASK, PPCSPE, 0, {RS, RA, RB}}, PPCSPE 3527 arch/powerpc/xmon/ppc-opc.c {"evmheumi", VX (4,1032), VX_MASK, PPCSPE, 0, {RS, RA, RB}}, PPCSPE 3528 arch/powerpc/xmon/ppc-opc.c {"evmhesmi", VX (4,1033), VX_MASK, PPCSPE, 0, {RS, RA, RB}}, PPCSPE 3530 arch/powerpc/xmon/ppc-opc.c {"evmhesmf", VX (4,1035), VX_MASK, PPCSPE, 0, {RS, RA, RB}}, PPCSPE 3531 arch/powerpc/xmon/ppc-opc.c {"evmhoumi", VX (4,1036), VX_MASK, PPCSPE, 0, {RS, RA, RB}}, PPCSPE 3533 arch/powerpc/xmon/ppc-opc.c {"evmhosmi", VX (4,1037), VX_MASK, PPCSPE, 0, {RS, RA, RB}}, PPCSPE 3534 arch/powerpc/xmon/ppc-opc.c {"evmhosmf", VX (4,1039), VX_MASK, PPCSPE, 0, {RS, RA, RB}}, PPCSPE 3539 arch/powerpc/xmon/ppc-opc.c {"evmhessfa", VX (4,1059), VX_MASK, PPCSPE, 0, {RS, RA, RB}}, PPCSPE 3540 arch/powerpc/xmon/ppc-opc.c {"evmhossfa", VX (4,1063), VX_MASK, PPCSPE, 0, {RS, RA, RB}}, PPCSPE 3541 arch/powerpc/xmon/ppc-opc.c {"evmheumia", VX (4,1064), VX_MASK, PPCSPE, 0, {RS, RA, RB}}, PPCSPE 3542 arch/powerpc/xmon/ppc-opc.c {"evmhesmia", VX (4,1065), VX_MASK, PPCSPE, 0, {RS, RA, RB}}, PPCSPE 3543 arch/powerpc/xmon/ppc-opc.c {"evmhesmfa", VX (4,1067), VX_MASK, PPCSPE, 0, {RS, RA, RB}}, PPCSPE 3544 arch/powerpc/xmon/ppc-opc.c {"evmhoumia", VX (4,1068), VX_MASK, PPCSPE, 0, {RS, RA, RB}}, PPCSPE 3545 arch/powerpc/xmon/ppc-opc.c {"evmhosmia", VX (4,1069), VX_MASK, PPCSPE, 0, {RS, RA, RB}}, PPCSPE 3546 arch/powerpc/xmon/ppc-opc.c {"evmhosmfa", VX (4,1071), VX_MASK, PPCSPE, 0, {RS, RA, RB}}, PPCSPE 3556 arch/powerpc/xmon/ppc-opc.c {"evmwhssf", VX (4,1095), VX_MASK, PPCSPE, 0, {RS, RA, RB}}, PPCSPE 3558 arch/powerpc/xmon/ppc-opc.c {"evmwlumi", VX (4,1096), VX_MASK, PPCSPE, 0, {RS, RA, RB}}, PPCSPE 3560 arch/powerpc/xmon/ppc-opc.c {"evmwhumi", VX (4,1100), VX_MASK, PPCSPE, 0, {RS, RA, RB}}, PPCSPE 3562 arch/powerpc/xmon/ppc-opc.c {"evmwhsmi", VX (4,1101), VX_MASK, PPCSPE, 0, {RS, RA, RB}}, PPCSPE 3564 arch/powerpc/xmon/ppc-opc.c {"evmwhsmf", VX (4,1103), VX_MASK, PPCSPE, 0, {RS, RA, RB}}, PPCSPE 3565 arch/powerpc/xmon/ppc-opc.c {"evmwssf", VX (4,1107), VX_MASK, PPCSPE, 0, {RS, RA, RB}}, PPCSPE 3567 arch/powerpc/xmon/ppc-opc.c {"evmwumi", VX (4,1112), VX_MASK, PPCSPE, 0, {RS, RA, RB}}, PPCSPE 3569 arch/powerpc/xmon/ppc-opc.c {"evmwsmi", VX (4,1113), VX_MASK, PPCSPE, 0, {RS, RA, RB}}, PPCSPE 3570 arch/powerpc/xmon/ppc-opc.c {"evmwsmf", VX (4,1115), VX_MASK, PPCSPE, 0, {RS, RA, RB}}, PPCSPE 3575 arch/powerpc/xmon/ppc-opc.c {"evmwhssfa", VX (4,1127), VX_MASK, PPCSPE, 0, {RS, RA, RB}}, PPCSPE 3576 arch/powerpc/xmon/ppc-opc.c {"evmwlumia", VX (4,1128), VX_MASK, PPCSPE, 0, {RS, RA, RB}}, PPCSPE 3577 arch/powerpc/xmon/ppc-opc.c {"evmwhumia", VX (4,1132), VX_MASK, PPCSPE, 0, {RS, RA, RB}}, PPCSPE 3578 arch/powerpc/xmon/ppc-opc.c {"evmwhsmia", VX (4,1133), VX_MASK, PPCSPE, 0, {RS, RA, RB}}, PPCSPE 3579 arch/powerpc/xmon/ppc-opc.c {"evmwhsmfa", VX (4,1135), VX_MASK, PPCSPE, 0, {RS, RA, RB}}, PPCSPE 3580 arch/powerpc/xmon/ppc-opc.c {"evmwssfa", VX (4,1139), VX_MASK, PPCSPE, 0, {RS, RA, RB}}, PPCSPE 3581 arch/powerpc/xmon/ppc-opc.c {"evmwumia", VX (4,1144), VX_MASK, PPCSPE, 0, {RS, RA, RB}}, PPCSPE 3582 arch/powerpc/xmon/ppc-opc.c {"evmwsmia", VX (4,1145), VX_MASK, PPCSPE, 0, {RS, RA, RB}}, PPCSPE 3583 arch/powerpc/xmon/ppc-opc.c {"evmwsmfa", VX (4,1147), VX_MASK, PPCSPE, 0, {RS, RA, RB}}, PPCSPE 3600 arch/powerpc/xmon/ppc-opc.c {"evaddusiaaw", VX (4,1216), VX_MASK, PPCSPE, 0, {RS, RA}}, PPCSPE 3602 arch/powerpc/xmon/ppc-opc.c {"evaddssiaaw", VX (4,1217), VX_MASK, PPCSPE, 0, {RS, RA}}, PPCSPE 3603 arch/powerpc/xmon/ppc-opc.c {"evsubfusiaaw",VX (4,1218), VX_MASK, PPCSPE, 0, {RS, RA}}, PPCSPE 3604 arch/powerpc/xmon/ppc-opc.c {"evsubfssiaaw",VX (4,1219), VX_MASK, PPCSPE, 0, {RS, RA}}, PPCSPE 3605 arch/powerpc/xmon/ppc-opc.c {"evmra", VX (4,1220), VX_MASK, PPCSPE, 0, {RS, RA}}, PPCSPE 3607 arch/powerpc/xmon/ppc-opc.c {"evdivws", VX (4,1222), VX_MASK, PPCSPE, 0, {RS, RA, RB}}, PPCSPE 3612 arch/powerpc/xmon/ppc-opc.c {"evdivwu", VX (4,1223), VX_MASK, PPCSPE, 0, {RS, RA, RB}}, PPCSPE 3614 arch/powerpc/xmon/ppc-opc.c {"evaddumiaaw", VX (4,1224), VX_MASK, PPCSPE, 0, {RS, RA}}, PPCSPE 3615 arch/powerpc/xmon/ppc-opc.c {"evaddsmiaaw", VX (4,1225), VX_MASK, PPCSPE, 0, {RS, RA}}, PPCSPE 3616 arch/powerpc/xmon/ppc-opc.c {"evsubfumiaaw",VX (4,1226), VX_MASK, PPCSPE, 0, {RS, RA}}, PPCSPE 3617 arch/powerpc/xmon/ppc-opc.c {"evsubfsmiaaw",VX (4,1227), VX_MASK, PPCSPE, 0, {RS, RA}}, PPCSPE 3626 arch/powerpc/xmon/ppc-opc.c {"evmheusiaaw", VX (4,1280), VX_MASK, PPCSPE, 0, {RS, RA, RB}}, PPCSPE 3628 arch/powerpc/xmon/ppc-opc.c {"evmhessiaaw", VX (4,1281), VX_MASK, PPCSPE, 0, {RS, RA, RB}}, PPCSPE 3630 arch/powerpc/xmon/ppc-opc.c {"evmhessfaaw", VX (4,1283), VX_MASK, PPCSPE, 0, {RS, RA, RB}}, PPCSPE 3631 arch/powerpc/xmon/ppc-opc.c {"evmhousiaaw", VX (4,1284), VX_MASK, PPCSPE, 0, {RS, RA, RB}}, PPCSPE 3634 arch/powerpc/xmon/ppc-opc.c {"evmhossiaaw", VX (4,1285), VX_MASK, PPCSPE, 0, {RS, RA, RB}}, PPCSPE 3638 arch/powerpc/xmon/ppc-opc.c {"evmhossfaaw", VX (4,1287), VX_MASK, PPCSPE, 0, {RS, RA, RB}}, PPCSPE 3639 arch/powerpc/xmon/ppc-opc.c {"evmheumiaaw", VX (4,1288), VX_MASK, PPCSPE, 0, {RS, RA, RB}}, PPCSPE 3642 arch/powerpc/xmon/ppc-opc.c {"evmhesmiaaw", VX (4,1289), VX_MASK, PPCSPE, 0, {RS, RA, RB}}, PPCSPE 3643 arch/powerpc/xmon/ppc-opc.c {"evmhesmfaaw", VX (4,1291), VX_MASK, PPCSPE, 0, {RS, RA, RB}}, PPCSPE 3645 arch/powerpc/xmon/ppc-opc.c {"evmhoumiaaw", VX (4,1292), VX_MASK, PPCSPE, 0, {RS, RA, RB}}, PPCSPE 3646 arch/powerpc/xmon/ppc-opc.c {"evmhosmiaaw", VX (4,1293), VX_MASK, PPCSPE, 0, {RS, RA, RB}}, PPCSPE 3647 arch/powerpc/xmon/ppc-opc.c {"evmhosmfaaw", VX (4,1295), VX_MASK, PPCSPE, 0, {RS, RA, RB}}, PPCSPE 3650 arch/powerpc/xmon/ppc-opc.c {"evmhegumiaa", VX (4,1320), VX_MASK, PPCSPE, 0, {RS, RA, RB}}, PPCSPE 3651 arch/powerpc/xmon/ppc-opc.c {"evmhegsmiaa", VX (4,1321), VX_MASK, PPCSPE, 0, {RS, RA, RB}}, PPCSPE 3652 arch/powerpc/xmon/ppc-opc.c {"evmhegsmfaa", VX (4,1323), VX_MASK, PPCSPE, 0, {RS, RA, RB}}, PPCSPE 3653 arch/powerpc/xmon/ppc-opc.c {"evmhogumiaa", VX (4,1324), VX_MASK, PPCSPE, 0, {RS, RA, RB}}, PPCSPE 3654 arch/powerpc/xmon/ppc-opc.c {"evmhogsmiaa", VX (4,1325), VX_MASK, PPCSPE, 0, {RS, RA, RB}}, PPCSPE 3655 arch/powerpc/xmon/ppc-opc.c {"evmhogsmfaa", VX (4,1327), VX_MASK, PPCSPE, 0, {RS, RA, RB}}, PPCSPE 3657 arch/powerpc/xmon/ppc-opc.c {"evmwlusiaaw", VX (4,1344), VX_MASK, PPCSPE, 0, {RS, RA, RB}}, PPCSPE 3659 arch/powerpc/xmon/ppc-opc.c {"evmwlssiaaw", VX (4,1345), VX_MASK, PPCSPE, 0, {RS, RA, RB}}, PPCSPE 3666 arch/powerpc/xmon/ppc-opc.c {"evmwlumiaaw", VX (4,1352), VX_MASK, PPCSPE, 0, {RS, RA, RB}}, PPCSPE 3668 arch/powerpc/xmon/ppc-opc.c {"evmwlsmiaaw", VX (4,1353), VX_MASK, PPCSPE, 0, {RS, RA, RB}}, PPCSPE 3671 arch/powerpc/xmon/ppc-opc.c {"evmwssfaa", VX (4,1363), VX_MASK, PPCSPE, 0, {RS, RA, RB}}, PPCSPE 3673 arch/powerpc/xmon/ppc-opc.c {"evmwumiaa", VX (4,1368), VX_MASK, PPCSPE, 0, {RS, RA, RB}}, PPCSPE 3675 arch/powerpc/xmon/ppc-opc.c {"evmwsmiaa", VX (4,1369), VX_MASK, PPCSPE, 0, {RS, RA, RB}}, PPCSPE 3676 arch/powerpc/xmon/ppc-opc.c {"evmwsmfaa", VX (4,1371), VX_MASK, PPCSPE, 0, {RS, RA, RB}}, PPCSPE 3679 arch/powerpc/xmon/ppc-opc.c {"evmheusianw", VX (4,1408), VX_MASK, PPCSPE, 0, {RS, RA, RB}}, PPCSPE 3681 arch/powerpc/xmon/ppc-opc.c {"evmhessianw", VX (4,1409), VX_MASK, PPCSPE, 0, {RS, RA, RB}}, PPCSPE 3690 arch/powerpc/xmon/ppc-opc.c {"evmhessfanw", VX (4,1411), VX_MASK, PPCSPE, 0, {RS, RA, RB}}, PPCSPE 3692 arch/powerpc/xmon/ppc-opc.c {"evmhousianw", VX (4,1412), VX_MASK, PPCSPE, 0, {RS, RA, RB}}, PPCSPE 3693 arch/powerpc/xmon/ppc-opc.c {"evmhossianw", VX (4,1413), VX_MASK, PPCSPE, 0, {RS, RA, RB}}, PPCSPE 3697 arch/powerpc/xmon/ppc-opc.c {"evmhossfanw", VX (4,1415), VX_MASK, PPCSPE, 0, {RS, RA, RB}}, PPCSPE 3698 arch/powerpc/xmon/ppc-opc.c {"evmheumianw", VX (4,1416), VX_MASK, PPCSPE, 0, {RS, RA, RB}}, PPCSPE 3699 arch/powerpc/xmon/ppc-opc.c {"evmhesmianw", VX (4,1417), VX_MASK, PPCSPE, 0, {RS, RA, RB}}, PPCSPE 3700 arch/powerpc/xmon/ppc-opc.c {"evmhesmfanw", VX (4,1419), VX_MASK, PPCSPE, 0, {RS, RA, RB}}, PPCSPE 3701 arch/powerpc/xmon/ppc-opc.c {"evmhoumianw", VX (4,1420), VX_MASK, PPCSPE, 0, {RS, RA, RB}}, PPCSPE 3702 arch/powerpc/xmon/ppc-opc.c {"evmhosmianw", VX (4,1421), VX_MASK, PPCSPE, 0, {RS, RA, RB}}, PPCSPE 3703 arch/powerpc/xmon/ppc-opc.c {"evmhosmfanw", VX (4,1423), VX_MASK, PPCSPE, 0, {RS, RA, RB}}, PPCSPE 3706 arch/powerpc/xmon/ppc-opc.c {"evmhegumian", VX (4,1448), VX_MASK, PPCSPE, 0, {RS, RA, RB}}, PPCSPE 3707 arch/powerpc/xmon/ppc-opc.c {"evmhegsmian", VX (4,1449), VX_MASK, PPCSPE, 0, {RS, RA, RB}}, PPCSPE 3708 arch/powerpc/xmon/ppc-opc.c {"evmhegsmfan", VX (4,1451), VX_MASK, PPCSPE, 0, {RS, RA, RB}}, PPCSPE 3709 arch/powerpc/xmon/ppc-opc.c {"evmhogumian", VX (4,1452), VX_MASK, PPCSPE, 0, {RS, RA, RB}}, PPCSPE 3710 arch/powerpc/xmon/ppc-opc.c {"evmhogsmian", VX (4,1453), VX_MASK, PPCSPE, 0, {RS, RA, RB}}, PPCSPE 3711 arch/powerpc/xmon/ppc-opc.c {"evmhogsmfan", VX (4,1455), VX_MASK, PPCSPE, 0, {RS, RA, RB}}, PPCSPE 3712 arch/powerpc/xmon/ppc-opc.c {"evmwlusianw", VX (4,1472), VX_MASK, PPCSPE, 0, {RS, RA, RB}}, PPCSPE 3714 arch/powerpc/xmon/ppc-opc.c {"evmwlssianw", VX (4,1473), VX_MASK, PPCSPE, 0, {RS, RA, RB}}, PPCSPE 3720 arch/powerpc/xmon/ppc-opc.c {"evmwlumianw", VX (4,1480), VX_MASK, PPCSPE, 0, {RS, RA, RB}}, PPCSPE 3721 arch/powerpc/xmon/ppc-opc.c {"evmwlsmianw", VX (4,1481), VX_MASK, PPCSPE, 0, {RS, RA, RB}}, PPCSPE 3724 arch/powerpc/xmon/ppc-opc.c {"evmwssfan", VX (4,1491), VX_MASK, PPCSPE, 0, {RS, RA, RB}}, PPCSPE 3726 arch/powerpc/xmon/ppc-opc.c {"evmwumian", VX (4,1496), VX_MASK, PPCSPE, 0, {RS, RA, RB}}, PPCSPE 3728 arch/powerpc/xmon/ppc-opc.c {"evmwsmian", VX (4,1497), VX_MASK, PPCSPE, 0, {RS, RA, RB}}, PPCSPE 3729 arch/powerpc/xmon/ppc-opc.c {"evmwsmfan", VX (4,1499), VX_MASK, PPCSPE, 0, {RS, RA, RB}}, PPCSPE 5285 arch/powerpc/xmon/ppc-opc.c {"mfspefscr", XSPR(31,339,512), XSPR_MASK, PPCSPE, 0, {RT}}, PPCSPE 5288 arch/powerpc/xmon/ppc-opc.c {"mfivor32", XSPR(31,339,528), XSPR_MASK, PPCSPE, 0, {RT}}, PPCSPE 5290 arch/powerpc/xmon/ppc-opc.c {"mfivor33", XSPR(31,339,529), XSPR_MASK, PPCSPE, 0, {RT}}, PPCSPE 5292 arch/powerpc/xmon/ppc-opc.c {"mfivor34", XSPR(31,339,530), XSPR_MASK, PPCSPE, 0, {RT}}, PPCSPE 5638 arch/powerpc/xmon/ppc-opc.c {"mtspefscr", XSPR(31,467,512), XSPR_MASK, PPCSPE, 0, {RS}}, PPCSPE 5641 arch/powerpc/xmon/ppc-opc.c {"mtivor32", XSPR(31,467,528), XSPR_MASK, PPCSPE, 0, {RS}}, PPCSPE 5643 arch/powerpc/xmon/ppc-opc.c {"mtivor33", XSPR(31,467,529), XSPR_MASK, PPCSPE, 0, {RS}}, PPCSPE 5645 arch/powerpc/xmon/ppc-opc.c {"mtivor34", XSPR(31,467,530), XSPR_MASK, PPCSPE, 0, {RS}},